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arm64: Add more headers for code compilation

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This makes ARM64 target compile more files. This patch is one of
series of patches to support new architecture, as fixes in many
places are required just to compile the code.

Signed-off-by: Jaroslaw Pelczar <jarek@jpelczar.com>
Change-Id: Ia060612733cd3a0fcb781fec449da164ed635b8e
Reviewed-on: https://review.haiku-os.org/c/haiku/+/1807
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>
This commit is contained in:
Jaroslaw Pelczar 2019-08-30 23:04:29 +02:00 committed by waddlesplash
parent ef21ae46d9
commit 1761cb8e6f
28 changed files with 1444 additions and 5 deletions
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16
headers/os/arch/arm64/arch_debugger.h Normal file
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@ -0,0 +1,16 @@
/*
* Copyright 2019 Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _ARCH_ARM64_DEBUGGER_H
#define _ARCH_ARM64_DEBUGGER_H
struct arm64_debug_cpu_state {
unsigned long x[30];
unsigned long lr;
unsigned long sp;
unsigned long elr;
unsigned int spsr;
} __attribute__((aligned(16)));
#endif // _ARCH_ARM_DEBUGGER_H

3
headers/os/kernel/debugger.h
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@ -18,6 +18,7 @@
#include <arch/m68k/arch_debugger.h> #include <arch/m68k/arch_debugger.h>
#include <arch/mipsel/arch_debugger.h> #include <arch/mipsel/arch_debugger.h>
#include <arch/arm/arch_debugger.h> #include <arch/arm/arch_debugger.h>
#include <arch/arm64/arch_debugger.h>
#include <arch/riscv64/arch_debugger.h> #include <arch/riscv64/arch_debugger.h>
#include <arch/sparc/arch_debugger.h> #include <arch/sparc/arch_debugger.h>
@ -38,6 +39,8 @@
typedef struct riscv64_debug_cpu_state debug_cpu_state; typedef struct riscv64_debug_cpu_state debug_cpu_state;
#elif defined(__sparc64__) #elif defined(__sparc64__)
typedef struct sparc_debug_cpu_state debug_cpu_state; typedef struct sparc_debug_cpu_state debug_cpu_state;
#elif defined(__aarch64__) || defined(__arm64__)
typedef struct arm64_debug_cpu_state debug_cpu_state;
#else #else
#error unsupported architecture #error unsupported architecture
#endif #endif

6
headers/private/kernel/arch/arm64/arch_cpu.h
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@ -12,7 +12,7 @@
#define set_ac() #define set_ac()
#define clear_ac() #define clear_ac()
#include <kernel/arch/arm64/armreg.h> #include <kernel/arch/arm64/arm_registers.h>
#ifndef _ASSEMBLER #ifndef _ASSEMBLER
@ -104,7 +104,7 @@ arm64_address_translate_ ##stage (uint64 addr) \
uint64 ret; \ uint64 ret; \
\ \
__asm __volatile( \ __asm __volatile( \
"at " __STRING(stage) ", %1 \n" \ "at " __ARMREG_STRING(stage) ", %1 \n" \
"mrs %0, par_el1" : "=r"(ret) : "r"(addr)); \ "mrs %0, par_el1" : "=r"(ret) : "r"(addr)); \
\ \
return (ret); \ return (ret); \
@ -125,6 +125,7 @@ struct iframe {
uint64 x[30]; uint64 x[30];
}; };
#ifdef __cplusplus
namespace BKernel { namespace BKernel {
struct Thread; struct Thread;
} // namespace BKernel } // namespace BKernel
@ -133,6 +134,7 @@ typedef struct arch_cpu_info {
uint32 mpidr; uint32 mpidr;
BKernel::Thread* last_vfp_user; BKernel::Thread* last_vfp_user;
} arch_cpu_info; } arch_cpu_info;
#endif
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {

664
headers/private/kernel/arch/arm64/arm_registers.h Normal file
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@ -0,0 +1,664 @@
/*-
* Copyright (c) 2013, 2014 Andrew Turner
* Copyright (c) 2015 The FreeBSD Foundation
* All rights reserved.
*
* This software was developed by Andrew Turner under
* sponsorship from the FreeBSD Foundation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_ARMREG_H_
#define _MACHINE_ARMREG_H_
#define INSN_SIZE 4
#define __ARMREG_STRING(x) #x
#define READ_SPECIALREG(reg) \
({ uint64_t val; \
__asm __volatile("mrs %0, " __ARMREG_STRING(reg) : "=&r" (val)); \
val; \
})
#define WRITE_SPECIALREG(reg, val) \
__asm __volatile("msr " __ARMREG_STRING(reg) ", %0" : : "r"((uint64_t)val))
/* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
#define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */
#define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */
#define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */
#define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */
#define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/
/* CPACR_EL1 */
#define CPACR_FPEN_MASK (0x3 << 20)
#define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */
#define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */
#define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */
#define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */
#define CPACR_TTA (0x1 << 28)
/* CTR_EL0 - Cache Type Register */
#define CTR_DLINE_SHIFT 16
#define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT)
#define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT)
#define CTR_ILINE_SHIFT 0
#define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT)
#define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT)
/* DAIF - Interrupt Mask Bits */
#define DAIF_D_MASKED (1 << 9)
#define DAIF_A_MASKED (1 << 8)
#define DAIF_I_MASKED (1 << 7)
#define DAIF_F_MASKED (1 << 6)
/* DCZID_EL0 - Data Cache Zero ID register */
#define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */
#define DCZID_BS_SHIFT 0
#define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT)
#define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT)
/* ESR_ELx */
#define ESR_ELx_ISS_MASK 0x00ffffff
#define ISS_INSN_FnV (0x01 << 10)
#define ISS_INSN_EA (0x01 << 9)
#define ISS_INSN_S1PTW (0x01 << 7)
#define ISS_INSN_IFSC_MASK (0x1f << 0)
#define ISS_DATA_ISV (0x01 << 24)
#define ISS_DATA_SAS_MASK (0x03 << 22)
#define ISS_DATA_SSE (0x01 << 21)
#define ISS_DATA_SRT_MASK (0x1f << 16)
#define ISS_DATA_SF (0x01 << 15)
#define ISS_DATA_AR (0x01 << 14)
#define ISS_DATA_FnV (0x01 << 10)
#define ISS_DATa_EA (0x01 << 9)
#define ISS_DATa_CM (0x01 << 8)
#define ISS_INSN_S1PTW (0x01 << 7)
#define ISS_DATa_WnR (0x01 << 6)
#define ISS_DATA_DFSC_MASK (0x3f << 0)
#define ISS_DATA_DFSC_ASF_L0 (0x00 << 0)
#define ISS_DATA_DFSC_ASF_L1 (0x01 << 0)
#define ISS_DATA_DFSC_ASF_L2 (0x02 << 0)
#define ISS_DATA_DFSC_ASF_L3 (0x03 << 0)
#define ISS_DATA_DFSC_TF_L0 (0x04 << 0)
#define ISS_DATA_DFSC_TF_L1 (0x05 << 0)
#define ISS_DATA_DFSC_TF_L2 (0x06 << 0)
#define ISS_DATA_DFSC_TF_L3 (0x07 << 0)
#define ISS_DATA_DFSC_AFF_L1 (0x09 << 0)
#define ISS_DATA_DFSC_AFF_L2 (0x0a << 0)
#define ISS_DATA_DFSC_AFF_L3 (0x0b << 0)
#define ISS_DATA_DFSC_PF_L1 (0x0d << 0)
#define ISS_DATA_DFSC_PF_L2 (0x0e << 0)
#define ISS_DATA_DFSC_PF_L3 (0x0f << 0)
#define ISS_DATA_DFSC_EXT (0x10 << 0)
#define ISS_DATA_DFSC_EXT_L0 (0x14 << 0)
#define ISS_DATA_DFSC_EXT_L1 (0x15 << 0)
#define ISS_DATA_DFSC_EXT_L2 (0x16 << 0)
#define ISS_DATA_DFSC_EXT_L3 (0x17 << 0)
#define ISS_DATA_DFSC_ECC (0x18 << 0)
#define ISS_DATA_DFSC_ECC_L0 (0x1c << 0)
#define ISS_DATA_DFSC_ECC_L1 (0x1d << 0)
#define ISS_DATA_DFSC_ECC_L2 (0x1e << 0)
#define ISS_DATA_DFSC_ECC_L3 (0x1f << 0)
#define ISS_DATA_DFSC_ALIGN (0x21 << 0)
#define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0)
#define ESR_ELx_IL (0x01 << 25)
#define ESR_ELx_EC_SHIFT 26
#define ESR_ELx_EC_MASK (0x3f << 26)
#define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
#define EXCP_UNKNOWN 0x00 /* Unkwn exception */
#define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */
#define EXCP_ILL_STATE 0x0e /* Illegal execution state */
#define EXCP_SVC32 0x11 /* SVC trap for AArch32 */
#define EXCP_SVC64 0x15 /* SVC trap for AArch64 */
#define EXCP_MSR 0x18 /* MSR/MRS trap */
#define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */
#define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */
#define EXCP_PC_ALIGN 0x22 /* PC alignment fault */
#define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */
#define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */
#define EXCP_SP_ALIGN 0x26 /* SP slignment fault */
#define EXCP_TRAP_FP 0x2c /* Trapped FP exception */
#define EXCP_SERROR 0x2f /* SError interrupt */
#define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */
#define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */
#define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */
#define EXCP_BRK 0x3c /* Breakpoint */
/* ICC_CTLR_EL1 */
#define ICC_CTLR_EL1_EOIMODE (1U << 1)
/* ICC_IAR1_EL1 */
#define ICC_IAR1_EL1_SPUR (0x03ff)
/* ICC_IGRPEN0_EL1 */
#define ICC_IGRPEN0_EL1_EN (1U << 0)
/* ICC_PMR_EL1 */
#define ICC_PMR_EL1_PRIO_MASK (0xFFUL)
/* ICC_SGI1R_EL1 */
#define ICC_SGI1R_EL1_TL_MASK 0xffffUL
#define ICC_SGI1R_EL1_AFF1_SHIFT 16
#define ICC_SGI1R_EL1_SGIID_SHIFT 24
#define ICC_SGI1R_EL1_AFF2_SHIFT 32
#define ICC_SGI1R_EL1_AFF3_SHIFT 48
#define ICC_SGI1R_EL1_SGIID_MASK 0xfUL
#define ICC_SGI1R_EL1_IRM (0x1UL << 40)
/* ICC_SRE_EL1 */
#define ICC_SRE_EL1_SRE (1U << 0)
/* ICC_SRE_EL2 */
#define ICC_SRE_EL2_SRE (1U << 0)
#define ICC_SRE_EL2_EN (1U << 3)
/* ID_AA64DFR0_EL1 */
#define ID_AA64DFR0_MASK 0x0000000ff0f0fffful
#define ID_AA64DFR0_DEBUG_VER_SHIFT 0
#define ID_AA64DFR0_DEBUG_VER_MASK (0xf << ID_AA64DFR0_DEBUG_VER_SHIFT)
#define ID_AA64DFR0_DEBUG_VER(x) ((x) & ID_AA64DFR0_DEBUG_VER_MASK)
#define ID_AA64DFR0_DEBUG_VER_8 (0x6 << ID_AA64DFR0_DEBUG_VER_SHIFT)
#define ID_AA64DFR0_DEBUG_VER_8_VHE (0x7 << ID_AA64DFR0_DEBUG_VER_SHIFT)
#define ID_AA64DFR0_DEBUG_VER_8_2 (0x8 << ID_AA64DFR0_DEBUG_VER_SHIFT)
#define ID_AA64DFR0_TRACE_VER_SHIFT 4
#define ID_AA64DFR0_TRACE_VER_MASK (0xf << ID_AA64DFR0_TRACE_VER_SHIFT)
#define ID_AA64DFR0_TRACE_VER(x) ((x) & ID_AA64DFR0_TRACE_VER_MASK)
#define ID_AA64DFR0_TRACE_VER_NONE (0x0 << ID_AA64DFR0_TRACE_VER_SHIFT)
#define ID_AA64DFR0_TRACE_VER_IMPL (0x1 << ID_AA64DFR0_TRACE_VER_SHIFT)
#define ID_AA64DFR0_PMU_VER_SHIFT 8
#define ID_AA64DFR0_PMU_VER_MASK (0xf << ID_AA64DFR0_PMU_VER_SHIFT)
#define ID_AA64DFR0_PMU_VER(x) ((x) & ID_AA64DFR0_PMU_VER_MASK)
#define ID_AA64DFR0_PMU_VER_NONE (0x0 << ID_AA64DFR0_PMU_VER_SHIFT)
#define ID_AA64DFR0_PMU_VER_3 (0x1 << ID_AA64DFR0_PMU_VER_SHIFT)
#define ID_AA64DFR0_PMU_VER_3_1 (0x4 << ID_AA64DFR0_PMU_VER_SHIFT)
#define ID_AA64DFR0_PMU_VER_IMPL (0xf << ID_AA64DFR0_PMU_VER_SHIFT)
#define ID_AA64DFR0_BRPS_SHIFT 12
#define ID_AA64DFR0_BRPS_MASK (0xf << ID_AA64DFR0_BRPS_SHIFT)
#define ID_AA64DFR0_BRPS(x) \
((((x) >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) + 1)
#define ID_AA64DFR0_WRPS_SHIFT 20
#define ID_AA64DFR0_WRPS_MASK (0xf << ID_AA64DFR0_WRPS_SHIFT)
#define ID_AA64DFR0_WRPS(x) \
((((x) >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) + 1)
#define ID_AA64DFR0_CTX_CMPS_SHIFT 28
#define ID_AA64DFR0_CTX_CMPS_MASK (0xf << ID_AA64DFR0_CTX_CMPS_SHIFT)
#define ID_AA64DFR0_CTX_CMPS(x) \
((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1)
#define ID_AA64DFR0_PMS_VER_SHIFT 32
#define ID_AA64DFR0_PMS_VER_MASK (0xful << ID_AA64DFR0_PMS_VER_SHIFT)
#define ID_AA64DFR0_PMS_VER(x) ((x) & ID_AA64DFR0_PMS_VER_MASK)
#define ID_AA64DFR0_PMS_VER_NONE (0x0ul << ID_AA64DFR0_PMS_VER_SHIFT)
#define ID_AA64DFR0_PMS_VER_V1 (0x1ul << ID_AA64DFR0_PMS_VER_SHIFT)
/* ID_AA64ISAR0_EL1 */
#define ID_AA64ISAR0_MASK 0x0000fffff0fffff0ul
#define ID_AA64ISAR0_AES_SHIFT 4
#define ID_AA64ISAR0_AES_MASK (0xf << ID_AA64ISAR0_AES_SHIFT)
#define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK)
#define ID_AA64ISAR0_AES_NONE (0x0 << ID_AA64ISAR0_AES_SHIFT)
#define ID_AA64ISAR0_AES_BASE (0x1 << ID_AA64ISAR0_AES_SHIFT)
#define ID_AA64ISAR0_AES_PMULL (0x2 << ID_AA64ISAR0_AES_SHIFT)
#define ID_AA64ISAR0_SHA1_SHIFT 8
#define ID_AA64ISAR0_SHA1_MASK (0xf << ID_AA64ISAR0_SHA1_SHIFT)
#define ID_AA64ISAR0_SHA1(x) ((x) & ID_AA64ISAR0_SHA1_MASK)
#define ID_AA64ISAR0_SHA1_NONE (0x0 << ID_AA64ISAR0_SHA1_SHIFT)
#define ID_AA64ISAR0_SHA1_BASE (0x1 << ID_AA64ISAR0_SHA1_SHIFT)
#define ID_AA64ISAR0_SHA2_SHIFT 12
#define ID_AA64ISAR0_SHA2_MASK (0xf << ID_AA64ISAR0_SHA2_SHIFT)
#define ID_AA64ISAR0_SHA2(x) ((x) & ID_AA64ISAR0_SHA2_MASK)
#define ID_AA64ISAR0_SHA2_NONE (0x0 << ID_AA64ISAR0_SHA2_SHIFT)
#define ID_AA64ISAR0_SHA2_BASE (0x1 << ID_AA64ISAR0_SHA2_SHIFT)
#define ID_AA64ISAR0_SHA2_512 (0x2 << ID_AA64ISAR0_SHA2_SHIFT)
#define ID_AA64ISAR0_CRC32_SHIFT 16
#define ID_AA64ISAR0_CRC32_MASK (0xf << ID_AA64ISAR0_CRC32_SHIFT)
#define ID_AA64ISAR0_CRC32(x) ((x) & ID_AA64ISAR0_CRC32_MASK)
#define ID_AA64ISAR0_CRC32_NONE (0x0 << ID_AA64ISAR0_CRC32_SHIFT)
#define ID_AA64ISAR0_CRC32_BASE (0x1 << ID_AA64ISAR0_CRC32_SHIFT)
#define ID_AA64ISAR0_ATOMIC_SHIFT 20
#define ID_AA64ISAR0_ATOMIC_MASK (0xf << ID_AA64ISAR0_ATOMIC_SHIFT)
#define ID_AA64ISAR0_ATOMIC(x) ((x) & ID_AA64ISAR0_ATOMIC_MASK)
#define ID_AA64ISAR0_ATOMIC_NONE (0x0 << ID_AA64ISAR0_ATOMIC_SHIFT)
#define ID_AA64ISAR0_ATOMIC_IMPL (0x2 << ID_AA64ISAR0_ATOMIC_SHIFT)
#define ID_AA64ISAR0_RDM_SHIFT 28
#define ID_AA64ISAR0_RDM_MASK (0xf << ID_AA64ISAR0_RDM_SHIFT)
#define ID_AA64ISAR0_RDM(x) ((x) & ID_AA64ISAR0_RDM_MASK)
#define ID_AA64ISAR0_RDM_NONE (0x0 << ID_AA64ISAR0_RDM_SHIFT)
#define ID_AA64ISAR0_RDM_IMPL (0x1 << ID_AA64ISAR0_RDM_SHIFT)
#define ID_AA64ISAR0_SHA3_SHIFT 32
#define ID_AA64ISAR0_SHA3_MASK (0xful << ID_AA64ISAR0_SHA3_SHIFT)
#define ID_AA64ISAR0_SHA3(x) ((x) & ID_AA64ISAR0_SHA3_MASK)
#define ID_AA64ISAR0_SHA3_NONE (0x0ul << ID_AA64ISAR0_SHA3_SHIFT)
#define ID_AA64ISAR0_SHA3_IMPL (0x1ul << ID_AA64ISAR0_SHA3_SHIFT)
#define ID_AA64ISAR0_SM3_SHIFT 36
#define ID_AA64ISAR0_SM3_MASK (0xful << ID_AA64ISAR0_SM3_SHIFT)
#define ID_AA64ISAR0_SM3(x) ((x) & ID_AA64ISAR0_SM3_MASK)
#define ID_AA64ISAR0_SM3_NONE (0x0ul << ID_AA64ISAR0_SM3_SHIFT)
#define ID_AA64ISAR0_SM3_IMPL (0x1ul << ID_AA64ISAR0_SM3_SHIFT)
#define ID_AA64ISAR0_SM4_SHIFT 40
#define ID_AA64ISAR0_SM4_MASK (0xful << ID_AA64ISAR0_SM4_SHIFT)
#define ID_AA64ISAR0_SM4(x) ((x) & ID_AA64ISAR0_SM4_MASK)
#define ID_AA64ISAR0_SM4_NONE (0x0ul << ID_AA64ISAR0_SM4_SHIFT)
#define ID_AA64ISAR0_SM4_IMPL (0x1ul << ID_AA64ISAR0_SM4_SHIFT)
#define ID_AA64ISAR0_DP_SHIFT 44
#define ID_AA64ISAR0_DP_MASK (0xful << ID_AA64ISAR0_DP_SHIFT)
#define ID_AA64ISAR0_DP(x) ((x) & ID_AA64ISAR0_DP_MASK)
#define ID_AA64ISAR0_DP_NONE (0x0ul << ID_AA64ISAR0_DP_SHIFT)
#define ID_AA64ISAR0_DP_IMPL (0x1ul << ID_AA64ISAR0_DP_SHIFT)
/* ID_AA64ISAR1_EL1 */
#define ID_AA64ISAR1_MASK 0xffffffff
#define ID_AA64ISAR1_DPB_SHIFT 0
#define ID_AA64ISAR1_DPB_MASK (0xf << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_DPB(x) ((x) & ID_AA64ISAR1_DPB_MASK)
#define ID_AA64ISAR1_DPB_NONE (0x0 << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_DPB_IMPL (0x1 << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_APA_SHIFT 4
#define ID_AA64ISAR1_APA_MASK (0xf << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_APA(x) ((x) & ID_AA64ISAR1_APA_MASK)
#define ID_AA64ISAR1_APA_NONE (0x0 << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_APA_IMPL (0x1 << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_API_SHIFT 8
#define ID_AA64ISAR1_API_MASK (0xf << ID_AA64ISAR1_API_SHIFT)
#define ID_AA64ISAR1_API(x) ((x) & ID_AA64ISAR1_API_MASK)
#define ID_AA64ISAR1_API_NONE (0x0 << ID_AA64ISAR1_API_SHIFT)
#define ID_AA64ISAR1_API_IMPL (0x1 << ID_AA64ISAR1_API_SHIFT)
#define ID_AA64ISAR1_JSCVT_SHIFT 12
#define ID_AA64ISAR1_JSCVT_MASK (0xf << ID_AA64ISAR1_JSCVT_SHIFT)
#define ID_AA64ISAR1_JSCVT(x) ((x) & ID_AA64ISAR1_JSCVT_MASK)
#define ID_AA64ISAR1_JSCVT_NONE (0x0 << ID_AA64ISAR1_JSCVT_SHIFT)
#define ID_AA64ISAR1_JSCVT_IMPL (0x1 << ID_AA64ISAR1_JSCVT_SHIFT)
#define ID_AA64ISAR1_FCMA_SHIFT 16
#define ID_AA64ISAR1_FCMA_MASK (0xf << ID_AA64ISAR1_FCMA_SHIFT)
#define ID_AA64ISAR1_FCMA(x) ((x) & ID_AA64ISAR1_FCMA_MASK)
#define ID_AA64ISAR1_FCMA_NONE (0x0 << ID_AA64ISAR1_FCMA_SHIFT)
#define ID_AA64ISAR1_FCMA_IMPL (0x1 << ID_AA64ISAR1_FCMA_SHIFT)
#define ID_AA64ISAR1_LRCPC_SHIFT 20
#define ID_AA64ISAR1_LRCPC_MASK (0xf << ID_AA64ISAR1_LRCPC_SHIFT)
#define ID_AA64ISAR1_LRCPC(x) ((x) & ID_AA64ISAR1_LRCPC_MASK)
#define ID_AA64ISAR1_LRCPC_NONE (0x0 << ID_AA64ISAR1_LRCPC_SHIFT)
#define ID_AA64ISAR1_LRCPC_IMPL (0x1 << ID_AA64ISAR1_LRCPC_SHIFT)
#define ID_AA64ISAR1_GPA_SHIFT 24
#define ID_AA64ISAR1_GPA_MASK (0xf << ID_AA64ISAR1_GPA_SHIFT)
#define ID_AA64ISAR1_GPA(x) ((x) & ID_AA64ISAR1_GPA_MASK)
#define ID_AA64ISAR1_GPA_NONE (0x0 << ID_AA64ISAR1_GPA_SHIFT)
#define ID_AA64ISAR1_GPA_IMPL (0x1 << ID_AA64ISAR1_GPA_SHIFT)
#define ID_AA64ISAR1_GPI_SHIFT 28
#define ID_AA64ISAR1_GPI_MASK (0xf << ID_AA64ISAR1_GPI_SHIFT)
#define ID_AA64ISAR1_GPI(x) ((x) & ID_AA64ISAR1_GPI_MASK)
#define ID_AA64ISAR1_GPI_NONE (0x0 << ID_AA64ISAR1_GPI_SHIFT)
#define ID_AA64ISAR1_GPI_IMPL (0x1 << ID_AA64ISAR1_GPI_SHIFT)
/* ID_AA64MMFR0_EL1 */
#define ID_AA64MMFR0_MASK 0xffffffff
#define ID_AA64MMFR0_PA_RANGE_SHIFT 0
#define ID_AA64MMFR0_PA_RANGE_MASK (0xf << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_PA_RANGE(x) ((x) & ID_AA64MMFR0_PA_RANGE_MASK)
#define ID_AA64MMFR0_PA_RANGE_4G (0x0 << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_PA_RANGE_64G (0x1 << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_PA_RANGE_1T (0x2 << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_PA_RANGE_4T (0x3 << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_PA_RANGE_16T (0x4 << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_PA_RANGE_256T (0x5 << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_PA_RANGE_4P (0x6 << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_ASID_BITS_SHIFT 4
#define ID_AA64MMFR0_ASID_BITS_MASK (0xf << ID_AA64MMFR0_ASID_BITS_SHIFT)
#define ID_AA64MMFR0_ASID_BITS(x) ((x) & ID_AA64MMFR0_ASID_BITS_MASK)
#define ID_AA64MMFR0_ASID_BITS_8 (0x0 << ID_AA64MMFR0_ASID_BITS_SHIFT)
#define ID_AA64MMFR0_ASID_BITS_16 (0x2 << ID_AA64MMFR0_ASID_BITS_SHIFT)
#define ID_AA64MMFR0_BIGEND_SHIFT 8
#define ID_AA64MMFR0_BIGEND_MASK (0xf << ID_AA64MMFR0_BIGEND_SHIFT)
#define ID_AA64MMFR0_BIGEND(x) ((x) & ID_AA64MMFR0_BIGEND_MASK)
#define ID_AA64MMFR0_BIGEND_FIXED (0x0 << ID_AA64MMFR0_BIGEND_SHIFT)
#define ID_AA64MMFR0_BIGEND_MIXED (0x1 << ID_AA64MMFR0_BIGEND_SHIFT)
#define ID_AA64MMFR0_S_NS_MEM_SHIFT 12
#define ID_AA64MMFR0_S_NS_MEM_MASK (0xf << ID_AA64MMFR0_S_NS_MEM_SHIFT)
#define ID_AA64MMFR0_S_NS_MEM(x) ((x) & ID_AA64MMFR0_S_NS_MEM_MASK)
#define ID_AA64MMFR0_S_NS_MEM_NONE (0x0 << ID_AA64MMFR0_S_NS_MEM_SHIFT)
#define ID_AA64MMFR0_S_NS_MEM_DISTINCT (0x1 << ID_AA64MMFR0_S_NS_MEM_SHIFT)
#define ID_AA64MMFR0_BIGEND_EL0_SHIFT 16
#define ID_AA64MMFR0_BIGEND_EL0_MASK (0xf << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
#define ID_AA64MMFR0_BIGEND_EL0(x) ((x) & ID_AA64MMFR0_BIGEND_EL0_MASK)
#define ID_AA64MMFR0_BIGEND_EL0_FIXED (0x0 << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
#define ID_AA64MMFR0_BIGEND_EL0_MIXED (0x1 << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
#define ID_AA64MMFR0_TGRAN16_SHIFT 20
#define ID_AA64MMFR0_TGRAN16_MASK (0xf << ID_AA64MMFR0_TGRAN16_SHIFT)
#define ID_AA64MMFR0_TGRAN16(x) ((x) & ID_AA64MMFR0_TGRAN16_MASK)
#define ID_AA64MMFR0_TGRAN16_NONE (0x0 << ID_AA64MMFR0_TGRAN16_SHIFT)
#define ID_AA64MMFR0_TGRAN16_IMPL (0x1 << ID_AA64MMFR0_TGRAN16_SHIFT)
#define ID_AA64MMFR0_TGRAN64_SHIFT 24
#define ID_AA64MMFR0_TGRAN64_MASK (0xf << ID_AA64MMFR0_TGRAN64_SHIFT)
#define ID_AA64MMFR0_TGRAN64(x) ((x) & ID_AA64MMFR0_TGRAN64_MASK)
#define ID_AA64MMFR0_TGRAN64_IMPL (0x0 << ID_AA64MMFR0_TGRAN64_SHIFT)
#define ID_AA64MMFR0_TGRAN64_NONE (0xf << ID_AA64MMFR0_TGRAN64_SHIFT)
#define ID_AA64MMFR0_TGRAN4_SHIFT 28
#define ID_AA64MMFR0_TGRAN4_MASK (0xf << ID_AA64MMFR0_TGRAN4_SHIFT)
#define ID_AA64MMFR0_TGRAN4(x) ((x) & ID_AA64MMFR0_TGRAN4_MASK)
#define ID_AA64MMFR0_TGRAN4_IMPL (0x0 << ID_AA64MMFR0_TGRAN4_SHIFT)
#define ID_AA64MMFR0_TGRAN4_NONE (0xf << ID_AA64MMFR0_TGRAN4_SHIFT)
/* ID_AA64MMFR1_EL1 */
#define ID_AA64MMFR1_MASK 0xffffffff
#define ID_AA64MMFR1_HAFDBS_SHIFT 0
#define ID_AA64MMFR1_HAFDBS_MASK (0xf << ID_AA64MMFR1_HAFDBS_SHIFT)
#define ID_AA64MMFR1_HAFDBS(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK)
#define ID_AA64MMFR1_HAFDBS_NONE (0x0 << ID_AA64MMFR1_HAFDBS_SHIFT)
#define ID_AA64MMFR1_HAFDBS_AF (0x1 << ID_AA64MMFR1_HAFDBS_SHIFT)
#define ID_AA64MMFR1_HAFDBS_AF_DBS (0x2 << ID_AA64MMFR1_HAFDBS_SHIFT)
#define ID_AA64MMFR1_VMIDBITS_SHIFT 4
#define ID_AA64MMFR1_VMIDBITS_MASK (0xf << ID_AA64MMFR1_VMIDBITS_SHIFT)
#define ID_AA64MMFR1_VMIDBITS(x) ((x) & ID_AA64MMFR1_VMIDBITS_MASK)
#define ID_AA64MMFR1_VMIDBITS_8 (0x0 << ID_AA64MMFR1_VMIDBITS_SHIFT)
#define ID_AA64MMFR1_VMIDBITS_16 (0x2 << ID_AA64MMFR1_VMIDBITS_SHIFT)
#define ID_AA64MMFR1_VH_SHIFT 8
#define ID_AA64MMFR1_VH_MASK (0xf << ID_AA64MMFR1_VH_SHIFT)
#define ID_AA64MMFR1_VH(x) ((x) & ID_AA64MMFR1_VH_MASK)
#define ID_AA64MMFR1_VH_NONE (0x0 << ID_AA64MMFR1_VH_SHIFT)
#define ID_AA64MMFR1_VH_IMPL (0x1 << ID_AA64MMFR1_VH_SHIFT)
#define ID_AA64MMFR1_HPDS_SHIFT 12
#define ID_AA64MMFR1_HPDS_MASK (0xf << ID_AA64MMFR1_HPDS_SHIFT)
#define ID_AA64MMFR1_HPDS(x) ((x) & ID_AA64MMFR1_HPDS_MASK)
#define ID_AA64MMFR1_HPDS_NONE (0x0 << ID_AA64MMFR1_HPDS_SHIFT)
#define ID_AA64MMFR1_HPDS_HPD (0x1 << ID_AA64MMFR1_HPDS_SHIFT)
#define ID_AA64MMFR1_HPDS_TTPBHA (0x2 << ID_AA64MMFR1_HPDS_SHIFT)
#define ID_AA64MMFR1_LO_SHIFT 16
#define ID_AA64MMFR1_LO_MASK (0xf << ID_AA64MMFR1_LO_SHIFT)
#define ID_AA64MMFR1_LO(x) ((x) & ID_AA64MMFR1_LO_MASK)
#define ID_AA64MMFR1_LO_NONE (0x0 << ID_AA64MMFR1_LO_SHIFT)
#define ID_AA64MMFR1_LO_IMPL (0x1 << ID_AA64MMFR1_LO_SHIFT)
#define ID_AA64MMFR1_PAN_SHIFT 20
#define ID_AA64MMFR1_PAN_MASK (0xf << ID_AA64MMFR1_PAN_SHIFT)
#define ID_AA64MMFR1_PAN(x) ((x) & ID_AA64MMFR1_PAN_MASK)
#define ID_AA64MMFR1_PAN_NONE (0x0 << ID_AA64MMFR1_PAN_SHIFT)
#define ID_AA64MMFR1_PAN_IMPL (0x1 << ID_AA64MMFR1_PAN_SHIFT)
#define ID_AA64MMFR1_PAN_ATS1E1 (0x2 << ID_AA64MMFR1_PAN_SHIFT)
#define ID_AA64MMFR1_SPEC_SEI_SHIFT 24
#define ID_AA64MMFR1_SPEC_SEI_MASK (0xf << ID_AA64MMFR1_SPEC_SEI_SHIFT)
#define ID_AA64MMFR1_SPEC_SEI(x) ((x) & ID_AA64MMFR1_SPEC_SEI_MASK)
#define ID_AA64MMFR1_SPEC_SEI_NONE (0x0 << ID_AA64MMFR1_SPEC_SEI_SHIFT)
#define ID_AA64MMFR1_SPEC_SEI_IMPL (0x1 << ID_AA64MMFR1_SPEC_SEI_SHIFT)
#define ID_AA64MMFR1_XNX_SHIFT 28
#define ID_AA64MMFR1_XNX_MASK (0xf << ID_AA64MMFR1_XNX_SHIFT)
#define ID_AA64MMFR1_XNX(x) ((x) & ID_AA64MMFR1_XNX_MASK)
#define ID_AA64MMFR1_XNX_NONE (0x0 << ID_AA64MMFR1_XNX_SHIFT)
#define ID_AA64MMFR1_XNX_IMPL (0x1 << ID_AA64MMFR1_XNX_SHIFT)
/* ID_AA64MMFR2_EL1 */
#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
#define ID_AA64MMFR2_MASK 0x0fffffff
#define ID_AA64MMFR2_CNP_SHIFT 0
#define ID_AA64MMFR2_CNP_MASK (0xf << ID_AA64MMFR2_CNP_SHIFT)
#define ID_AA64MMFR2_CNP(x) ((x) & ID_AA64MMFR2_CNP_MASK)
#define ID_AA64MMFR2_CNP_NONE (0x0 << ID_AA64MMFR2_CNP_SHIFT)
#define ID_AA64MMFR2_CNP_IMPL (0x1 << ID_AA64MMFR2_CNP_SHIFT)
#define ID_AA64MMFR2_UAO_SHIFT 4
#define ID_AA64MMFR2_UAO_MASK (0xf << ID_AA64MMFR2_UAO_SHIFT)
#define ID_AA64MMFR2_UAO(x) ((x) & ID_AA64MMFR2_UAO_MASK)
#define ID_AA64MMFR2_UAO_NONE (0x0 << ID_AA64MMFR2_UAO_SHIFT)
#define ID_AA64MMFR2_UAO_IMPL (0x1 << ID_AA64MMFR2_UAO_SHIFT)
#define ID_AA64MMFR2_LSM_SHIFT 8
#define ID_AA64MMFR2_LSM_MASK (0xf << ID_AA64MMFR2_LSM_SHIFT)
#define ID_AA64MMFR2_LSM(x) ((x) & ID_AA64MMFR2_LSM_MASK)
#define ID_AA64MMFR2_LSM_NONE (0x0 << ID_AA64MMFR2_LSM_SHIFT)
#define ID_AA64MMFR2_LSM_IMPL (0x1 << ID_AA64MMFR2_LSM_SHIFT)
#define ID_AA64MMFR2_IESB_SHIFT 12
#define ID_AA64MMFR2_IESB_MASK (0xf << ID_AA64MMFR2_IESB_SHIFT)
#define ID_AA64MMFR2_IESB(x) ((x) & ID_AA64MMFR2_IESB_MASK)
#define ID_AA64MMFR2_IESB_NONE (0x0 << ID_AA64MMFR2_IESB_SHIFT)
#define ID_AA64MMFR2_IESB_IMPL (0x1 << ID_AA64MMFR2_IESB_SHIFT)
#define ID_AA64MMFR2_VA_RANGE_SHIFT 16
#define ID_AA64MMFR2_VA_RANGE_MASK (0xf << ID_AA64MMFR2_VA_RANGE_SHIFT)
#define ID_AA64MMFR2_VA_RANGE(x) ((x) & ID_AA64MMFR2_VA_RANGE_MASK)
#define ID_AA64MMFR2_VA_RANGE_48 (0x0 << ID_AA64MMFR2_VA_RANGE_SHIFT)
#define ID_AA64MMFR2_VA_RANGE_52 (0x1 << ID_AA64MMFR2_VA_RANGE_SHIFT)
#define ID_AA64MMFR2_CCIDX_SHIFT 20
#define ID_AA64MMFR2_CCIDX_MASK (0xf << ID_AA64MMFR2_CCIDX_SHIFT)
#define ID_AA64MMFR2_CCIDX(x) ((x) & ID_AA64MMFR2_CCIDX_MASK)
#define ID_AA64MMFR2_CCIDX_32 (0x0 << ID_AA64MMFR2_CCIDX_SHIFT)
#define ID_AA64MMFR2_CCIDX_64 (0x1 << ID_AA64MMFR2_CCIDX_SHIFT)
#define ID_AA64MMFR2_NV_SHIFT 24
#define ID_AA64MMFR2_NV_MASK (0xf << ID_AA64MMFR2_NV_SHIFT)
#define ID_AA64MMFR2_NV(x) ((x) & ID_AA64MMFR2_NV_MASK)
#define ID_AA64MMFR2_NV_NONE (0x0 << ID_AA64MMFR2_NV_SHIFT)
#define ID_AA64MMFR2_NV_IMPL (0x1 << ID_AA64MMFR2_NV_SHIFT)
/* ID_AA64PFR0_EL1 */
#define ID_AA64PFR0_MASK 0x0000000ffffffffful
#define ID_AA64PFR0_EL0_SHIFT 0
#define ID_AA64PFR0_EL0_MASK (0xf << ID_AA64PFR0_EL0_SHIFT)
#define ID_AA64PFR0_EL0(x) ((x) & ID_AA64PFR0_EL0_MASK)
#define ID_AA64PFR0_EL0_64 (1 << ID_AA64PFR0_EL0_SHIFT)
#define ID_AA64PFR0_EL0_64_32 (2 << ID_AA64PFR0_EL0_SHIFT)
#define ID_AA64PFR0_EL1_SHIFT 4
#define ID_AA64PFR0_EL1_MASK (0xf << ID_AA64PFR0_EL1_SHIFT)
#define ID_AA64PFR0_EL1(x) ((x) & ID_AA64PFR0_EL1_MASK)
#define ID_AA64PFR0_EL1_64 (1 << ID_AA64PFR0_EL1_SHIFT)
#define ID_AA64PFR0_EL1_64_32 (2 << ID_AA64PFR0_EL1_SHIFT)
#define ID_AA64PFR0_EL2_SHIFT 8
#define ID_AA64PFR0_EL2_MASK (0xf << ID_AA64PFR0_EL2_SHIFT)
#define ID_AA64PFR0_EL2(x) ((x) & ID_AA64PFR0_EL2_MASK)
#define ID_AA64PFR0_EL2_NONE (0 << ID_AA64PFR0_EL2_SHIFT)
#define ID_AA64PFR0_EL2_64 (1 << ID_AA64PFR0_EL2_SHIFT)
#define ID_AA64PFR0_EL2_64_32 (2 << ID_AA64PFR0_EL2_SHIFT)
#define ID_AA64PFR0_EL3_SHIFT 12
#define ID_AA64PFR0_EL3_MASK (0xf << ID_AA64PFR0_EL3_SHIFT)
#define ID_AA64PFR0_EL3(x) ((x) & ID_AA64PFR0_EL3_MASK)
#define ID_AA64PFR0_EL3_NONE (0 << ID_AA64PFR0_EL3_SHIFT)
#define ID_AA64PFR0_EL3_64 (1 << ID_AA64PFR0_EL3_SHIFT)
#define ID_AA64PFR0_EL3_64_32 (2 << ID_AA64PFR0_EL3_SHIFT)
#define ID_AA64PFR0_FP_SHIFT 16
#define ID_AA64PFR0_FP_MASK (0xf << ID_AA64PFR0_FP_SHIFT)
#define ID_AA64PFR0_FP(x) ((x) & ID_AA64PFR0_FP_MASK)
#define ID_AA64PFR0_FP_IMPL (0x0 << ID_AA64PFR0_FP_SHIFT)
#define ID_AA64PFR0_FP_HP (0x1 << ID_AA64PFR0_FP_SHIFT)
#define ID_AA64PFR0_FP_NONE (0xf << ID_AA64PFR0_FP_SHIFT)
#define ID_AA64PFR0_ADV_SIMD_SHIFT 20
#define ID_AA64PFR0_ADV_SIMD_MASK (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT)
#define ID_AA64PFR0_ADV_SIMD(x) ((x) & ID_AA64PFR0_ADV_SIMD_MASK)
#define ID_AA64PFR0_ADV_SIMD_IMPL (0x0 << ID_AA64PFR0_ADV_SIMD_SHIFT)
#define ID_AA64PFR0_ADV_SIMD_HP (0x1 << ID_AA64PFR0_ADV_SIMD_SHIFT)
#define ID_AA64PFR0_ADV_SIMD_NONE (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT)
#define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */
#define ID_AA64PFR0_GIC_SHIFT 24
#define ID_AA64PFR0_GIC_MASK (0xf << ID_AA64PFR0_GIC_SHIFT)
#define ID_AA64PFR0_GIC(x) ((x) & ID_AA64PFR0_GIC_MASK)
#define ID_AA64PFR0_GIC_CPUIF_NONE (0x0 << ID_AA64PFR0_GIC_SHIFT)
#define ID_AA64PFR0_GIC_CPUIF_EN (0x1 << ID_AA64PFR0_GIC_SHIFT)
#define ID_AA64PFR0_RAS_SHIFT 28
#define ID_AA64PFR0_RAS_MASK (0xf << ID_AA64PFR0_RAS_SHIFT)
#define ID_AA64PFR0_RAS(x) ((x) & ID_AA64PFR0_RAS_MASK)
#define ID_AA64PFR0_RAS_NONE (0x0 << ID_AA64PFR0_RAS_SHIFT)
#define ID_AA64PFR0_RAS_V1 (0x1 << ID_AA64PFR0_RAS_SHIFT)
#define ID_AA64PFR0_SVE_SHIFT 32
#define ID_AA64PFR0_SVE_MASK (0xful << ID_AA64PFR0_SVE_SHIFT)
#define ID_AA64PFR0_SVE(x) ((x) & ID_AA64PFR0_SVE_MASK)
#define ID_AA64PFR0_SVE_NONE (0x0ul << ID_AA64PFR0_SVE_SHIFT)
#define ID_AA64PFR0_SVE_IMPL (0x1ul << ID_AA64PFR0_SVE_SHIFT)
/* MAIR_EL1 - Memory Attribute Indirection Register */
#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8))
#define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
#define MAIR_DEVICE_nGnRnE 0x00
#define MAIR_NORMAL_NC 0x44
#define MAIR_NORMAL_WT 0xbb
#define MAIR_NORMAL_WB 0xff
/* PAR_EL1 - Physical Address Register */
#define PAR_F_SHIFT 0
#define PAR_F (0x1 << PAR_F_SHIFT)
#define PAR_SUCCESS(x) (((x) & PAR_F) == 0)
/* When PAR_F == 0 (success) */
#define PAR_SH_SHIFT 7
#define PAR_SH_MASK (0x3 << PAR_SH_SHIFT)
#define PAR_NS_SHIFT 9
#define PAR_NS_MASK (0x3 << PAR_NS_SHIFT)
#define PAR_PA_SHIFT 12
#define PAR_PA_MASK 0x0000fffffffff000
#define PAR_ATTR_SHIFT 56
#define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT)
/* When PAR_F == 1 (aborted) */
#define PAR_FST_SHIFT 1
#define PAR_FST_MASK (0x3f << PAR_FST_SHIFT)
#define PAR_PTW_SHIFT 8
#define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT)
#define PAR_S_SHIFT 9
#define PAR_S_MASK (0x1 << PAR_S_SHIFT)
/* SCTLR_EL1 - System Control Register */
#define SCTLR_RES0 0xc8222440 /* Reserved ARMv8.0, write 0 */
#define SCTLR_RES1 0x30d00800 /* Reserved ARMv8.0, write 1 */
#define SCTLR_M 0x00000001
#define SCTLR_A 0x00000002
#define SCTLR_C 0x00000004
#define SCTLR_SA 0x00000008
#define SCTLR_SA0 0x00000010
#define SCTLR_CP15BEN 0x00000020
/* Bit 6 is reserved */
#define SCTLR_ITD 0x00000080
#define SCTLR_SED 0x00000100
#define SCTLR_UMA 0x00000200
/* Bit 10 is reserved */
/* Bit 11 is reserved */
#define SCTLR_I 0x00001000
#define SCTLR_EnDB 0x00002000 /* ARMv8.3 */
#define SCTLR_DZE 0x00004000
#define SCTLR_UCT 0x00008000
#define SCTLR_nTWI 0x00010000
/* Bit 17 is reserved */
#define SCTLR_nTWE 0x00040000
#define SCTLR_WXN 0x00080000
/* Bit 20 is reserved */
#define SCTLR_IESB 0x00200000 /* ARMv8.2 */
/* Bit 22 is reserved */
#define SCTLR_SPAN 0x00800000 /* ARMv8.1 */
#define SCTLR_EOE 0x01000000
#define SCTLR_EE 0x02000000
#define SCTLR_UCI 0x04000000
#define SCTLR_EnDA 0x08000000 /* ARMv8.3 */
#define SCTLR_nTLSMD 0x10000000 /* ARMv8.2 */
#define SCTLR_LSMAOE 0x20000000 /* ARMv8.2 */
#define SCTLR_EnIB 0x40000000 /* ARMv8.3 */
#define SCTLR_EnIA 0x80000000 /* ARMv8.3 */
/* SPSR_EL1 */
/*
* When the exception is taken in AArch64:
* M[3:2] is the exception level
* M[1] is unused
* M[0] is the SP select:
* 0: always SP0
* 1: current ELs SP
*/
#define PSR_M_EL0t 0x00000000
#define PSR_M_EL1t 0x00000004
#define PSR_M_EL1h 0x00000005
#define PSR_M_EL2t 0x00000008
#define PSR_M_EL2h 0x00000009
#define PSR_M_64 0x00000000
#define PSR_M_32 0x00000010
#define PSR_M_MASK 0x0000000f
#define PSR_T 0x00000020
#define PSR_AARCH32 0x00000010
#define PSR_F 0x00000040
#define PSR_I 0x00000080
#define PSR_A 0x00000100
#define PSR_D 0x00000200
#define PSR_IL 0x00100000
#define PSR_SS 0x00200000
#define PSR_V 0x10000000
#define PSR_C 0x20000000
#define PSR_Z 0x40000000
#define PSR_N 0x80000000
#define PSR_FLAGS 0xf0000000
/* TCR_EL1 - Translation Control Register */
#define TCR_ASID_16 (1 << 36)
#define TCR_IPS_SHIFT 32
#define TCR_IPS_32BIT (0 << TCR_IPS_SHIFT)
#define TCR_IPS_36BIT (1 << TCR_IPS_SHIFT)
#define TCR_IPS_40BIT (2 << TCR_IPS_SHIFT)
#define TCR_IPS_42BIT (3 << TCR_IPS_SHIFT)
#define TCR_IPS_44BIT (4 << TCR_IPS_SHIFT)
#define TCR_IPS_48BIT (5 << TCR_IPS_SHIFT)
#define TCR_TG1_SHIFT 30
#define TCR_TG1_16K (1 << TCR_TG1_SHIFT)
#define TCR_TG1_4K (2 << TCR_TG1_SHIFT)
#define TCR_TG1_64K (3 << TCR_TG1_SHIFT)
#define TCR_SH1_SHIFT 28
#define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT)
#define TCR_ORGN1_SHIFT 26
#define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT)
#define TCR_IRGN1_SHIFT 24
#define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT)
#define TCR_SH0_SHIFT 12
#define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT)
#define TCR_ORGN0_SHIFT 10
#define TCR_ORGN0_WBWA (0x1UL << TCR_ORGN0_SHIFT)
#define TCR_IRGN0_SHIFT 8
#define TCR_IRGN0_WBWA (0x1UL << TCR_IRGN0_SHIFT)
#define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\
(TCR_ORGN0_WBWA | TCR_ORGN1_WBWA))
#define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS)
#define TCR_T1SZ_SHIFT 16
#define TCR_T0SZ_SHIFT 0
#define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT)
#define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT)
#define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x))
/* Saved Program Status Register */
#define DBG_SPSR_SS (0x1 << 21)
/* Monitor Debug System Control Register */
#define DBG_MDSCR_SS (0x1 << 0)
#define DBG_MDSCR_KDE (0x1 << 13)
#define DBG_MDSCR_MDE (0x1 << 15)
/* Perfomance Monitoring Counters */
#define PMCR_E (1 << 0) /* Enable all counters */
#define PMCR_P (1 << 1) /* Reset all counters */
#define PMCR_C (1 << 2) /* Clock counter reset */
#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */
#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */
#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
#define PMCR_LC (1 << 6) /* Long cycle count enable */
#define PMCR_IMP_SHIFT 24 /* Implementer code */
#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT)
#define PMCR_IDCODE_SHIFT 16 /* Identification code */
#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT)
#define PMCR_IDCODE_CORTEX_A57 0x01
#define PMCR_IDCODE_CORTEX_A72 0x02
#define PMCR_IDCODE_CORTEX_A53 0x03
#define PMCR_N_SHIFT 11 /* Number of counters implemented */
#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT)
#endif /* !_MACHINE_ARMREG_H_ */

13
headers/private/system/arch/arm64/arch_commpage_defs.h Normal file
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@ -0,0 +1,13 @@
/*
* Copyright 2019 Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _SYSTEM_ARCH_ARM64_COMMPAGE_DEFS_H
#define _SYSTEM_ARCH_ARM64_COMMPAGE_DEFS_H
#ifndef _SYSTEM_COMMPAGE_DEFS_H
# error Must not be included directly. Include <commpage_defs.h> instead!
#endif
#endif /* _SYSTEM_ARCH_ARM64_COMMPAGE_DEFS_H */

12
headers/private/system/arch/arm64/arch_config.h Normal file
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@ -0,0 +1,12 @@
/*
* Copyright 2019 Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _KERNEL_ARCH_ARM64_CONFIG_H
#define _KERNEL_ARCH_ARM64_CONFIG_H
#define FUNCTION_CALL_PARAMETER_ALIGNMENT_TYPE unsigned long
#define STACK_GROWS_DOWNWARDS
#endif /* _KERNEL_ARCH_ARM64_CONFIG_H */

12
headers/private/system/arch/arm64/arch_cpu_defs.h Normal file
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@ -0,0 +1,12 @@
/*
* Copyright 2019 Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _SYSTEM_ARCH_ARM64_DEFS_H
#define _SYSTEM_ARCH_ARM64_DEFS_H
#define SPINLOCK_PAUSE() __asm__ __volatile__("yield")
#endif /* _SYSTEM_ARCH_ARM64_DEFS_H */

25
headers/private/system/arch/arm64/arch_elf.h Normal file
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@ -0,0 +1,25 @@
/*
* Copyright 2019 Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _KERNEL_ARCH_ARM64_ELF_H
#define _KERNEL_ARCH_ARM64_ELF_H
#define R_AARCH64_NONE 0 /* No relocation */
#define R_AARCH64_ABS64 257 /* Absolute offset */
#define R_AARCH64_ABS32 258 /* Absolute, 32-bit overflow check */
#define R_AARCH64_ABS16 259 /* Absolute, 16-bit overflow check */
#define R_AARCH64_PREL64 260 /* PC relative */
#define R_AARCH64_PREL32 261 /* PC relative, 32-bit overflow check */
#define R_AARCH64_PREL16 262 /* PC relative, 16-bit overflow check */
#define R_AARCH64_COPY 1024 /* Copy data from shared object */
#define R_AARCH64_GLOB_DAT 1025 /* Set GOT entry to data address */
#define R_AARCH64_JUMP_SLOT 1026 /* Set GOT entry to code address */
#define R_AARCH64_RELATIVE 1027 /* Add load address of shared object */
#define R_AARCH64_TLS_DTPREL64 1028
#define R_AARCH64_TLS_DTPMOD64 1029
#define R_AARCH64_TLS_TPREL64 1030
#define R_AARCH64_TLSDESC 1031 /* Identify the TLS descriptor */
#define R_AARCH64_IRELATIVE 1032
#endif /* _KERNEL_ARCH_ARM64_ELF_H */

21
headers/private/system/arch/arm64/arch_real_time_data.h Normal file
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@ -0,0 +1,21 @@
/*
* Copyright 2019 Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _KERNEL_ARCH_REAL_TIME_DATA_H
#define _KERNEL_ARCH_REAL_TIME_DATA_H
#include <StorageDefs.h>
#include <SupportDefs.h>
struct arm64_real_time_data {
vint64 system_time_offset;
};
struct arch_real_time_data {
struct arm64_real_time_data data[2];
vint32 system_time_conversion_factor;
vint32 version;
};
#endif /* _KERNEL_ARCH_REAL_TIME_DATA_H */

14
headers/private/system/arch/arm64/asm_defs.h Normal file
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@ -0,0 +1,14 @@
/*
* Copyright 2019 Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef SYSTEM_ARCH_ARM64_ASM_DEFS_H
#define SYSTEM_ARCH_ARM64_ASM_DEFS_H
#define SYMBOL(name) .global name; name
#define SYMBOL_END(name) .size name, . - name
#define STATIC_FUNCTION(name) .type name, %function; name
#define FUNCTION(name) .global name; .type name, %function; name
#define FUNCTION_END(name) .size name, . - name
#endif /* SYSTEM_ARCH_ARM64_ASM_DEFS_H */

6
src/libs/compat/freebsd_network/compat/sys/param.h
View File

@ -56,7 +56,8 @@
#define ALIGNED_POINTER(p, t) ((((uintptr_t)(p)) & (sizeof (t) - 1)) == 0) #define ALIGNED_POINTER(p, t) ((((uintptr_t)(p)) & (sizeof (t) - 1)) == 0)
#elif defined(__arm__) #elif defined(__arm__)
#define ALIGNED_POINTER(p, t) ((((unsigned)(p)) & (sizeof(t) - 1)) == 0) #define ALIGNED_POINTER(p, t) ((((unsigned)(p)) & (sizeof(t) - 1)) == 0)
#elif defined(__mips__) || defined(__sparc__) || defined(__riscv64__) #elif defined(__mips__) || defined(__sparc__) || defined(__riscv64__) \
|| defined(__aarch64__) || defined(__arm64__)
#define ALIGNED_POINTER(p, t) ((((unsigned long)(p)) & (sizeof (t) - 1)) == 0) #define ALIGNED_POINTER(p, t) ((((unsigned long)(p)) & (sizeof (t) - 1)) == 0)
#else #else
#error Need definition of ALIGNED_POINTER for this arch! #error Need definition of ALIGNED_POINTER for this arch!
@ -64,7 +65,8 @@
/* defined in arch_cpu.h which we can't include here as it's C++ */ /* defined in arch_cpu.h which we can't include here as it's C++ */
#if defined(__x86_64__) || defined(__i386__) || defined(__arm__) \ #if defined(__x86_64__) || defined(__i386__) || defined(__arm__) \
|| defined(__sparc__) || defined(__riscv64__) || defined(__sparc__) || defined(__riscv64__) \
|| defined(__aarch64__) || defined(__arm64__)
#define CACHE_LINE_SIZE 64 #define CACHE_LINE_SIZE 64
#else #else
#error Need definition of CACHE_LINE_SIZE for this arch! #error Need definition of CACHE_LINE_SIZE for this arch!

4
src/system/kernel/arch/arm64/Jamfile Normal file
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@ -0,0 +1,4 @@
SubDir HAIKU_TOP src system kernel arch arm64 ;
SubDirHdrs $(SUBDIR) $(DOTDOT) generic ;
UsePrivateKernelHeaders ;

2
src/system/kernel/debug/core_dump.cpp
View File

@ -1125,6 +1125,8 @@ private:
header.e_machine = EM_MIPS; header.e_machine = EM_MIPS;
#elif defined(__HAIKU_ARCH_ARM) #elif defined(__HAIKU_ARCH_ARM)
header.e_machine = EM_ARM; header.e_machine = EM_ARM;
#elif defined(__HAIKU_ARCH_ARM64)
header.e_machine = EM_AARCH64;
#elif defined(__HAIKU_ARCH_SPARC) #elif defined(__HAIKU_ARCH_SPARC)
header.e_machine = EM_SPARCV9; header.e_machine = EM_SPARCV9;
#elif defined(__HAIKU_ARCH_RISCV64) #elif defined(__HAIKU_ARCH_RISCV64)

23
src/system/libroot/os/arch/arm64/Jamfile Normal file
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@ -0,0 +1,23 @@
SubDir HAIKU_TOP src system libroot os arch arm ;
SubDirC++Flags -std=gnu++11 ;
local architectureObject ;
for architectureObject in [ MultiArchSubDirSetup arm64 ] {
on $(architectureObject) {
local architecture = $(TARGET_PACKAGING_ARCH) ;
UsePrivateKernelHeaders ;
UsePrivateSystemHeaders ;
SEARCH_SOURCE += [ FDirName $(SUBDIR) $(DOTDOT) generic ] ;
MergeObject <$(architecture)>os_arch_$(TARGET_ARCH).o :
generic_atomic.cpp
generic_stack_trace.cpp
generic_system_time_nsecs.cpp
;
}
}

33
src/system/libroot/os/arch/arm64/syscalls.inc Normal file
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@ -0,0 +1,33 @@
/*
* Copyright 2019 Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License.
*/
#define _AARCH64_SYSCALL_ENCODE(name, code, nparams) \
.globl name; \
.type name,%function; \
.p2align 2; \
name: \
svc #(((code) << 5) | (nparams)); \
ret
#define SYSCALL0(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 0)
#define SYSCALL1(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 1)
#define SYSCALL2(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 2)
#define SYSCALL3(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 3)
#define SYSCALL4(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 4)
#define SYSCALL5(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 5)
#define SYSCALL6(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 6)
#define SYSCALL7(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 7)
#define SYSCALL8(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 8)
#define SYSCALL9(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 9)
#define SYSCALL10(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 10)
#define SYSCALL11(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 11)
#define SYSCALL12(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 12)
#define SYSCALL13(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 13)
#define SYSCALL14(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 14)
#define SYSCALL15(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 15)
#define SYSCALL16(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 16)
#define SYSCALL17(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 17)
#define SYSCALL18(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 18)
#define SYSCALL19(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 19)
#define SYSCALL20(name, n) _AARCH64_SYSCALL_ENCODE(name, n, 20)

2
src/system/libroot/os/syscalls.S
View File

@ -19,6 +19,8 @@
# include "arch/ppc/syscalls.inc" # include "arch/ppc/syscalls.inc"
#elif defined(ARCH_arm) #elif defined(ARCH_arm)
# include "arch/arm/syscalls.inc" # include "arch/arm/syscalls.inc"
#elif defined(ARCH_arm64)
# include "arch/arm64/syscalls.inc"
#elif defined(ARCH_m68k) #elif defined(ARCH_m68k)
# include "arch/m68k/syscalls.inc" # include "arch/m68k/syscalls.inc"
#elif defined(ARCH_riscv64) #elif defined(ARCH_riscv64)

30
src/system/libroot/posix/glibc/include/arch/arm64/bits/endian.h Normal file
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@ -0,0 +1,30 @@
/* Copyright (C) 1997-2018 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public License as
published by the Free Software Foundation; either version 2.1 of the
License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library. If not, see
<http://www.gnu.org/licenses/>. */
#ifndef _ENDIAN_H
# error "Never use <bits/endian.h> directly; include <endian.h> instead."
#endif
/* AArch64 can be either big or little endian. */
#ifdef __AARCH64EB__
# define __BYTE_ORDER __BIG_ENDIAN
#else
# define __BYTE_ORDER __LITTLE_ENDIAN
#endif
#define __FLOAT_WORD_ORDER __BYTE_ORDER

82
src/system/libroot/posix/glibc/include/arch/arm64/bits/fenv.h Normal file
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@ -0,0 +1,82 @@
/* Copyright (C) 2004-2018 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public License as
published by the Free Software Foundation; either version 2.1 of the
License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, see
<http://www.gnu.org/licenses/>. */
#ifndef _FENV_H
# error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
#endif
/* Define bits representing exceptions in the FPSR status word. */
enum
{
FE_INVALID =
#define FE_INVALID 1
FE_INVALID,
FE_DIVBYZERO =
#define FE_DIVBYZERO 2
FE_DIVBYZERO,
FE_OVERFLOW =
#define FE_OVERFLOW 4
FE_OVERFLOW,
FE_UNDERFLOW =
#define FE_UNDERFLOW 8
FE_UNDERFLOW,
FE_INEXACT =
#define FE_INEXACT 16
FE_INEXACT,
};
/* Amount to shift by to convert an exception bit in FPSR to a an
exception bit mask in FPCR. */
#define FE_EXCEPT_SHIFT 8
/* All supported exceptions. */
#define FE_ALL_EXCEPT \
(FE_INVALID | FE_DIVBYZERO | FE_OVERFLOW | FE_UNDERFLOW | FE_INEXACT)
/* Define bits representing rounding modes in the FPCR Rmode field. */
#define FE_TONEAREST 0x000000
#define FE_UPWARD 0x400000
#define FE_DOWNWARD 0x800000
#define FE_TOWARDZERO 0xc00000
/* Type representing exception flags. */
typedef unsigned int fexcept_t;
/* Type representing floating-point environment. */
typedef struct
{
unsigned int __fpcr;
unsigned int __fpsr;
}
fenv_t;
/* If the default argument is used we use this value. */
#define FE_DFL_ENV ((const fenv_t *) -1l)
#ifdef __USE_GNU
/* Floating-point environment where none of the exceptions are masked. */
# define FE_NOMASK_ENV ((const fenv_t *) -2)
#endif
#if __GLIBC_USE (IEC_60559_BFP_EXT)
/* Type representing floating-point control modes. */
typedef unsigned int femode_t;
/* Default floating-point control modes. */
# define FE_DFL_MODE ((const femode_t *) -1L)
#endif

26
src/system/libroot/posix/glibc/include/arch/arm64/bits/huge_val.h Normal file
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@ -0,0 +1,26 @@
/* Stub `HUGE_VAL' constant.
Used by <stdlib.h> and <math.h> functions for overflow.
Copyright (C) 1992, 1996, 1997, 2004 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, see
<http://www.gnu.org/licenses/>. */
#ifndef _MATH_H
# error "Never use <bits/huge_val.h> directly; include <math.h> instead."
#endif
# define HUGE_VAL (__builtin_huge_val())
# define HUGE_VALF (__builtin_huge_valf())
# define HUGE_VALL (__builtin_huge_vall())

43
src/system/libroot/posix/glibc/include/arch/arm64/bits/mathdef.h Normal file
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@ -0,0 +1,43 @@
/* Copyright (C) 1999, 2000, 2004, 2006, 2007
Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
#if !defined _MATH_H && !defined _COMPLEX_H
# error "Never use <bits/mathdef.h> directly; include <math.h> instead"
#endif
#if defined __USE_ISOC99 && defined _MATH_H && !defined _MATH_H_MATHDEF
# define _MATH_H_MATHDEF 1
/* GCC does not promote `float' values to `double'. */
typedef float float_t; /* `float' expressions are evaluated as
`float'. */
typedef double double_t; /* `double' expressions are evaluated as
`double'. */
#ifdef __FLT_EVAL_METHOD__
# if __FLT_EVAL_METHOD__ == -1
# define FLT_EVAL_METHOD 2
# else
# define FLT_EVAL_METHOD __FLT_EVAL_METHOD__
# endif
#else
# define FLT_EVAL_METHOD 0
#endif
#endif /* ISO C99 */

1
src/system/libroot/posix/glibc/include/arch/arm64/bits/mathinline.h Normal file
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@ -0,0 +1 @@
#warning ARM64: check mathinline.h

25
src/system/libroot/posix/glibc/include/arch/arm64/bits/nan.h Normal file
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@ -0,0 +1,25 @@
/* `NAN' constant for IEEE 754 machines.
Copyright (C) 1992,1996,1997,1999,2004,2006 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, see
<http://www.gnu.org/licenses/>. */
#ifndef _MATH_H
# error "Never use <bits/nan.h> directly; include <math.h> instead."
#endif
/* IEEE Not A Number. */
# define NAN (__builtin_nanf (""))

28
src/system/libroot/posix/glibc/include/arch/arm64/bits/wordsize.h Normal file
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@ -0,0 +1,28 @@
/* Determine the wordsize from the preprocessor defines.
Copyright (C) 2016-2018 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, see
<http://www.gnu.org/licenses/>. */
#ifdef __LP64__
# define __WORDSIZE 64
#else
# define __WORDSIZE 32
# define __WORDSIZE32_SIZE_ULONG 1
# define __WORDSIZE32_PTRDIFF_LONG 1
#endif
#define __WORDSIZE_TIME64_COMPAT32 0

228
src/system/libroot/posix/glibc/include/arch/arm64/config.h Normal file
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@ -0,0 +1,228 @@
//#if !defined __ASSEMBLER__ && !defined _ISOMAC && !defined __OPTIMIZE__
//# error "glibc cannot be compiled without optimization"
//#endif
/* Another evil option when it comes to compiling the C library is
--ffast-math since it alters the ABI. */
#if defined __FAST_MATH__ && !defined TEST_FAST_MATH
# error "glibc must not be compiled with -ffast-math"
#endif
/* Define if using GNU ld, with support for weak symbols in a.out,
and for symbol set and warning messages extensions in a.out and ELF.
This implies HAVE_WEAK_SYMBOLS; set by --with-gnu-ld. */
#define HAVE_GNU_LD 1
/* Define if using ELF, which supports weak symbols.
This implies HAVE_ASM_WEAK_DIRECTIVE set by --with-elf. */
#define HAVE_ELF 1
/* Define if using XCOFF. Set by --with-xcoff. */
#undef HAVE_XCOFF
/* Define if weak symbols are available via the `.weak' directive. */
#define HAVE_ASM_WEAK_DIRECTIVE 1
/* Define if weak symbols are available via the `.weakext' directive. */
#undef HAVE_ASM_WEAKEXT_DIRECTIVE
/* Define to the assembler line separator character for multiple
assembler instructions per line. Default is `;' */
#undef ASM_LINE_SEP
/* Define if not using ELF, but `.init' and `.fini' sections are available. */
#undef HAVE_INITFINI
/* Define if __attribute__((section("foo"))) puts quotes around foo. */
/*#define HAVE_SECTION_QUOTES 1
[zooey]: defining this causes assembler errors, and I don't think
that any BeOS-gcc actually produces quotes in sections...
*/
#undef HAVE_SECTION_QUOTES
/* Define if using the GNU assembler, gas. */
#define HAVE_GNU_AS 1
/* Define if the assembler supports the `.set' directive. */
#define HAVE_ASM_SET_DIRECTIVE 1
/* Define to the name of the assembler's directive for
declaring a symbol global (default `.globl'). */
#define ASM_GLOBAL_DIRECTIVE .globl
/* Define to the prefix before `object' or `function' in the
assembler's `.type' directive, if it has one. */
#undef ASM_TYPE_DIRECTIVE_PREFIX
/* Define a symbol_name as a global .symbol_name for ld. */
#undef HAVE_ASM_GLOBAL_DOT_NAME
/* Define if the assembler generates debugging information directly. */
#undef HAVE_CPP_ASM_DEBUGINFO
/* Define if _Unwind_Find_FDE should be exported from glibc. */
#undef EXPORT_UNWIND_FIND_FDE
/* Define to use GNU libio instead of GNU stdio.
This is defined by configure under --enable-libio. */
#define USE_IN_LIBIO 1
/* Define if using ELF and the assembler supports the `.previous'
directive. */
#define HAVE_ASM_PREVIOUS_DIRECTIVE 1
/* Define if using ELF and the assembler supports the `.popsection'
directive. */
#undef HAVE_ASM_POPSECTION_DIRECTIVE
/* Define if versioning of the library is wanted. */
#undef DO_VERSIONING
/* Defined to the oldest ABI we support, like 2.1. */
#undef GLIBC_OLDEST_ABI
/* Define if static NSS modules are wanted. */
#undef DO_STATIC_NSS
/* Define if gcc uses DWARF2 unwind information for exception support. */
#define HAVE_DWARF2_UNWIND_INFO 1
/* Define if gcc uses DWARF2 unwind information for exception support
with static variable. */
#define HAVE_DWARF2_UNWIND_INFO_STATIC 1
/* Define if the compiler supports __builtin_expect. */
#undef HAVE_BUILTIN_EXPECT
/* Define if the compiler supports __builtin_memset. */
#undef HAVE_BUILTIN_MEMSET
/* Define if the __thread keyword is supported. */
#undef HAVE___THREAD
/* Define if the compiler supports __attribute__((tls_model(""))). */
#undef HAVE_TLS_MODEL_ATTRIBUTE
/* Define if the regparm attribute shall be used for local functions
(gcc on ix86 only). */
#define USE_REGPARMS 0
/* Defined on PowerPC if the GCC being used has a problem with clobbering
certain registers (CR0, MQ, CTR, LR) in asm statements. */
#undef BROKEN_PPC_ASM_CR0
/* Defined on SPARC if ld doesn't handle R_SPARC_WDISP22 against .hidden
symbol. sysdeps/sparc/sparc32/elf/configure. */
#undef BROKEN_SPARC_WDISP22
/* Define if the linker supports the -z combreloc option. */
#undef HAVE_Z_COMBRELOC
/* Define if the assembler supported .protected. */
#undef HAVE_PROTECTED
/* Define if the assembler supported .hidden. */
#undef HAVE_HIDDEN
/* Define if the compiler supports __attribute__ ((visibility (...))). */
#undef HAVE_VISIBILITY_ATTRIBUTE
/* Define if the compiler doesn't support __attribute__ ((visibility (...)))
together with __asm__ redirection properly. */
#undef HAVE_BROKEN_VISIBILITY_ATTRIBUTE
/* Define if the compiler doesn't support __attribute__ ((alias (...)))
together with __asm__ redirection properly. */
#undef HAVE_BROKEN_ALIAS_ATTRIBUTE
/* Define if _rtld_local structure should be forced into .sdata section. */
#undef HAVE_SDATA_SECTION
/* Define if binutils support TLS handling. */
#undef HAVE_TLS_SUPPORT
/* Define if the linker supports .preinit_array/.init_array/.fini_array
sections. */
#undef HAVE_INITFINI_ARRAY
/* Define if the access to static and hidden variables is position independent
and does not need relocations. */
#undef PI_STATIC_AND_HIDDEN
/* Define this to disable the `hidden_proto' et al macros in
include/libc-symbols.h that avoid PLT slots in the shared objects. */
#undef NO_HIDDEN
/* Defined to some form of __attribute__ ((...)) if the compiler supports
a different, more efficient calling convention. */
#if USE_REGPARMS && !defined PROF && !defined __BOUNDED_POINTERS__
# define internal_function __attribute__ ((regparm (3), stdcall))
#endif
/* Linux specific: minimum supported kernel version. */
#undef __LINUX_KERNEL_VERSION
/* Override abi-tags ABI version if necessary. */
#undef __ABI_TAG_VERSION
/* An extension in gcc 2.96 and up allows the subtraction of two
local labels. */
#undef HAVE_SUBTRACT_LOCAL_LABELS
/* bash 2.0 introduced the _XXX_GNU_nonoption_argv_flags_ variable to help
getopt determine whether a parameter is a flag or not. This features
was disabled later since it caused trouble. We are by default therefore
disabling the support as well. */
#undef USE_NONOPTION_FLAGS
/* Mach/Hurd specific: define if mig supports the `retcode' keyword. */
#undef HAVE_MIG_RETCODE
/* Mach specific: define if the `host_page_size' RPC is available. */
#undef HAVE_HOST_PAGE_SIZE
/*
*/
#ifndef _LIBC
/* These symbols might be defined by some sysdeps configures.
They are used only in miscellaneous generator programs, not
in compiling libc itself. */
/* sysdeps/generic/configure.in */
#undef HAVE_PSIGNAL
/* sysdeps/unix/configure.in */
#define HAVE_STRERROR
/* sysdeps/unix/common/configure.in */
#undef HAVE_SYS_SIGLIST
#undef HAVE__SYS_SIGLIST
#undef HAVE__CTYPE_
#undef HAVE___CTYPE_
#undef HAVE___CTYPE
#undef HAVE__CTYPE__
#undef HAVE__CTYPE
#undef HAVE__LOCP
#endif
/*
*/
#ifdef _LIBC
/* The zic and zdump programs need these definitions. */
#define HAVE_STRERROR 1
/* The locale code needs these definitions. */
#define HAVE_REGEX 1
//#define HAVE_MMAP 1
#undef HAVE_MMAP
#endif

98
src/system/libroot/posix/glibc/include/arch/arm64/math_ldbl.h Normal file
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@ -0,0 +1,98 @@
#ifndef _MATH_PRIVATE_H_
#error "Never use <math_ldbl.h> directly; include <math_private.h> instead."
#endif
/* A union which permits us to convert between a long double and
three 32 bit ints. */
#if __FLOAT_WORD_ORDER == BIG_ENDIAN
typedef union
{
long double value;
struct
{
int sign_exponent:16;
unsigned int empty:16;
u_int32_t msw;
u_int32_t lsw;
} parts;
} ieee_long_double_shape_type;
#endif
#if __FLOAT_WORD_ORDER == LITTLE_ENDIAN
typedef union
{
long double value;
struct
{
u_int32_t lsw;
u_int32_t msw;
int sign_exponent:16;
unsigned int empty:16;
} parts;
} ieee_long_double_shape_type;
#endif
/* Get three 32 bit ints from a double. */
#define GET_LDOUBLE_WORDS(exp,ix0,ix1,d) \
do { \
ieee_long_double_shape_type ew_u; \
ew_u.value = (d); \
(exp) = ew_u.parts.sign_exponent; \
(ix0) = ew_u.parts.msw; \
(ix1) = ew_u.parts.lsw; \
} while (0)
/* Set a double from two 32 bit ints. */
#define SET_LDOUBLE_WORDS(d,exp,ix0,ix1) \
do { \
ieee_long_double_shape_type iw_u; \
iw_u.parts.sign_exponent = (exp); \
iw_u.parts.msw = (ix0); \
iw_u.parts.lsw = (ix1); \
(d) = iw_u.value; \
} while (0)
/* Get the more significant 32 bits of a long double mantissa. */
#define GET_LDOUBLE_MSW(v,d) \
do { \
ieee_long_double_shape_type sh_u; \
sh_u.value = (d); \
(v) = sh_u.parts.msw; \
} while (0)
/* Set the more significant 32 bits of a long double mantissa from an int. */
#define SET_LDOUBLE_MSW(d,v) \
do { \
ieee_long_double_shape_type sh_u; \
sh_u.value = (d); \
sh_u.parts.msw = (v); \
(d) = sh_u.value; \
} while (0)
/* Get int from the exponent of a long double. */
#define GET_LDOUBLE_EXP(exp,d) \
do { \
ieee_long_double_shape_type ge_u; \
ge_u.value = (d); \
(exp) = ge_u.parts.sign_exponent; \
} while (0)
/* Set exponent of a long double from an int. */
#define SET_LDOUBLE_EXP(d,exp) \
do { \
ieee_long_double_shape_type se_u; \
se_u.value = (d); \
se_u.parts.sign_exponent = (exp); \
(d) = se_u.value; \
} while (0)

28
src/system/libroot/posix/glibc/include/arch/arm64/stackinfo.h Normal file
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@ -0,0 +1,28 @@
/* Copyright (C) 2001 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
/* This file contains a bit of information about the stack allocation
of the processor. */
#ifndef _STACKINFO_H
#define _STACKINFO_H 1
/* On Arm the stack grows down. */
#define _STACK_GROWS_DOWN 1
#endif /* stackinfo.h */

2
src/system/libroot/posix/stdlib/strtod.c
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@ -127,7 +127,7 @@
defined(__sparc64__) || defined(__powerpc__) || defined(__POWERPC__) || \ defined(__sparc64__) || defined(__powerpc__) || defined(__POWERPC__) || \
defined(__m68k__) || defined(__M68K__) || defined(__arm__) || \ defined(__m68k__) || defined(__M68K__) || defined(__arm__) || \
defined(__mipsel__) || defined(__MIPSEL__) || defined(__x86_64__) || \ defined(__mipsel__) || defined(__MIPSEL__) || defined(__x86_64__) || \
defined(__riscv64__) defined(__riscv64__) || defined(__aarch64__) || defined(__arm64__)
# include <sys/types.h> # include <sys/types.h>
# if BYTE_ORDER == BIG_ENDIAN # if BYTE_ORDER == BIG_ENDIAN
# define IEEE_BIG_ENDIAN # define IEEE_BIG_ENDIAN

2
src/tools/gensyscalls/arch/arm64/arch_gensyscalls.h Normal file
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@ -0,0 +1,2 @@
#define SYSCALL_RETURN_TYPE_ALIGNMENT_TYPE long
#define SYSCALL_PARAMETER_ALIGNMENT_TYPE long