* added an ALIGN macro for easing readability and use it for 128 alignments
* use HDAC_STREAM_POSITION register value to check the current buffer cycle in interrupt handler * added B_FULL_LOCK flags for area allocation, not sure it's handled but at least more correct * buffer descriptors now use a low and high address fields * applied a byte mask on format * enabled PCI bus mastering if not yet done * the PCI space register TCSEL (Traffic Class Select Register, which sets PCI express QOS) is now reset to TC0 (clear 0-2 bits) as needed on some boards like mine to ensure good playback Playback is finally working correctly here on ICH8 HDA! git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@26847 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Jérôme Duval
parent
28fd262f0e
commit
1708513ca8
@ -26,6 +26,7 @@
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(((controller)->num_input_streams + (controller)->num_output_streams \
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+ (index)) * HDAC_STREAM_SIZE)
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#define ALIGN(size, align) (((size) + align - 1) & ~(align - 1))
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#define PAGE_ALIGN(size) (((size) + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1))
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static const struct {
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@ -73,6 +74,7 @@ static void
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stream_handle_interrupt(hda_controller* controller, hda_stream* stream)
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{
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uint8 status;
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uint32 position, bufferSize;
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if (!stream->running)
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return;
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@ -83,20 +85,24 @@ stream_handle_interrupt(hda_controller* controller, hda_stream* stream)
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stream->Write8(HDAC_STREAM_STATUS, status);
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if ((status & STATUS_BUFFER_COMPLETED) != 0) {
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if ((status & STATUS_BUFFER_COMPLETED) == 0) {
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dprintf("hda: stream status %x\n", status);
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return;
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}
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position = stream->Read32(HDAC_STREAM_POSITION);
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bufferSize = ALIGN(stream->sample_size * stream->num_channels * stream->buffer_length, 128);
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// Buffer Completed Interrupt
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acquire_spinlock(&stream->lock);
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stream->real_time = system_time();
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stream->frames_count += stream->buffer_length;
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stream->buffer_cycle = (stream->buffer_cycle + 1)
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% stream->num_buffers;
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stream->buffer_cycle = 1 - (position / bufferSize);
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release_spinlock(&stream->lock);
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release_sem_etc(stream->buffer_ready_sem, 1, B_DO_NOT_RESCHEDULE);
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} else
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dprintf("hda: stream status %x\n", status);
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}
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@ -301,9 +307,8 @@ init_corb_rirb_pos(hda_controller* controller)
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}
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/* Determine rirb offset in memory and total size of corb+alignment+rirb */
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rirbOffset = (controller->corb_length * sizeof(corb_t) + 0x7f) & ~0x7f;
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posOffset = (rirbOffset + controller->rirb_length * sizeof(rirb_t) + 0x7f)
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& ~0x7f;
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rirbOffset = ALIGN(controller->corb_length * sizeof(corb_t), 128);
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posOffset = ALIGN(rirbOffset + controller->rirb_length * sizeof(rirb_t), 128);
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posSize = 8 * (controller->num_input_streams
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+ controller->num_output_streams + controller->num_bidir_streams);
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@ -312,7 +317,7 @@ init_corb_rirb_pos(hda_controller* controller)
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/* Allocate memory area */
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controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos",
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(void**)&controller->corb, B_ANY_KERNEL_ADDRESS, memSize,
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B_CONTIGUOUS, 0);
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B_FULL_LOCK | B_CONTIGUOUS, 0);
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if (controller->corb_rirb_pos_area < 0)
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return controller->corb_rirb_pos_area;
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@ -418,7 +423,6 @@ hda_stream_new(hda_audio_group* audioGroup, int type)
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dprintf("%s: Unknown stream type %d!\n", __func__, type);
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free(stream);
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stream = NULL;
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break;
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}
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// find I/O and Pin widgets for this stream
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@ -500,7 +504,8 @@ hda_stream_setup_buffers(hda_audio_group* audioGroup, hda_stream* stream,
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/* Calculate size of buffer (aligned to 128 bytes) */
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bufferSize = stream->sample_size * stream->num_channels
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* stream->buffer_length;
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bufferSize = (bufferSize + 127) & (~127);
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bufferSize = ALIGN(bufferSize, 128);
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dprintf("HDA: sample size %ld, num channels %ld, buffer length %ld ****************\n",
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stream->sample_size, stream->num_channels, stream->buffer_length);
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@ -510,7 +515,7 @@ dprintf("HDA: sample size %ld, num channels %ld, buffer length %ld *************
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/* Allocate memory for buffers */
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stream->buffer_area = create_area("hda buffers", (void**)&buffer,
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B_ANY_KERNEL_ADDRESS, alloc, B_CONTIGUOUS, B_READ_AREA | B_WRITE_AREA);
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B_ANY_KERNEL_ADDRESS, alloc, B_FULL_LOCK | B_CONTIGUOUS, B_READ_AREA | B_WRITE_AREA);
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if (stream->buffer_area < B_OK)
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return stream->buffer_area;
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@ -539,7 +544,7 @@ dprintf("HDA: sample size %ld, num channels %ld, buffer length %ld *************
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stream->buffer_descriptors_area = create_area("hda buffer descriptors",
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(void**)&bufferDescriptors, B_ANY_KERNEL_ADDRESS, alloc,
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B_CONTIGUOUS, 0);
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B_FULL_LOCK | B_CONTIGUOUS, 0);
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if (stream->buffer_descriptors_area < B_OK) {
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delete_area(stream->buffer_area);
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return stream->buffer_descriptors_area;
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@ -560,14 +565,15 @@ dprintf("HDA: sample size %ld, num channels %ld, buffer length %ld *************
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/* Setup buffer descriptor list (BDL) entries */
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for (index = 0; index < stream->num_buffers; index++, bufferDescriptors++) {
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bufferDescriptors->address = stream->physical_buffers[index];
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bufferDescriptors->lower = stream->physical_buffers[index];
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bufferDescriptors->upper = 0;
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bufferDescriptors->length = bufferSize;
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bufferDescriptors->ioc = 1;
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// we want an interrupt after every buffer
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}
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/* Configure stream registers */
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format = stream->num_channels - 1;
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format = (stream->num_channels - 1) & 0xf;
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switch (stream->sample_format) {
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case B_FMT_8BIT_S: format |= FORMAT_8BIT; stream->bps = 8; break;
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case B_FMT_16BIT: format |= FORMAT_16BIT; stream->bps = 16; break;
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@ -598,8 +604,8 @@ dprintf("HDA: sample size %ld, num channels %ld, buffer length %ld *************
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stream->Write32(HDAC_STREAM_BUFFERS_BASE_UPPER, 0);
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stream->Write16(HDAC_STREAM_LAST_VALID, stream->num_buffers - 1);
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/* total cyclic buffer size in _bytes_ */
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stream->Write32(HDAC_STREAM_BUFFER_SIZE, stream->sample_size
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* stream->num_channels * stream->num_buffers * stream->buffer_length);
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stream->Write32(HDAC_STREAM_BUFFER_SIZE, bufferSize
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* stream->num_buffers);
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stream->Write8(HDAC_STREAM_CONTROL2, stream->id << 4);
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stream->controller->Write32(HDAC_DMA_POSITION_BASE_LOWER,
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@ -667,8 +673,9 @@ hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, uint32 count)
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status_t
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hda_hw_init(hda_controller* controller)
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{
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uint16 capabilities, stateStatus;
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uint16 capabilities, stateStatus, cmd;
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status_t status;
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uint8 tcsel;
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/* Map MMIO registers */
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controller->regs_area = map_physical_memory("hda_hw_regs",
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@ -680,6 +687,15 @@ hda_hw_init(hda_controller* controller)
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goto error;
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}
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cmd = (gPci->read_pci_config)(controller->pci_info.bus,
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controller->pci_info.device, controller->pci_info.function, PCI_command, 2);
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if (!(cmd & PCI_command_master)) {
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(gPci->write_pci_config)(controller->pci_info.bus,
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controller->pci_info.device, controller->pci_info.function,
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PCI_command, 2, cmd | PCI_command_master);
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dprintf("hda: enabling PCI bus mastering\n");
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}
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/* Absolute minimum hw is online; we can now install interrupt handler */
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controller->irq = controller->pci_info.u.h0.interrupt_line;
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status = install_io_interrupt_handler(controller->irq,
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@ -687,6 +703,13 @@ hda_hw_init(hda_controller* controller)
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if (status != B_OK)
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goto no_irq;
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/* TCSEL is reset to TC0 (clear 0-2 bits) */
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tcsel = (gPci->read_pci_config)(controller->pci_info.bus,
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controller->pci_info.device, controller->pci_info.function, PCI_HDA_TCSEL, 1);
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(gPci->write_pci_config)(controller->pci_info.bus,
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controller->pci_info.device, controller->pci_info.function,
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PCI_HDA_TCSEL, 1, tcsel & 0xf8);
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capabilities = controller->Read16(HDAC_GLOBAL_CAP);
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controller->num_input_streams = GLOBAL_CAP_INPUT_STREAMS(capabilities);
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controller->num_output_streams = GLOBAL_CAP_OUTPUT_STREAMS(capabilities);
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@ -131,6 +131,9 @@
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#define HDAC_STREAM_BUFFERS_BASE_LOWER 0x18 // 32bits, BDPL
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#define HDAC_STREAM_BUFFERS_BASE_UPPER 0x1c // 32bits, BDPU
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/* PCI space register definitions */
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#define PCI_HDA_TCSEL 0x44
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typedef uint32 corb_t;
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typedef struct {
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uint32 response;
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@ -141,7 +144,8 @@ typedef struct {
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#define RESPONSE_FLAGS_UNSOLICITED (1 << 4)
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typedef struct {
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uint64 address;
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uint32 lower;
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uint32 upper;
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uint32 length;
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uint32 ioc;
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} bdl_entry_t;
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