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more dualhead updates

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@6113 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2004-01-17 10:48:18 +00:00
parent 881996e814
commit 16c2f5b1c8
2 changed files with 3 additions and 5 deletions
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6
headers/private/graphics/nvidia/DriverInterface.h
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@ -5,7 +5,7 @@
Other authors: Other authors:
Mark Watson; Mark Watson;
Apsed; Apsed;
Rudolf Cornelissen 10/2002-12/2003. Rudolf Cornelissen 10/2002-1/2004.
*/ */
#ifndef DRIVERINTERFACE_H #ifndef DRIVERINTERFACE_H
@ -145,7 +145,6 @@ typedef struct {
/*more display mode stuff*/ /*more display mode stuff*/
display_mode dm; /* current display mode configuration: head1 */ display_mode dm; /* current display mode configuration: head1 */
display_mode dm2; /* current display mode configuration: head2 */ display_mode dm2; /* current display mode configuration: head2 */
bool switched_crtcs; /* dualhead stretch and switch mode info */
bool acc_mode; /* signals (non)accelerated mode */ bool acc_mode; /* signals (non)accelerated mode */
bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */ bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */
@ -256,9 +255,6 @@ typedef struct {
/* mirror of the ROM (copied in driver, because may not be mapped permanently - only over fb) */ /* mirror of the ROM (copied in driver, because may not be mapped permanently - only over fb) */
uint8 rom_mirror[32768]; uint8 rom_mirror[32768];
/* CRTC delay -> used in timing for MAVEN, depending on which CRTC is driving it */
uint8 crtc_delay;
/* NV31 (FX5600) tweak to get pixelPLL going (unknown register) */ /* NV31 (FX5600) tweak to get pixelPLL going (unknown register) */
uint16 pixpll_vco_div2; uint16 pixpll_vco_div2;

2
headers/private/graphics/nvidia/nv_macros.h
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@ -719,6 +719,8 @@
/* read and write from the dac registers */ /* read and write from the dac registers */
#define DACR(A) (NV_REG32(NVDAC_##A)) #define DACR(A) (NV_REG32(NVDAC_##A))
#define DACW(A,B) (NV_REG32(NVDAC_##A)=B) #define DACW(A,B) (NV_REG32(NVDAC_##A)=B)
/* read and write from the secondary dac registers */
#define DAC2R(A) (NV_REG32(NVDAC2_##A)) #define DAC2R(A) (NV_REG32(NVDAC2_##A))
#define DAC2W(A,B) (NV_REG32(NVDAC2_##A)=B) #define DAC2W(A,B) (NV_REG32(NVDAC2_##A)=B)