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added primary pixelPLL programming and calculations for CLE266/KM400 architectures. K8M800 still needs to be setup (PLL registeradresses and ranges differ here). Although set refreshrates are about 5% too high, you can now decently set any mode you like: as long as you have *some* vesa mode preset (still). Looking at a soothing 75Hz now here :)

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@13792 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2005-07-21 21:35:34 +00:00
parent 71903a151d
commit 16bf7b9598
6 changed files with 39 additions and 56 deletions
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4
src/add-ons/accelerants/via/InitAccelerant.c
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@ -25,7 +25,7 @@ static status_t init_common(int the_fd) {
/* memorize the file descriptor */
fd = the_fd;
/* set the magic number so the driver knows we're for real */
gpd.magic = SKEL_PRIVATE_DATA_MAGIC;
gpd.magic = VIA_PRIVATE_DATA_MAGIC;
/* contact driver and get a pointer to the registers and shared data */
result = ioctl(fd, ENG_GET_PRIVATE_DATA, &gpd, sizeof(gpd));
if (result != B_OK) goto error0;
@ -224,7 +224,7 @@ void GET_ACCELERANT_CLONE_INFO(void *data) {
status_t result;
/* call the kernel driver to get the device name */
dn.magic = SKEL_PRIVATE_DATA_MAGIC;
dn.magic = VIA_PRIVATE_DATA_MAGIC;
/* store the returned info directly into the passed buffer */
dn.name = (char *)data;
result = ioctl(fd, ENG_DEVICE_NAME, &dn, sizeof(dn));

9
src/add-ons/accelerants/via/SetDisplayMode.c
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@ -22,7 +22,7 @@ static void interrupt_enable(bool flag) {
eng_set_bool_state sbs;
/* set the magic number so the driver knows we're for real */
sbs.magic = SKEL_PRIVATE_DATA_MAGIC;
sbs.magic = VIA_PRIVATE_DATA_MAGIC;
sbs.do_it = flag;
/* contact driver and get a pointer to the registers and shared data */
result = ioctl(fd, ENG_RUN_INTERRUPTS, &sbs, sizeof(sbs));
@ -138,8 +138,8 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
/* set the pixel clock PLL(s) */
LOG(8,("SETMODE: target clock %dkHz\n",target.timing.pixel_clock));
// if (head1_set_pix_pll(target) == B_ERROR)
// LOG(8,("SETMODE: error setting pixel clock (internal DAC)\n"));
if (head1_set_pix_pll(target) == B_ERROR)
LOG(8,("SETMODE: error setting pixel clock (internal DAC)\n"));
/* we do not need to set the pixelclock here for a head that's in TVout mode */
// if (!(target2.flags & TV_BITS))
@ -278,8 +278,7 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
}
/* set the pixel clock PLL */
// status = head1_set_pix_pll(target);
status = B_OK;
status = head1_set_pix_pll(target);
if (status==B_ERROR)
LOG(8,("CRTC: error setting pixel clock (internal DAC)\n"));

6
src/add-ons/accelerants/via/engine/agp.c
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@ -36,8 +36,8 @@ status_t eng_agp_setup(void)
// LOG(4, ("AGP: STRAPINFO2 now contains $%08x\n", ENG_REG32(RG32_NVSTRAPINFO2)));
// }
/* set the magic number so the skeleton kerneldriver knows we're for real */
nca.magic = nai.magic = SKEL_PRIVATE_DATA_MAGIC;
/* set the magic number so the via kerneldriver knows we're for real */
nca.magic = nai.magic = VIA_PRIVATE_DATA_MAGIC;
/* contact driver and get a pointer to the registers and shared data */
for (index = 0; index < 8; index++)
@ -105,7 +105,7 @@ status_t eng_agp_setup(void)
if (si->settings.force_pci)
{
/* set PCI mode if specified by user in skel.settings */
LOG(4,("AGP: forcing PCI mode (specified in skel.settings)\n"));
LOG(4,("AGP: forcing PCI mode (specified in via.settings)\n"));
/* let the AGP busmanager setup PCI mode.
* (the AGP speed scheme is of no consequence now) */

67
src/add-ons/accelerants/via/engine/dac.c
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@ -7,7 +7,7 @@
#include "std.h"
static status_t nv4_nv10_nv20_dac_pix_pll_find(
static status_t cle266_km400_dac_pix_pll_find(
display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test);
/* see if an analog VGA monitor is connected to connector #1 */
@ -155,16 +155,16 @@ status_t eng_dac_set_pix_pll(display_mode target)
* note:
* this assumes the cards BIOS correctly programmed the panel (is likely) */
//fixme: when VESA DDC EDID stuff is implemented, this option can be deleted...
if (si->ps.tmds1_active && !si->settings.pgm_panel)
if (0)//si->ps.tmds1_active && !si->settings.pgm_panel)
{
LOG(4,("DAC: Not programming DFP refresh (specified in skel.settings)\n"));
LOG(4,("DAC: Not programming DFP refresh (specified in via.settings)\n"));
return B_OK;
}
/* fix a DVI or laptop flatpanel to 60Hz refresh! */
/* Note:
* The pixelclock drives the flatpanel modeline, not the CRTC modeline. */
if (si->ps.tmds1_active)
if (0)//si->ps.tmds1_active)
{
LOG(4,("DAC: Fixing DFP refresh to 60Hz!\n"));
@ -187,13 +187,16 @@ status_t eng_dac_set_pix_pll(display_mode target)
// DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0C)|0x01); /*select the PIXPLL*/
/* program new frequency */
DACW(PIXPLLC, ((p << 16) | (n << 8) | m));
/* program 2nd set N and M scalers if they exist (b31=1 enables them) */
if (si->ps.ext_pll) DACW(PIXPLLC2, 0x80000401);
//fixme: add K8M800 programming and calcs!! (these differ, plus extended) <<<<<
if (si->ps.card_arch != K8M800)
{
/* fixme: b7 is a lock-indicator or a filter select: to be determined! */
SEQW(PPLL_N_CLE, (n & 0x7f));
SEQW(PPLL_MP_CLE, ((m & 0x3f) | ((p & 0x03) << 6)));
}
/* Wait for the PIXPLL frequency to lock until timeout occurs */
//fixme: do NV cards have a LOCK indication bit??
//fixme: do VIA cards have a LOCK indication bit??
/* while((!(DXIR(PIXPLLSTAT)&0x40)) & (time <= 2000))
{
time++;
@ -220,13 +223,13 @@ status_t eng_dac_pix_pll_find
(display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test)
{
switch (si->ps.card_type) {
default: return nv4_nv10_nv20_dac_pix_pll_find(target, calc_pclk, m_result, n_result, p_result, test);
default: return cle266_km400_dac_pix_pll_find(target, calc_pclk, m_result, n_result, p_result, test);
}
return B_ERROR;
}
/* find nearest valid pixel PLL setting */
static status_t nv4_nv10_nv20_dac_pix_pll_find(
static status_t cle266_km400_dac_pix_pll_find(
display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test)
{
int m = 0, n = 0, p = 0/*, m_max*/;
@ -253,7 +256,7 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find(
break;
}
*/
LOG(4,("DAC: NV4/NV10/NV20 restrictions apply\n"));
LOG(4,("DAC: CLE266/KM400 restrictions apply\n"));
/* determine the max. pixelclock for the current videomode */
switch (target.space)
@ -282,11 +285,11 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find(
/* Make sure the requested pixelclock is within the PLL's operational limits */
/* lower limit is min_pixel_vco divided by highest postscaler-factor */
if (req_pclk < (si->ps.min_pixel_vco / 16.0))
if (req_pclk < (si->ps.min_pixel_vco / 8.0))
{
LOG(4,("DAC: clamping pixclock: requested %fMHz, set to %fMHz\n",
req_pclk, (float)(si->ps.min_pixel_vco / 16.0)));
req_pclk = (si->ps.min_pixel_vco / 16.0);
req_pclk, (float)(si->ps.min_pixel_vco / 8.0)));
req_pclk = (si->ps.min_pixel_vco / 8.0);
}
/* upper limit is given by pins in combination with current active mode */
if (req_pclk > max_pclk)
@ -297,7 +300,7 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find(
}
/* iterate through all valid PLL postscaler settings */
for (p=0x01; p < 0x20; p = p<<1)
for (p = 0x01; p < 0x10; p = p << 1)
{
/* calculate the needed VCO frequency for this postscaler setting */
f_vco = req_pclk * p;
@ -305,37 +308,22 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find(
/* check if this is within range of the VCO specs */
if ((f_vco >= si->ps.min_pixel_vco) && (f_vco <= si->ps.max_pixel_vco))
{
/* FX5600 and FX5700 tweak for 2nd set N and M scalers */
if (si->ps.ext_pll) f_vco /= 4;
/* iterate trough all valid reference-frequency postscaler settings */
for (m = 7; m <= 14; m++)
for (m = 1; m <= 63; m++)
{
/* check if phase-discriminator will be within operational limits */
//fixme: PLL calcs will be resetup/splitup/updated...
if (si->ps.card_type == NV36)
{
if (((si->ps.f_ref / m) < 3.2) || ((si->ps.f_ref / m) > 6.4)) continue;
}
else
{
if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue;
}
/* (range as used by VESA BIOS on CLE266, verified.) */
if (((si->ps.f_ref / m) < 2.0) || ((si->ps.f_ref / m) > 3.6)) continue;
/* calculate VCO postscaler setting for current setup.. */
n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);
/* ..and check for validity */
if ((n < 1) || (n > 255)) continue;
/* (checked VESA BIOS on CLE266, b7 is NOT part of divider.) */
if ((n < 1) || (n > 127)) continue;
/* find error in frequency this setting gives */
if (si->ps.ext_pll)
{
/* FX5600 and FX5700 tweak for 2nd set N and M scalers */
error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p));
}
else
error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p));
error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p));
/* note the setting if best yet */
if (error < error_best)
@ -356,8 +344,6 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find(
/* log the VCO frequency found */
f_vco = ((si->ps.f_ref / m) * n);
/* FX5600 and FX5700 tweak for 2nd set N and M scalers */
if (si->ps.ext_pll) f_vco *= 4;
LOG(2,("DAC: pix VCO frequency found %fMhz\n", f_vco));
@ -379,9 +365,6 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find(
case 8:
p = 0x03;
break;
case 16:
p = 0x04;
break;
}
*p_result = p;

4
src/add-ons/accelerants/via/engine/globals.c
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@ -20,7 +20,7 @@ int accelerantIsClone;
eng_get_set_pci eng_pci_access=
{
SKEL_PRIVATE_DATA_MAGIC,
VIA_PRIVATE_DATA_MAGIC,
0,
4,
0
@ -28,7 +28,7 @@ eng_get_set_pci eng_pci_access=
eng_in_out_isa eng_isa_access=
{
SKEL_PRIVATE_DATA_MAGIC,
VIA_PRIVATE_DATA_MAGIC,
0,
1,
0

5
src/add-ons/accelerants/via/engine/info.c
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@ -695,13 +695,14 @@ void get_panel_modes(display_mode *p1, display_mode *p2, bool *pan1, bool *pan2)
static void pins_cle266_fake(void)
{
si->ps.f_ref = 14.31818;
/* we have a standard PLL */
si->ps.ext_pll = false;
/* carefull not to take to high limits, and high should be >= 2x low. */
si->ps.max_system_vco = 230;
si->ps.min_system_vco = 20;
si->ps.max_pixel_vco = 230;
si->ps.min_pixel_vco = 20;
si->ps.max_pixel_vco = 400; /* VESA BIOS uses upto 433Mhz */
si->ps.min_pixel_vco = 50; /* VESA BIOS uses downto 53.2Mhz */
si->ps.max_video_vco = 0;
si->ps.min_video_vco = 0;
si->ps.max_dac1_clock = 230;