added primary pixelPLL programming and calculations for CLE266/KM400 architectures. K8M800 still needs to be setup (PLL registeradresses and ranges differ here). Although set refreshrates are about 5% too high, you can now decently set any mode you like: as long as you have *some* vesa mode preset (still). Looking at a soothing 75Hz now here :)
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@13792 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
parent
71903a151d
commit
16bf7b9598
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@ -25,7 +25,7 @@ static status_t init_common(int the_fd) {
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/* memorize the file descriptor */
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fd = the_fd;
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/* set the magic number so the driver knows we're for real */
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gpd.magic = SKEL_PRIVATE_DATA_MAGIC;
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gpd.magic = VIA_PRIVATE_DATA_MAGIC;
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/* contact driver and get a pointer to the registers and shared data */
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result = ioctl(fd, ENG_GET_PRIVATE_DATA, &gpd, sizeof(gpd));
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if (result != B_OK) goto error0;
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@ -224,7 +224,7 @@ void GET_ACCELERANT_CLONE_INFO(void *data) {
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status_t result;
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/* call the kernel driver to get the device name */
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dn.magic = SKEL_PRIVATE_DATA_MAGIC;
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dn.magic = VIA_PRIVATE_DATA_MAGIC;
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/* store the returned info directly into the passed buffer */
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dn.name = (char *)data;
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result = ioctl(fd, ENG_DEVICE_NAME, &dn, sizeof(dn));
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@ -22,7 +22,7 @@ static void interrupt_enable(bool flag) {
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eng_set_bool_state sbs;
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/* set the magic number so the driver knows we're for real */
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sbs.magic = SKEL_PRIVATE_DATA_MAGIC;
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sbs.magic = VIA_PRIVATE_DATA_MAGIC;
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sbs.do_it = flag;
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/* contact driver and get a pointer to the registers and shared data */
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result = ioctl(fd, ENG_RUN_INTERRUPTS, &sbs, sizeof(sbs));
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@ -138,8 +138,8 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
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/* set the pixel clock PLL(s) */
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LOG(8,("SETMODE: target clock %dkHz\n",target.timing.pixel_clock));
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// if (head1_set_pix_pll(target) == B_ERROR)
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// LOG(8,("SETMODE: error setting pixel clock (internal DAC)\n"));
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if (head1_set_pix_pll(target) == B_ERROR)
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LOG(8,("SETMODE: error setting pixel clock (internal DAC)\n"));
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/* we do not need to set the pixelclock here for a head that's in TVout mode */
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// if (!(target2.flags & TV_BITS))
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@ -278,8 +278,7 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
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}
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/* set the pixel clock PLL */
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// status = head1_set_pix_pll(target);
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status = B_OK;
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status = head1_set_pix_pll(target);
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if (status==B_ERROR)
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LOG(8,("CRTC: error setting pixel clock (internal DAC)\n"));
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@ -36,8 +36,8 @@ status_t eng_agp_setup(void)
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// LOG(4, ("AGP: STRAPINFO2 now contains $%08x\n", ENG_REG32(RG32_NVSTRAPINFO2)));
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// }
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/* set the magic number so the skeleton kerneldriver knows we're for real */
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nca.magic = nai.magic = SKEL_PRIVATE_DATA_MAGIC;
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/* set the magic number so the via kerneldriver knows we're for real */
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nca.magic = nai.magic = VIA_PRIVATE_DATA_MAGIC;
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/* contact driver and get a pointer to the registers and shared data */
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for (index = 0; index < 8; index++)
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@ -105,7 +105,7 @@ status_t eng_agp_setup(void)
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if (si->settings.force_pci)
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{
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/* set PCI mode if specified by user in skel.settings */
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LOG(4,("AGP: forcing PCI mode (specified in skel.settings)\n"));
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LOG(4,("AGP: forcing PCI mode (specified in via.settings)\n"));
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/* let the AGP busmanager setup PCI mode.
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* (the AGP speed scheme is of no consequence now) */
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@ -7,7 +7,7 @@
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#include "std.h"
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static status_t nv4_nv10_nv20_dac_pix_pll_find(
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static status_t cle266_km400_dac_pix_pll_find(
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display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test);
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/* see if an analog VGA monitor is connected to connector #1 */
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@ -155,16 +155,16 @@ status_t eng_dac_set_pix_pll(display_mode target)
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* note:
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* this assumes the cards BIOS correctly programmed the panel (is likely) */
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//fixme: when VESA DDC EDID stuff is implemented, this option can be deleted...
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if (si->ps.tmds1_active && !si->settings.pgm_panel)
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if (0)//si->ps.tmds1_active && !si->settings.pgm_panel)
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{
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LOG(4,("DAC: Not programming DFP refresh (specified in skel.settings)\n"));
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LOG(4,("DAC: Not programming DFP refresh (specified in via.settings)\n"));
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return B_OK;
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}
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/* fix a DVI or laptop flatpanel to 60Hz refresh! */
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/* Note:
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* The pixelclock drives the flatpanel modeline, not the CRTC modeline. */
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if (si->ps.tmds1_active)
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if (0)//si->ps.tmds1_active)
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{
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LOG(4,("DAC: Fixing DFP refresh to 60Hz!\n"));
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@ -187,13 +187,16 @@ status_t eng_dac_set_pix_pll(display_mode target)
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// DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0C)|0x01); /*select the PIXPLL*/
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/* program new frequency */
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DACW(PIXPLLC, ((p << 16) | (n << 8) | m));
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/* program 2nd set N and M scalers if they exist (b31=1 enables them) */
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if (si->ps.ext_pll) DACW(PIXPLLC2, 0x80000401);
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//fixme: add K8M800 programming and calcs!! (these differ, plus extended) <<<<<
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if (si->ps.card_arch != K8M800)
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{
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/* fixme: b7 is a lock-indicator or a filter select: to be determined! */
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SEQW(PPLL_N_CLE, (n & 0x7f));
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SEQW(PPLL_MP_CLE, ((m & 0x3f) | ((p & 0x03) << 6)));
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}
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/* Wait for the PIXPLL frequency to lock until timeout occurs */
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//fixme: do NV cards have a LOCK indication bit??
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//fixme: do VIA cards have a LOCK indication bit??
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/* while((!(DXIR(PIXPLLSTAT)&0x40)) & (time <= 2000))
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{
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time++;
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@ -220,13 +223,13 @@ status_t eng_dac_pix_pll_find
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(display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test)
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{
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switch (si->ps.card_type) {
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default: return nv4_nv10_nv20_dac_pix_pll_find(target, calc_pclk, m_result, n_result, p_result, test);
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default: return cle266_km400_dac_pix_pll_find(target, calc_pclk, m_result, n_result, p_result, test);
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}
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return B_ERROR;
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}
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/* find nearest valid pixel PLL setting */
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static status_t nv4_nv10_nv20_dac_pix_pll_find(
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static status_t cle266_km400_dac_pix_pll_find(
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display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test)
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{
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int m = 0, n = 0, p = 0/*, m_max*/;
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@ -253,7 +256,7 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find(
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break;
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}
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*/
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LOG(4,("DAC: NV4/NV10/NV20 restrictions apply\n"));
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LOG(4,("DAC: CLE266/KM400 restrictions apply\n"));
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/* determine the max. pixelclock for the current videomode */
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switch (target.space)
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@ -282,11 +285,11 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find(
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/* Make sure the requested pixelclock is within the PLL's operational limits */
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/* lower limit is min_pixel_vco divided by highest postscaler-factor */
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if (req_pclk < (si->ps.min_pixel_vco / 16.0))
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if (req_pclk < (si->ps.min_pixel_vco / 8.0))
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{
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LOG(4,("DAC: clamping pixclock: requested %fMHz, set to %fMHz\n",
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req_pclk, (float)(si->ps.min_pixel_vco / 16.0)));
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req_pclk = (si->ps.min_pixel_vco / 16.0);
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req_pclk, (float)(si->ps.min_pixel_vco / 8.0)));
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req_pclk = (si->ps.min_pixel_vco / 8.0);
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}
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/* upper limit is given by pins in combination with current active mode */
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if (req_pclk > max_pclk)
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@ -297,7 +300,7 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find(
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}
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/* iterate through all valid PLL postscaler settings */
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for (p=0x01; p < 0x20; p = p<<1)
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for (p = 0x01; p < 0x10; p = p << 1)
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{
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/* calculate the needed VCO frequency for this postscaler setting */
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f_vco = req_pclk * p;
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@ -305,37 +308,22 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find(
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/* check if this is within range of the VCO specs */
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if ((f_vco >= si->ps.min_pixel_vco) && (f_vco <= si->ps.max_pixel_vco))
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{
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/* FX5600 and FX5700 tweak for 2nd set N and M scalers */
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if (si->ps.ext_pll) f_vco /= 4;
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/* iterate trough all valid reference-frequency postscaler settings */
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for (m = 7; m <= 14; m++)
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for (m = 1; m <= 63; m++)
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{
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/* check if phase-discriminator will be within operational limits */
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//fixme: PLL calcs will be resetup/splitup/updated...
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if (si->ps.card_type == NV36)
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{
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if (((si->ps.f_ref / m) < 3.2) || ((si->ps.f_ref / m) > 6.4)) continue;
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}
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else
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{
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if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue;
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}
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/* (range as used by VESA BIOS on CLE266, verified.) */
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if (((si->ps.f_ref / m) < 2.0) || ((si->ps.f_ref / m) > 3.6)) continue;
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/* calculate VCO postscaler setting for current setup.. */
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n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);
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/* ..and check for validity */
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if ((n < 1) || (n > 255)) continue;
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/* (checked VESA BIOS on CLE266, b7 is NOT part of divider.) */
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if ((n < 1) || (n > 127)) continue;
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/* find error in frequency this setting gives */
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if (si->ps.ext_pll)
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{
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/* FX5600 and FX5700 tweak for 2nd set N and M scalers */
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error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p));
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}
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else
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error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p));
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error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p));
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/* note the setting if best yet */
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if (error < error_best)
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@ -356,8 +344,6 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find(
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/* log the VCO frequency found */
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f_vco = ((si->ps.f_ref / m) * n);
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/* FX5600 and FX5700 tweak for 2nd set N and M scalers */
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if (si->ps.ext_pll) f_vco *= 4;
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LOG(2,("DAC: pix VCO frequency found %fMhz\n", f_vco));
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@ -379,9 +365,6 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find(
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case 8:
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p = 0x03;
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break;
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case 16:
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p = 0x04;
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break;
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}
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*p_result = p;
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@ -20,7 +20,7 @@ int accelerantIsClone;
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eng_get_set_pci eng_pci_access=
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{
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SKEL_PRIVATE_DATA_MAGIC,
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VIA_PRIVATE_DATA_MAGIC,
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0,
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4,
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0
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@ -28,7 +28,7 @@ eng_get_set_pci eng_pci_access=
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eng_in_out_isa eng_isa_access=
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{
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SKEL_PRIVATE_DATA_MAGIC,
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VIA_PRIVATE_DATA_MAGIC,
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0,
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1,
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0
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@ -695,13 +695,14 @@ void get_panel_modes(display_mode *p1, display_mode *p2, bool *pan1, bool *pan2)
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static void pins_cle266_fake(void)
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{
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si->ps.f_ref = 14.31818;
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/* we have a standard PLL */
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si->ps.ext_pll = false;
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/* carefull not to take to high limits, and high should be >= 2x low. */
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si->ps.max_system_vco = 230;
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si->ps.min_system_vco = 20;
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si->ps.max_pixel_vco = 230;
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si->ps.min_pixel_vco = 20;
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si->ps.max_pixel_vco = 400; /* VESA BIOS uses upto 433Mhz */
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si->ps.min_pixel_vco = 50; /* VESA BIOS uses downto 53.2Mhz */
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si->ps.max_video_vco = 0;
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si->ps.min_video_vco = 0;
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si->ps.max_dac1_clock = 230;
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