* Added Broadcom BCM570x driver from FreeBSD (bge). Does not compile yet, needs
a bit more work on the compatibility layer. * Added nVidia nForce MCP driver (nfe) from FreeBSD. Compiles and might even work - please test. It would also be nice to know if your PHY is detected correctly (see syslog output). git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@23124 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler
parent
3fffcad10d
commit
1607b8e503
@ -12,10 +12,12 @@ SubInclude HAIKU_TOP src add-ons kernel drivers network via_rhine ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network vlance ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network wb840 ;
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# FreeBSD 6.2 drivers
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# FreeBSD 7 drivers
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SubInclude HAIKU_TOP src add-ons kernel drivers network 3com ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network broadcom_bcm570x ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network ipro100 ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network marvell_yukon ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network nforce ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network pcnet ;
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SubIncludeGPL HAIKU_TOP src add-ons kernel drivers network bcm440x ;
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@ -0,0 +1,3 @@
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SubDir HAIKU_TOP src add-ons kernel drivers network broadcom_bcm570x ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network broadcom_bcm570x dev ;
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@ -0,0 +1,4 @@
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SubDir HAIKU_TOP src add-ons kernel drivers network broadcom_bcm570x dev ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network broadcom_bcm570x dev bge ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network broadcom_bcm570x dev mii ;
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@ -0,0 +1,18 @@
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SubDir HAIKU_TOP src add-ons kernel drivers network broadcom_bcm570x dev bge ;
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SubDirCcFlags -Wall ;
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UsePrivateHeaders kernel net ;
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UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ;
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UseHeaders [ FDirName $(SUBDIR) .. mii ] : true ;
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UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
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SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ;
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KernelAddon broadcom_bcm570x :
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if_bge.c
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glue.c
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: libfreebsd_network.a broadcom_bcm570x_mii.a
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;
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@ -0,0 +1,27 @@
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/*
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* Copyright 2007, Axel Dörfler, axeld@pinc-software.de. All Rights Reserved.
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* Distributed under the terms of the MIT License.
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*/
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#include <sys/bus.h>
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HAIKU_FBSD_DRIVER_GLUE(broadcom_bcm570x, bge, pci);
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HAIKU_DRIVER_REQUIREMENTS(FBSD_TASKQUEUES | FBSD_SWI_TASKQUEUE);
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extern driver_t *DRIVER_MODULE_NAME(ukphy, miibus);
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driver_t *
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__haiku_select_miibus_driver(device_t dev)
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{
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driver_t *drivers[] = {
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DRIVER_MODULE_NAME(ukphy, miibus),
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NULL
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};
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return __haiku_probe_miibus(dev, drivers);
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}
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4539
src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/bge/if_bge.c
Normal file
4539
src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/bge/if_bge.c
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,15 @@
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SubDir HAIKU_TOP src add-ons kernel drivers network broadcom_bcm570x dev mii ;
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UsePrivateHeaders kernel net ;
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UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ;
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UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
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SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ;
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KernelStaticLibrary broadcom_bcm570x_mii.a
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:
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ukphy.c
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ukphy_subr.c
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;
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@ -0,0 +1,364 @@
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/*-
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* Copyright (c) 2000
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* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD: src/sys/dev/mii/brgphyreg.h,v 1.10 2007/06/07 02:21:38 davidch Exp $
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*/
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#ifndef _DEV_MII_BRGPHYREG_H_
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#define _DEV_MII_BRGPHYREG_H_
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/*
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* Broadcom BCM5400 registers
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*/
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#define BRGPHY_MII_BMCR 0x00
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#define BRGPHY_BMCR_RESET 0x8000
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#define BRGPHY_BMCR_LOOP 0x4000
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#define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
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#define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
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#define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */
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#define BRGPHY_BMCR_ISO 0x0400 /* Isolate */
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#define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
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#define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */
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#define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
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#define BRGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
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#define BRGPHY_S1000 BRGPHY_BMCR_SPD1 /* 1000mbps */
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#define BRGPHY_S100 BRGPHY_BMCR_SPD0 /* 100mpbs */
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#define BRGPHY_S10 0 /* 10mbps */
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#define BRGPHY_MII_BMSR 0x01
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#define BRGPHY_BMSR_EXTSTS 0x0100 /* Extended status present */
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#define BRGPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */
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#define BRGPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */
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#define BRGPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */
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#define BRGPHY_BMSR_ANEG 0x0008 /* Autoneg capable */
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#define BRGPHY_BMSR_LINK 0x0004 /* Link status */
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#define BRGPHY_BMSR_JABBER 0x0002 /* Jabber detected */
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#define BRGPHY_BMSR_EXT 0x0001 /* Extended capability */
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#define BRGPHY_MII_ANAR 0x04
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#define BRGPHY_ANAR_NP 0x8000 /* Next page */
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#define BRGPHY_ANAR_RF 0x2000 /* Remote fault */
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#define BRGPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */
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#define BRGPHY_ANAR_PC 0x0400 /* Pause capable */
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#define BRGPHY_ANAR_SEL 0x001F /* Selector field, 00001=Ethernet */
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#define BRGPHY_MII_ANLPAR 0x05
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#define BRGPHY_ANLPAR_NP 0x8000 /* Next page */
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#define BRGPHY_ANLPAR_RF 0x2000 /* Remote fault */
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#define BRGPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */
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#define BRGPHY_ANLPAR_PC 0x0400 /* Pause capable */
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#define BRGPHY_ANLPAR_SEL 0x001F /* Selector field, 00001=Ethernet */
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#define BRGPHY_SEL_TYPE 0x0001 /* Ethernet */
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#define BRGPHY_MII_ANER 0x06
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#define BRGPHY_ANER_PDF 0x0010 /* Parallel detection fault */
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#define BRGPHY_ANER_LPNP 0x0008 /* Link partner can next page */
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#define BRGPHY_ANER_NP 0x0004 /* Local PHY can next page */
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#define BRGPHY_ANER_RX 0x0002 /* Next page received */
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#define BRGPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */
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#define BRGPHY_MII_NEXTP 0x07 /* Next page */
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#define BRGPHY_MII_NEXTP_LP 0x08 /* Next page of link partner */
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#define BRGPHY_MII_1000CTL 0x09 /* 1000baseT control */
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#define BRGPHY_1000CTL_TST 0xE000 /* Test modes */
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#define BRGPHY_1000CTL_MSE 0x1000 /* Master/Slave enable */
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#define BRGPHY_1000CTL_MSC 0x0800 /* Master/Slave configuration */
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#define BRGPHY_1000CTL_RD 0x0400 /* Repeater/DTE */
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#define BRGPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */
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#define BRGPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */
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#define BRGPHY_MII_1000STS 0x0A /* 1000baseT status */
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#define BRGPHY_1000STS_MSF 0x8000 /* Master/slave fault */
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#define BRGPHY_1000STS_MSR 0x4000 /* Master/slave result */
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#define BRGPHY_1000STS_LRS 0x2000 /* Local receiver status */
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#define BRGPHY_1000STS_RRS 0x1000 /* Remote receiver status */
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#define BRGPHY_1000STS_LPFD 0x0800 /* Link partner can FD */
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#define BRGPHY_1000STS_LPHD 0x0400 /* Link partner can HD */
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#define BRGPHY_1000STS_IEC 0x00FF /* Idle error count */
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#define BRGPHY_MII_EXTSTS 0x0F /* Extended status */
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#define BRGPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
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#define BRGPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
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#define BRGPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
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#define BRGPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
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#define BRGPHY_MII_PHY_EXTCTL 0x10 /* PHY extended control */
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#define BRGPHY_PHY_EXTCTL_MAC_PHY 0x8000 /* 10BIT/GMI-interface */
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#define BRGPHY_PHY_EXTCTL_DIS_CROSS 0x4000 /* Disable MDI crossover */
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#define BRGPHY_PHY_EXTCTL_TX_DIS 0x2000 /* TX output disabled */
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#define BRGPHY_PHY_EXTCTL_INT_DIS 0x1000 /* Interrupts disabled */
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#define BRGPHY_PHY_EXTCTL_F_INT 0x0800 /* Force interrupt */
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#define BRGPHY_PHY_EXTCTL_BY_45 0x0400 /* Bypass 4B5B-Decoder */
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#define BRGPHY_PHY_EXTCTL_BY_SCR 0x0200 /* Bypass scrambler */
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#define BRGPHY_PHY_EXTCTL_BY_MLT3 0x0100 /* Bypass MLT3 encoder */
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#define BRGPHY_PHY_EXTCTL_BY_RXA 0x0080 /* Bypass RX alignment */
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#define BRGPHY_PHY_EXTCTL_RES_SCR 0x0040 /* Reset scrambler */
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#define BRGPHY_PHY_EXTCTL_EN_LTR 0x0020 /* Enable LED traffic mode */
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#define BRGPHY_PHY_EXTCTL_LED_ON 0x0010 /* Force LEDs on */
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#define BRGPHY_PHY_EXTCTL_LED_OFF 0x0008 /* Force LEDs off */
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#define BRGPHY_PHY_EXTCTL_EX_IPG 0x0004 /* Extended TX IPG mode */
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#define BRGPHY_PHY_EXTCTL_3_LED 0x0002 /* Three link LED mode */
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#define BRGPHY_PHY_EXTCTL_HIGH_LA 0x0001 /* GMII Fifo Elasticy (?) */
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#define BRGPHY_MII_PHY_EXTSTS 0x11 /* PHY extended status */
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#define BRGPHY_PHY_EXTSTS_CROSS_STAT 0x2000 /* MDI crossover status */
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#define BRGPHY_PHY_EXTSTS_INT_STAT 0x1000 /* Interrupt status */
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#define BRGPHY_PHY_EXTSTS_RRS 0x0800 /* Remote receiver status */
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#define BRGPHY_PHY_EXTSTS_LRS 0x0400 /* Local receiver status */
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#define BRGPHY_PHY_EXTSTS_LOCKED 0x0200 /* Locked */
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#define BRGPHY_PHY_EXTSTS_LS 0x0100 /* Link status */
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#define BRGPHY_PHY_EXTSTS_RF 0x0080 /* Remove fault */
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#define BRGPHY_PHY_EXTSTS_CE_ER 0x0040 /* Carrier ext error */
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#define BRGPHY_PHY_EXTSTS_BAD_SSD 0x0020 /* Bad SSD */
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#define BRGPHY_PHY_EXTSTS_BAD_ESD 0x0010 /* Bad ESS */
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#define BRGPHY_PHY_EXTSTS_RX_ER 0x0008 /* RX error */
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#define BRGPHY_PHY_EXTSTS_TX_ER 0x0004 /* TX error */
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#define BRGPHY_PHY_EXTSTS_LOCK_ER 0x0002 /* Lock error */
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#define BRGPHY_PHY_EXTSTS_MLT3_ER 0x0001 /* MLT3 code error */
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#define BRGPHY_MII_RXERRCNT 0x12 /* RX error counter */
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#define BRGPHY_MII_FCERRCNT 0x13 /* False carrier sense counter */
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#define BGRPHY_FCERRCNT 0x00FF /* False carrier counter */
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#define BRGPHY_MII_RXNOCNT 0x14 /* RX not OK counter */
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#define BRGPHY_RXNOCNT_LOCAL 0xFF00 /* Local RX not OK counter */
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#define BRGPHY_RXNOCNT_REMOTE 0x00FF /* Local RX not OK counter */
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#define BRGPHY_MII_DSP_RW_PORT 0x15 /* DSP coefficient r/w port */
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#define BRGPHY_MII_DSP_ADDR_REG 0x17 /* DSP coefficient addr register */
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#define BRGPHY_DSP_TAP_NUMBER_MASK 0x00
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#define BRGPHY_DSP_AGC_A 0x00
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#define BRGPHY_DSP_AGC_B 0x01
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#define BRGPHY_DSP_MSE_PAIR_STATUS 0x02
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#define BRGPHY_DSP_SOFT_DECISION 0x03
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#define BRGPHY_DSP_PHASE_REG 0x04
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#define BRGPHY_DSP_SKEW 0x05
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#define BRGPHY_DSP_POWER_SAVER_UPPER_BOUND 0x06
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#define BRGPHY_DSP_POWER_SAVER_LOWER_BOUND 0x07
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#define BRGPHY_DSP_LAST_ECHO 0x08
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#define BRGPHY_DSP_FREQUENCY 0x09
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#define BRGPHY_DSP_PLL_BANDWIDTH 0x0A
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#define BRGPHY_DSP_PLL_PHASE_OFFSET 0x0B
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#define BRGPHYDSP_FILTER_DCOFFSET 0x0C00
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#define BRGPHY_DSP_FILTER_FEXT3 0x0B00
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#define BRGPHY_DSP_FILTER_FEXT2 0x0A00
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#define BRGPHY_DSP_FILTER_FEXT1 0x0900
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#define BRGPHY_DSP_FILTER_FEXT0 0x0800
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#define BRGPHY_DSP_FILTER_NEXT3 0x0700
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#define BRGPHY_DSP_FILTER_NEXT2 0x0600
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#define BRGPHY_DSP_FILTER_NEXT1 0x0500
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#define BRGPHY_DSP_FILTER_NEXT0 0x0400
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#define BRGPHY_DSP_FILTER_ECHO 0x0300
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#define BRGPHY_DSP_FILTER_DFE 0x0200
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#define BRGPHY_DSP_FILTER_FFE 0x0100
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#define BRGPHY_DSP_CONTROL_ALL_FILTERS 0x1000
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#define BRGPHY_DSP_SEL_CH_0 0x0000
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#define BRGPHY_DSP_SEL_CH_1 0x2000
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#define BRGPHY_DSP_SEL_CH_2 0x4000
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#define BRGPHY_DSP_SEL_CH_3 0x6000
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#define BRGPHY_MII_AUXCTL 0x18 /* AUX control */
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#define BRGPHY_AUXCTL_LOW_SQ 0x8000 /* Low squelch */
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#define BRGPHY_AUXCTL_LONG_PKT 0x4000 /* RX long packets */
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#define BRGPHY_AUXCTL_ER_CTL 0x3000 /* Edgerate control */
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#define BRGPHY_AUXCTL_TX_TST 0x0400 /* TX test, always 1 */
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#define BRGPHY_AUXCTL_DIS_PRF 0x0080 /* dis part resp filter */
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#define BRGPHY_AUXCTL_DIAG_MODE 0x0004 /* Diagnostic mode */
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#define BRGPHY_MII_AUXSTS 0x19 /* AUX status */
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#define BRGPHY_AUXSTS_ACOMP 0x8000 /* Autoneg complete */
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#define BRGPHY_AUXSTS_AN_ACK 0x4000 /* Autoneg complete ack */
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#define BRGPHY_AUXSTS_AN_ACK_D 0x2000 /* Autoneg complete ack detect */
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#define BRGPHY_AUXSTS_AN_NPW 0x1000 /* Autoneg next page wait */
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#define BRGPHY_AUXSTS_AN_RES 0x0700 /* Autoneg HCD */
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#define BRGPHY_AUXSTS_PDF 0x0080 /* Parallel detect. fault */
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#define BRGPHY_AUXSTS_RF 0x0040 /* Remote fault */
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#define BRGPHY_AUXSTS_ANP_R 0x0020 /* Autoneg page received */
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#define BRGPHY_AUXSTS_LP_ANAB 0x0010 /* Link partner autoneg ability */
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#define BRGPHY_AUXSTS_LP_NPAB 0x0008 /* Link partner next page ability */
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#define BRGPHY_AUXSTS_LINK 0x0004 /* Link status */
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#define BRGPHY_AUXSTS_PRR 0x0002 /* Pause resolution-RX */
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#define BRGPHY_AUXSTS_PRT 0x0001 /* Pause resolution-TX */
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#define BRGPHY_RES_1000FD 0x0700 /* 1000baseT full duplex */
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#define BRGPHY_RES_1000HD 0x0600 /* 1000baseT half duplex */
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#define BRGPHY_RES_100FD 0x0500 /* 100baseT full duplex */
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#define BRGPHY_RES_100T4 0x0400 /* 100baseT4 */
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#define BRGPHY_RES_100HD 0x0300 /* 100baseT half duplex */
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#define BRGPHY_RES_10FD 0x0200 /* 10baseT full duplex */
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#define BRGPHY_RES_10HD 0x0100 /* 10baseT half duplex */
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#define BRGPHY_MII_ISR 0x1A /* Interrupt status */
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#define BRGPHY_ISR_PSERR 0x4000 /* Pair swap error */
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#define BRGPHY_ISR_MDXI_SC 0x2000 /* MDIX Status Change */
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#define BRGPHY_ISR_HCT 0x1000 /* Counter above 32K */
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#define BRGPHY_ISR_LCT 0x0800 /* All counter below 128 */
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#define BRGPHY_ISR_AN_PR 0x0400 /* Autoneg page received */
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#define BRGPHY_ISR_NO_HDCL 0x0200 /* No HCD Link */
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#define BRGPHY_ISR_NO_HDC 0x0100 /* No HCD */
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#define BRGPHY_ISR_USHDC 0x0080 /* Negotiated Unsupported HCD */
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#define BRGPHY_ISR_SCR_S_ERR 0x0040 /* Scrambler sync error */
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#define BRGPHY_ISR_RRS_CHG 0x0020 /* Remote RX status change */
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#define BRGPHY_ISR_LRS_CHG 0x0010 /* Local RX status change */
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#define BRGPHY_ISR_DUP_CHG 0x0008 /* Duplex mode change */
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#define BRGPHY_ISR_LSP_CHG 0x0004 /* Link speed changed */
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#define BRGPHY_ISR_LNK_CHG 0x0002 /* Link status change */
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#define BRGPHY_ISR_CRCERR 0x0001 /* CRC error */
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#define BRGPHY_MII_IMR 0x1B /* Interrupt mask */
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#define BRGPHY_IMR_PSERR 0x4000 /* Pair swap error */
|
||||
#define BRGPHY_IMR_MDXI_SC 0x2000 /* MDIX Status Change */
|
||||
#define BRGPHY_IMR_HCT 0x1000 /* Counter above 32K */
|
||||
#define BRGPHY_IMR_LCT 0x0800 /* All counter below 128 */
|
||||
#define BRGPHY_IMR_AN_PR 0x0400 /* Autoneg page received */
|
||||
#define BRGPHY_IMR_NO_HDCL 0x0200 /* No HCD Link */
|
||||
#define BRGPHY_IMR_NO_HDC 0x0100 /* No HCD */
|
||||
#define BRGPHY_IMR_USHDC 0x0080 /* Negotiated Unsupported HCD */
|
||||
#define BRGPHY_IMR_SCR_S_ERR 0x0040 /* Scrambler sync error */
|
||||
#define BRGPHY_IMR_RRS_CHG 0x0020 /* Remote RX status change */
|
||||
#define BRGPHY_IMR_LRS_CHG 0x0010 /* Local RX status change */
|
||||
#define BRGPHY_IMR_DUP_CHG 0x0008 /* Duplex mode change */
|
||||
#define BRGPHY_IMR_LSP_CHG 0x0004 /* Link speed changed */
|
||||
#define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */
|
||||
#define BRGPHY_IMR_CRCERR 0x0001 /* CRC error */
|
||||
|
||||
/*******************************************************/
|
||||
/* Begin: Shared SerDes PHY register definitions */
|
||||
/*******************************************************/
|
||||
|
||||
/* SerDes autoneg is different from copper */
|
||||
#define BRGPHY_SERDES_ANAR 0x04
|
||||
#define BRGPHY_SERDES_ANAR_FDX 0x0020
|
||||
#define BRGPHY_SERDES_ANAR_HDX 0x0040
|
||||
#define BRGPHY_SERDES_ANAR_NO_PAUSE (0x0 << 7)
|
||||
#define BRGPHY_SERDES_ANAR_SYM_PAUSE (0x1 << 7)
|
||||
#define BRGPHY_SERDES_ANAR_ASYM_PAUSE (0x2 << 7)
|
||||
#define BRGPHY_SERDES_ANAR_BOTH_PAUSE (0x3 << 7)
|
||||
|
||||
#define BRGPHY_SERDES_ANLPAR 0x05
|
||||
#define BRGPHY_SERDES_ANLPAR_FDX 0x0020
|
||||
#define BRGPHY_SERDES_ANLPAR_HDX 0x0040
|
||||
#define BRGPHY_SERDES_ANLPAR_NO_PAUSE (0x0 << 7)
|
||||
#define BRGPHY_SERDES_ANLPAR_SYM_PAUSE (0x1 << 7)
|
||||
#define BRGPHY_SERDES_ANLPAR_ASYM_PAUSE (0x2 << 7)
|
||||
#define BRGPHY_SERDES_ANLPAR_BOTH_PAUSE (0x3 << 7)
|
||||
|
||||
/*******************************************************/
|
||||
/* End: Shared SerDes PHY register definitions */
|
||||
/*******************************************************/
|
||||
|
||||
/*******************************************************/
|
||||
/* Begin: PHY register values for the 5706 PHY */
|
||||
/*******************************************************/
|
||||
|
||||
/*
|
||||
* Shadow register 0x1C, bit 15 is write enable,
|
||||
* bits 14-10 select function (0x00 to 0x1F).
|
||||
*/
|
||||
#define BRGPHY_MII_SHADOW_1C 0x1C
|
||||
#define BRGPHY_SHADOW_1C_WRITE_EN 0x8000
|
||||
#define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00
|
||||
|
||||
/* Shadow 0x1C Mode Control Register (select value 0x1F) */
|
||||
#define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10)
|
||||
/* When set, Regs 0-0x0F are 1000X, else 1000T */
|
||||
#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001
|
||||
|
||||
#define BRGPHY_MII_TEST1 0x1E
|
||||
#define BRGPHY_TEST1_TRIM_EN 0x0010
|
||||
#define BRGPHY_TEST1_CRC_EN 0x8000
|
||||
|
||||
#define BRGPHY_MII_TEST2 0x1F
|
||||
|
||||
/*******************************************************/
|
||||
/* End: PHY register values for the 5706 PHY */
|
||||
/*******************************************************/
|
||||
|
||||
/*******************************************************/
|
||||
/* Begin: PHY register values for the 5708S SerDes PHY */
|
||||
/*******************************************************/
|
||||
|
||||
/* Autoneg Next Page Transmit 1 Regiser */
|
||||
#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1 0x0B
|
||||
#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G 0x0001
|
||||
|
||||
/* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */
|
||||
#define BRGPHY_5708S_BLOCK_ADDR 0x1f
|
||||
#define BRGPHY_5708S_DIG_PG0 0x0000
|
||||
#define BRGPHY_5708S_DIG3_PG2 0x0002
|
||||
#define BRGPHY_5708S_TX_MISC_PG5 0x0005
|
||||
|
||||
/* 5708S SerDes "Digital" Registers (page 0) */
|
||||
#define BRGPHY_5708S_PG0_1000X_CTL1 0x10
|
||||
#define BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN 0x0010
|
||||
#define BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE 0x0001
|
||||
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1 0x14
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_LINK 0x0002
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_FDX 0x0004
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK 0x0018
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10 (0x0 << 3)
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100 (0x1 << 3)
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3)
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3)
|
||||
|
||||
|
||||
#define BRGPHY_5708S_PG0_1000X_CTL2 0x11
|
||||
#define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001
|
||||
|
||||
/* 5708S SerDes "Digital 3" Registers (page 2) */
|
||||
#define BRGPHY_5708S_PG2_DIGCTL_3_0 0x10
|
||||
#define BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE 0x0001
|
||||
|
||||
/* 5708S SerDes "TX Misc" Registers (page 5) */
|
||||
#define BRGPHY_5708S_PG5_2500STATUS1 0x10
|
||||
#define BRGPHY_5708S_PG5_TXACTL1 0x15
|
||||
#define BRGPHY_5708S_PG5_TXACTL3 0x17
|
||||
|
||||
/*******************************************************/
|
||||
/* End: PHY register values for the 5708S SerDes PHY */
|
||||
/*******************************************************/
|
||||
|
||||
#define BRGPHY_INTRS \
|
||||
~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG)
|
||||
|
||||
#endif /* _DEV_BRGPHY_MIIREG_H_ */
|
||||
@ -0,0 +1,12 @@
|
||||
#define MII_OUI_BROADCOM 0x001018
|
||||
#define MII_MODEL_BROADCOM_3C905B 0x0012
|
||||
#define MII_MODEL_BROADCOM_3C905C 0x0017
|
||||
#define MII_MODEL_BROADCOM_BCM5201 0x0021
|
||||
#define MII_MODEL_BROADCOM_BCM5221 0x001e
|
||||
#define MII_MODEL_BROADCOM_BCM4401 0x0036
|
||||
|
||||
#define MII_STR_BROADCOM_3C905B "3C905B"
|
||||
#define MII_STR_BROADCOM_3C905C "3C905C"
|
||||
#define MII_STR_BROADCOM_BCM5201 "BCM5201"
|
||||
#define MII_STR_BROADCOM_BCM5221 "BCM5221"
|
||||
#define MII_STR_BROADCOM_BCM4401 "BCM4401"
|
||||
@ -0,0 +1,220 @@
|
||||
/* $NetBSD: ukphy.c,v 1.2 1999/04/23 04:24:32 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
||||
* NASA Ames Research Center, and by Frank van der Linden.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the NetBSD
|
||||
* Foundation, Inc. and its contributors.
|
||||
* 4. Neither the name of The NetBSD Foundation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1997 Manuel Bouyer. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Manuel Bouyer.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy.c,v 1.20 2007/01/20 00:52:29 marius Exp $");
|
||||
|
||||
/*
|
||||
* driver for generic unknown PHYs
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/socket.h>
|
||||
#include <sys/errno.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/bus.h>
|
||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
|
||||
#include <dev/mii/mii.h>
|
||||
#include <dev/mii/miivar.h>
|
||||
|
||||
#include "miibus_if.h"
|
||||
|
||||
static int ukphy_probe(device_t);
|
||||
static int ukphy_attach(device_t);
|
||||
|
||||
static device_method_t ukphy_methods[] = {
|
||||
/* device interface */
|
||||
DEVMETHOD(device_probe, ukphy_probe),
|
||||
DEVMETHOD(device_attach, ukphy_attach),
|
||||
DEVMETHOD(device_detach, mii_phy_detach),
|
||||
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static devclass_t ukphy_devclass;
|
||||
|
||||
static driver_t ukphy_driver = {
|
||||
"ukphy",
|
||||
ukphy_methods,
|
||||
sizeof(struct mii_softc)
|
||||
};
|
||||
|
||||
DRIVER_MODULE(ukphy, miibus, ukphy_driver, ukphy_devclass, 0, 0);
|
||||
|
||||
static int ukphy_service(struct mii_softc *, struct mii_data *, int);
|
||||
|
||||
static int
|
||||
ukphy_probe(device_t dev)
|
||||
{
|
||||
|
||||
/*
|
||||
* We know something is here, so always match at a low priority.
|
||||
*/
|
||||
device_set_desc(dev, "Generic IEEE 802.3u media interface");
|
||||
return (BUS_PROBE_GENERIC);
|
||||
}
|
||||
|
||||
static int
|
||||
ukphy_attach(device_t dev)
|
||||
{
|
||||
struct mii_softc *sc;
|
||||
struct mii_attach_args *ma;
|
||||
struct mii_data *mii;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
ma = device_get_ivars(dev);
|
||||
sc->mii_dev = device_get_parent(dev);
|
||||
mii = device_get_softc(sc->mii_dev);
|
||||
LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
|
||||
|
||||
if (bootverbose)
|
||||
device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
|
||||
MII_OUI(ma->mii_id1, ma->mii_id2),
|
||||
MII_MODEL(ma->mii_id2), MII_REV(ma->mii_id2));
|
||||
|
||||
sc->mii_inst = mii->mii_instance;
|
||||
sc->mii_phy = ma->mii_phyno;
|
||||
sc->mii_service = ukphy_service;
|
||||
sc->mii_pdata = mii;
|
||||
|
||||
mii->mii_instance++;
|
||||
|
||||
mii_phy_reset(sc);
|
||||
|
||||
sc->mii_capabilities =
|
||||
PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
|
||||
if (sc->mii_capabilities & BMSR_EXTSTAT)
|
||||
sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
|
||||
device_printf(dev, " ");
|
||||
mii_phy_add_media(sc);
|
||||
printf("\n");
|
||||
|
||||
MIIBUS_MEDIAINIT(sc->mii_dev);
|
||||
mii_phy_setmedia(sc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
ukphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
|
||||
{
|
||||
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
||||
int reg;
|
||||
|
||||
switch (cmd) {
|
||||
case MII_POLLSTAT:
|
||||
/*
|
||||
* If we're not polling our PHY instance, just return.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
|
||||
return (0);
|
||||
break;
|
||||
|
||||
case MII_MEDIACHG:
|
||||
/*
|
||||
* If the media indicates a different PHY instance,
|
||||
* isolate ourselves.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
|
||||
reg = PHY_READ(sc, MII_BMCR);
|
||||
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* If the interface is not up, don't do anything.
|
||||
*/
|
||||
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
|
||||
break;
|
||||
|
||||
mii_phy_setmedia(sc);
|
||||
break;
|
||||
|
||||
case MII_TICK:
|
||||
/*
|
||||
* If we're not currently selected, just return.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
|
||||
return (0);
|
||||
if (mii_phy_tick(sc) == EJUSTRETURN)
|
||||
return (0);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Update the media status. */
|
||||
ukphy_status(sc);
|
||||
|
||||
/* Callback if something changed. */
|
||||
mii_phy_update(sc, cmd);
|
||||
return (0);
|
||||
}
|
||||
@ -0,0 +1,129 @@
|
||||
/* $NetBSD: ukphy_subr.c,v 1.2 1998/11/05 04:08:02 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
||||
* NASA Ames Research Center, and by Frank van der Linden.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the NetBSD
|
||||
* Foundation, Inc. and its contributors.
|
||||
* 4. Neither the name of The NetBSD Foundation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy_subr.c,v 1.8.8.1 2006/07/19 04:40:26 yongari Exp $");
|
||||
|
||||
/*
|
||||
* Subroutines shared by the ukphy driver and other PHY drivers.
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/socket.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/bus.h>
|
||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
|
||||
#include <dev/mii/mii.h>
|
||||
#include <dev/mii/miivar.h>
|
||||
|
||||
#include "miibus_if.h"
|
||||
|
||||
/*
|
||||
* Media status subroutine. If a PHY driver does media detection simply
|
||||
* by decoding the NWay autonegotiation, use this routine.
|
||||
*/
|
||||
void
|
||||
ukphy_status(struct mii_softc *phy)
|
||||
{
|
||||
struct mii_data *mii = phy->mii_pdata;
|
||||
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
||||
int bmsr, bmcr, anlpar, gtcr, gtsr;
|
||||
|
||||
mii->mii_media_status = IFM_AVALID;
|
||||
mii->mii_media_active = IFM_ETHER;
|
||||
|
||||
bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR);
|
||||
if (bmsr & BMSR_LINK)
|
||||
mii->mii_media_status |= IFM_ACTIVE;
|
||||
|
||||
bmcr = PHY_READ(phy, MII_BMCR);
|
||||
if (bmcr & BMCR_ISO) {
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
mii->mii_media_status = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
if (bmcr & BMCR_LOOP)
|
||||
mii->mii_media_active |= IFM_LOOP;
|
||||
|
||||
if (bmcr & BMCR_AUTOEN) {
|
||||
/*
|
||||
* NWay autonegotiation takes the highest-order common
|
||||
* bit of the ANAR and ANLPAR (i.e. best media advertised
|
||||
* both by us and our link partner).
|
||||
*/
|
||||
if ((bmsr & BMSR_ACOMP) == 0) {
|
||||
/* Erg, still trying, I guess... */
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
return;
|
||||
}
|
||||
|
||||
anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR);
|
||||
if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 &&
|
||||
(phy->mii_extcapabilities &
|
||||
(EXTSR_1000THDX | EXTSR_1000TFDX)) != 0) {
|
||||
gtcr = PHY_READ(phy, MII_100T2CR);
|
||||
gtsr = PHY_READ(phy, MII_100T2SR);
|
||||
} else
|
||||
gtcr = gtsr = 0;
|
||||
|
||||
if ((gtcr & GTCR_ADV_1000TFDX) && (gtsr & GTSR_LP_1000TFDX))
|
||||
mii->mii_media_active |= IFM_1000_T|IFM_FDX;
|
||||
else if ((gtcr & GTCR_ADV_1000THDX) &&
|
||||
(gtsr & GTSR_LP_1000THDX))
|
||||
mii->mii_media_active |= IFM_1000_T;
|
||||
else if (anlpar & ANLPAR_T4)
|
||||
mii->mii_media_active |= IFM_100_T4;
|
||||
else if (anlpar & ANLPAR_TX_FD)
|
||||
mii->mii_media_active |= IFM_100_TX|IFM_FDX;
|
||||
else if (anlpar & ANLPAR_TX)
|
||||
mii->mii_media_active |= IFM_100_TX;
|
||||
else if (anlpar & ANLPAR_10_FD)
|
||||
mii->mii_media_active |= IFM_10_T|IFM_FDX;
|
||||
else if (anlpar & ANLPAR_10)
|
||||
mii->mii_media_active |= IFM_10_T;
|
||||
else
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
} else
|
||||
mii->mii_media_active = ife->ifm_media;
|
||||
}
|
||||
3
src/add-ons/kernel/drivers/network/nforce/Jamfile
Normal file
3
src/add-ons/kernel/drivers/network/nforce/Jamfile
Normal file
@ -0,0 +1,3 @@
|
||||
SubDir HAIKU_TOP src add-ons kernel drivers network nforce ;
|
||||
|
||||
SubInclude HAIKU_TOP src add-ons kernel drivers network nforce dev ;
|
||||
4
src/add-ons/kernel/drivers/network/nforce/dev/Jamfile
Normal file
4
src/add-ons/kernel/drivers/network/nforce/dev/Jamfile
Normal file
@ -0,0 +1,4 @@
|
||||
SubDir HAIKU_TOP src add-ons kernel drivers network nforce dev ;
|
||||
|
||||
SubInclude HAIKU_TOP src add-ons kernel drivers network nforce dev mii ;
|
||||
SubInclude HAIKU_TOP src add-ons kernel drivers network nforce dev nfe ;
|
||||
15
src/add-ons/kernel/drivers/network/nforce/dev/mii/Jamfile
Normal file
15
src/add-ons/kernel/drivers/network/nforce/dev/mii/Jamfile
Normal file
@ -0,0 +1,15 @@
|
||||
SubDir HAIKU_TOP src add-ons kernel drivers network nforce dev mii ;
|
||||
|
||||
UsePrivateHeaders kernel net ;
|
||||
|
||||
UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ;
|
||||
UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
|
||||
|
||||
SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ;
|
||||
|
||||
KernelStaticLibrary nforce_mii.a
|
||||
:
|
||||
ciphy.c
|
||||
ukphy.c
|
||||
ukphy_subr.c
|
||||
;
|
||||
424
src/add-ons/kernel/drivers/network/nforce/dev/mii/ciphy.c
Normal file
424
src/add-ons/kernel/drivers/network/nforce/dev/mii/ciphy.c
Normal file
@ -0,0 +1,424 @@
|
||||
/*-
|
||||
* Copyright (c) 2004
|
||||
* Bill Paul <wpaul@windriver.com>. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Bill Paul.
|
||||
* 4. Neither the name of the author nor the names of any co-contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD: src/sys/dev/mii/ciphy.c,v 1.9 2007/06/06 06:55:49 yongari Exp $");
|
||||
|
||||
/*
|
||||
* Driver for the Cicada CS8201 10/100/1000 copper PHY.
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/socket.h>
|
||||
#include <sys/bus.h>
|
||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_arp.h>
|
||||
#include <net/if_media.h>
|
||||
|
||||
#include <dev/mii/mii.h>
|
||||
#include <dev/mii/miivar.h>
|
||||
#include "miidevs.h"
|
||||
|
||||
#include <dev/mii/ciphyreg.h>
|
||||
|
||||
#include "miibus_if.h"
|
||||
|
||||
#include <machine/bus.h>
|
||||
/*
|
||||
#include <dev/vge/if_vgereg.h>
|
||||
*/
|
||||
static int ciphy_probe(device_t);
|
||||
static int ciphy_attach(device_t);
|
||||
|
||||
static device_method_t ciphy_methods[] = {
|
||||
/* device interface */
|
||||
DEVMETHOD(device_probe, ciphy_probe),
|
||||
DEVMETHOD(device_attach, ciphy_attach),
|
||||
DEVMETHOD(device_detach, mii_phy_detach),
|
||||
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static devclass_t ciphy_devclass;
|
||||
|
||||
static driver_t ciphy_driver = {
|
||||
"ciphy",
|
||||
ciphy_methods,
|
||||
sizeof(struct mii_softc)
|
||||
};
|
||||
|
||||
DRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0);
|
||||
|
||||
static int ciphy_service(struct mii_softc *, struct mii_data *, int);
|
||||
static void ciphy_status(struct mii_softc *);
|
||||
static void ciphy_reset(struct mii_softc *);
|
||||
static void ciphy_fixup(struct mii_softc *);
|
||||
|
||||
static const struct mii_phydesc ciphys[] = {
|
||||
MII_PHY_DESC(CICADA, CS8201),
|
||||
MII_PHY_DESC(CICADA, CS8201A),
|
||||
MII_PHY_DESC(CICADA, CS8201B),
|
||||
MII_PHY_DESC(VITESSE, VSC8601),
|
||||
MII_PHY_END
|
||||
};
|
||||
|
||||
static int
|
||||
ciphy_probe(device_t dev)
|
||||
{
|
||||
|
||||
return (mii_phy_dev_probe(dev, ciphys, BUS_PROBE_DEFAULT));
|
||||
}
|
||||
|
||||
static int
|
||||
ciphy_attach(device_t dev)
|
||||
{
|
||||
struct mii_softc *sc;
|
||||
struct mii_attach_args *ma;
|
||||
struct mii_data *mii;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
ma = device_get_ivars(dev);
|
||||
sc->mii_dev = device_get_parent(dev);
|
||||
mii = device_get_softc(sc->mii_dev);
|
||||
LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
|
||||
|
||||
sc->mii_inst = mii->mii_instance;
|
||||
sc->mii_phy = ma->mii_phyno;
|
||||
sc->mii_service = ciphy_service;
|
||||
sc->mii_pdata = mii;
|
||||
|
||||
sc->mii_flags |= MIIF_NOISOLATE;
|
||||
mii->mii_instance++;
|
||||
|
||||
ciphy_reset(sc);
|
||||
|
||||
sc->mii_capabilities =
|
||||
PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
|
||||
if (sc->mii_capabilities & BMSR_EXTSTAT)
|
||||
sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
|
||||
device_printf(dev, " ");
|
||||
mii_phy_add_media(sc);
|
||||
printf("\n");
|
||||
|
||||
MIIBUS_MEDIAINIT(sc->mii_dev);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
|
||||
{
|
||||
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
||||
int reg, speed, gig;
|
||||
|
||||
switch (cmd) {
|
||||
case MII_POLLSTAT:
|
||||
/*
|
||||
* If we're not polling our PHY instance, just return.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
|
||||
return (0);
|
||||
break;
|
||||
|
||||
case MII_MEDIACHG:
|
||||
/*
|
||||
* If the media indicates a different PHY instance,
|
||||
* isolate ourselves.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
|
||||
reg = PHY_READ(sc, MII_BMCR);
|
||||
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* If the interface is not up, don't do anything.
|
||||
*/
|
||||
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
|
||||
break;
|
||||
|
||||
ciphy_fixup(sc); /* XXX hardware bug work-around */
|
||||
|
||||
switch (IFM_SUBTYPE(ife->ifm_media)) {
|
||||
case IFM_AUTO:
|
||||
#ifdef foo
|
||||
/*
|
||||
* If we're already in auto mode, just return.
|
||||
*/
|
||||
if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN)
|
||||
return (0);
|
||||
#endif
|
||||
(void) mii_phy_auto(sc);
|
||||
break;
|
||||
case IFM_1000_T:
|
||||
speed = CIPHY_S1000;
|
||||
goto setit;
|
||||
case IFM_100_TX:
|
||||
speed = CIPHY_S100;
|
||||
goto setit;
|
||||
case IFM_10_T:
|
||||
speed = CIPHY_S10;
|
||||
setit:
|
||||
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
|
||||
speed |= CIPHY_BMCR_FDX;
|
||||
gig = CIPHY_1000CTL_AFD;
|
||||
} else {
|
||||
gig = CIPHY_1000CTL_AHD;
|
||||
}
|
||||
|
||||
PHY_WRITE(sc, CIPHY_MII_1000CTL, 0);
|
||||
PHY_WRITE(sc, CIPHY_MII_BMCR, speed);
|
||||
PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE);
|
||||
|
||||
if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
|
||||
break;
|
||||
|
||||
PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
|
||||
PHY_WRITE(sc, CIPHY_MII_BMCR,
|
||||
speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG);
|
||||
|
||||
/*
|
||||
* When setting the link manually, one side must
|
||||
* be the master and the other the slave. However
|
||||
* ifmedia doesn't give us a good way to specify
|
||||
* this, so we fake it by using one of the LINK
|
||||
* flags. If LINK0 is set, we program the PHY to
|
||||
* be a master, otherwise it's a slave.
|
||||
*/
|
||||
if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
|
||||
PHY_WRITE(sc, CIPHY_MII_1000CTL,
|
||||
gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC);
|
||||
} else {
|
||||
PHY_WRITE(sc, CIPHY_MII_1000CTL,
|
||||
gig|CIPHY_1000CTL_MSE);
|
||||
}
|
||||
break;
|
||||
case IFM_NONE:
|
||||
PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
|
||||
break;
|
||||
case IFM_100_T4:
|
||||
default:
|
||||
return (EINVAL);
|
||||
}
|
||||
break;
|
||||
|
||||
case MII_TICK:
|
||||
/*
|
||||
* If we're not currently selected, just return.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
|
||||
return (0);
|
||||
|
||||
/*
|
||||
* Is the interface even up?
|
||||
*/
|
||||
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
|
||||
return (0);
|
||||
|
||||
/*
|
||||
* Only used for autonegotiation.
|
||||
*/
|
||||
if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
|
||||
break;
|
||||
|
||||
/*
|
||||
* Check to see if we have link. If we do, we don't
|
||||
* need to restart the autonegotiation process. Read
|
||||
* the BMSR twice in case it's latched.
|
||||
*/
|
||||
reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
|
||||
if (reg & BMSR_LINK)
|
||||
break;
|
||||
|
||||
/*
|
||||
* Only retry autonegotiation every 5 seconds.
|
||||
*/
|
||||
if (++sc->mii_ticks <= MII_ANEGTICKS)
|
||||
break;
|
||||
|
||||
sc->mii_ticks = 0;
|
||||
mii_phy_auto(sc);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* Update the media status. */
|
||||
ciphy_status(sc);
|
||||
|
||||
/*
|
||||
* Callback if something changed. Note that we need to poke
|
||||
* apply fixups for certain PHY revs.
|
||||
*/
|
||||
if (sc->mii_media_active != mii->mii_media_active ||
|
||||
sc->mii_media_status != mii->mii_media_status ||
|
||||
cmd == MII_MEDIACHG) {
|
||||
ciphy_fixup(sc);
|
||||
}
|
||||
mii_phy_update(sc, cmd);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
ciphy_status(struct mii_softc *sc)
|
||||
{
|
||||
struct mii_data *mii = sc->mii_pdata;
|
||||
int bmsr, bmcr;
|
||||
|
||||
mii->mii_media_status = IFM_AVALID;
|
||||
mii->mii_media_active = IFM_ETHER;
|
||||
|
||||
bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
|
||||
|
||||
if (bmsr & BMSR_LINK)
|
||||
mii->mii_media_status |= IFM_ACTIVE;
|
||||
|
||||
bmcr = PHY_READ(sc, CIPHY_MII_BMCR);
|
||||
|
||||
if (bmcr & CIPHY_BMCR_LOOP)
|
||||
mii->mii_media_active |= IFM_LOOP;
|
||||
|
||||
if (bmcr & CIPHY_BMCR_AUTOEN) {
|
||||
if ((bmsr & CIPHY_BMSR_ACOMP) == 0) {
|
||||
/* Erg, still trying, I guess... */
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR);
|
||||
switch (bmsr & CIPHY_AUXCSR_SPEED) {
|
||||
case CIPHY_SPEED10:
|
||||
mii->mii_media_active |= IFM_10_T;
|
||||
break;
|
||||
case CIPHY_SPEED100:
|
||||
mii->mii_media_active |= IFM_100_TX;
|
||||
break;
|
||||
case CIPHY_SPEED1000:
|
||||
mii->mii_media_active |= IFM_1000_T;
|
||||
break;
|
||||
default:
|
||||
device_printf(sc->mii_dev, "unknown PHY speed %x\n",
|
||||
bmsr & CIPHY_AUXCSR_SPEED);
|
||||
break;
|
||||
}
|
||||
|
||||
if (bmsr & CIPHY_AUXCSR_FDX)
|
||||
mii->mii_media_active |= IFM_FDX;
|
||||
}
|
||||
|
||||
static void
|
||||
ciphy_reset(struct mii_softc *sc)
|
||||
{
|
||||
|
||||
mii_phy_reset(sc);
|
||||
DELAY(1000);
|
||||
}
|
||||
|
||||
#define PHY_SETBIT(x, y, z) \
|
||||
PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
|
||||
#define PHY_CLRBIT(x, y, z) \
|
||||
PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
|
||||
|
||||
static void
|
||||
ciphy_fixup(struct mii_softc *sc)
|
||||
{
|
||||
uint16_t model;
|
||||
uint16_t status, speed;
|
||||
uint16_t val;
|
||||
|
||||
model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2));
|
||||
status = PHY_READ(sc, CIPHY_MII_AUXCSR);
|
||||
speed = status & CIPHY_AUXCSR_SPEED;
|
||||
|
||||
if (strcmp(device_get_name(device_get_parent(sc->mii_dev)),
|
||||
"nfe") == 0) {
|
||||
/* need to set for 2.5V RGMII for NVIDIA adapters */
|
||||
val = PHY_READ(sc, CIPHY_MII_ECTL1);
|
||||
val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL);
|
||||
val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII);
|
||||
PHY_WRITE(sc, CIPHY_MII_ECTL1, val);
|
||||
/* From Linux. */
|
||||
val = PHY_READ(sc, CIPHY_MII_AUXCSR);
|
||||
val |= CIPHY_AUXCSR_MDPPS;
|
||||
PHY_WRITE(sc, CIPHY_MII_AUXCSR, val);
|
||||
val = PHY_READ(sc, CIPHY_MII_10BTCSR);
|
||||
val |= CIPHY_10BTCSR_ECHO;
|
||||
PHY_WRITE(sc, CIPHY_MII_10BTCSR, val);
|
||||
}
|
||||
|
||||
switch (model) {
|
||||
case MII_MODEL_CICADA_CS8201:
|
||||
|
||||
/* Turn off "aux mode" (whatever that means) */
|
||||
PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS);
|
||||
|
||||
/*
|
||||
* Work around speed polling bug in VT3119/VT3216
|
||||
* when using MII in full duplex mode.
|
||||
*/
|
||||
if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
|
||||
(status & CIPHY_AUXCSR_FDX)) {
|
||||
PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
|
||||
} else {
|
||||
PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
|
||||
}
|
||||
|
||||
/* Enable link/activity LED blink. */
|
||||
PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK);
|
||||
|
||||
break;
|
||||
|
||||
case MII_MODEL_CICADA_CS8201A:
|
||||
case MII_MODEL_CICADA_CS8201B:
|
||||
|
||||
/*
|
||||
* Work around speed polling bug in VT3119/VT3216
|
||||
* when using MII in full duplex mode.
|
||||
*/
|
||||
if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
|
||||
(status & CIPHY_AUXCSR_FDX)) {
|
||||
PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
|
||||
} else {
|
||||
PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
|
||||
}
|
||||
|
||||
break;
|
||||
case MII_MODEL_VITESSE_VSC8601:
|
||||
break;
|
||||
default:
|
||||
device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n",
|
||||
model);
|
||||
break;
|
||||
}
|
||||
}
|
||||
361
src/add-ons/kernel/drivers/network/nforce/dev/mii/ciphyreg.h
Normal file
361
src/add-ons/kernel/drivers/network/nforce/dev/mii/ciphyreg.h
Normal file
@ -0,0 +1,361 @@
|
||||
/*-
|
||||
* Copyright (c) 2004
|
||||
* Bill Paul <wpaul@windriver.com>. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Bill Paul.
|
||||
* 4. Neither the name of the author nor the names of any co-contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD: src/sys/dev/mii/ciphyreg.h,v 1.3 2007/06/06 06:55:49 yongari Exp $
|
||||
*/
|
||||
|
||||
#ifndef _DEV_MII_CIPHYREG_H_
|
||||
#define _DEV_MII_CIPHYREG_H_
|
||||
|
||||
/*
|
||||
* Register definitions for the Cicada CS8201 10/100/1000 gigE copper
|
||||
* PHY, embedded within the VIA Networks VT6122 controller.
|
||||
*/
|
||||
|
||||
/* Command register */
|
||||
#define CIPHY_MII_BMCR 0x00
|
||||
#define CIPHY_BMCR_RESET 0x8000
|
||||
#define CIPHY_BMCR_LOOP 0x4000
|
||||
#define CIPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */
|
||||
#define CIPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
|
||||
#define CIPHY_BMCR_PDOWN 0x0800 /* Power down */
|
||||
#define CIPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
|
||||
#define CIPHY_BMCR_FDX 0x0100 /* Duplex mode */
|
||||
#define CIPHY_BMCR_CTEST 0x0080 /* Collision test enable */
|
||||
#define CIPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
|
||||
|
||||
#define CIPHY_S1000 CIPHY_BMCR_SPD1 /* 1000mbps */
|
||||
#define CIPHY_S100 CIPHY_BMCR_SPD0 /* 100mpbs */
|
||||
#define CIPHY_S10 0 /* 10mbps */
|
||||
|
||||
/* Status register */
|
||||
#define CIPHY_MII_BMSR 0x01
|
||||
#define CIPHY_BMSR_100T4 0x8000 /* 100 base T4 capable */
|
||||
#define CIPHY_BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */
|
||||
#define CIPHY_BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */
|
||||
#define CIPHY_BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */
|
||||
#define CIPHY_BMSR_10THDX 0x0800 /* 10 base T half duplex capable */
|
||||
#define CIPHY_BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */
|
||||
#define CIPHY_BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */
|
||||
#define CIPHY_BMSR_EXTSTS 0x0100 /* Extended status present */
|
||||
#define CIPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */
|
||||
#define CIPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */
|
||||
#define CIPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */
|
||||
#define CIPHY_BMSR_ANEG 0x0008 /* Autoneg capable */
|
||||
#define CIPHY_BMSR_LINK 0x0004 /* Link status */
|
||||
#define CIPHY_BMSR_JABBER 0x0002 /* Jabber detected */
|
||||
#define CIPHY_BMSR_EXT 0x0001 /* Extended capability */
|
||||
|
||||
/* PHY ID registers */
|
||||
#define CIPHY_MII_PHYIDR1 0x02
|
||||
#define CIPHY_MII_PHYIDR2 0x03
|
||||
|
||||
/* Autoneg advertisement */
|
||||
#define CIPHY_MII_ANAR 0x04
|
||||
#define CIPHY_ANAR_NP 0x8000 /* Next page */
|
||||
#define CIPHY_ANAR_RF 0x2000 /* Remote fault */
|
||||
#define CIPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */
|
||||
#define CIPHY_ANAR_PC 0x0400 /* Pause capable */
|
||||
#define CIPHY_ANAR_T4 0x0200 /* local device supports 100bT4 */
|
||||
#define CIPHY_ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */
|
||||
#define CIPHY_ANAR_TX 0x0080 /* local device supports 100bTx */
|
||||
#define CIPHY_ANAR_10_FD 0x0040 /* local device supports 10bT FD */
|
||||
#define CIPHY_ANAR_10 0x0020 /* local device supports 10bT */
|
||||
#define CIPHY_ANAR_SEL 0x001F /* selector field, 00001=Ethernet */
|
||||
|
||||
/* Autoneg link partner ability */
|
||||
#define CIPHY_MII_ANLPAR 0x05
|
||||
#define CIPHY_ANLPAR_NP 0x8000 /* Next page */
|
||||
#define CIPHY_ANLPAR_ACK 0x4000 /* link partner acknowledge */
|
||||
#define CIPHY_ANLPAR_RF 0x2000 /* Remote fault */
|
||||
#define CIPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */
|
||||
#define CIPHY_ANLPAR_PC 0x0400 /* Pause capable */
|
||||
#define CIPHY_ANLPAR_T4 0x0200 /* link partner supports 100bT4 */
|
||||
#define CIPHY_ANLPAR_TX_FD 0x0100 /* link partner supports 100bTx FD */
|
||||
#define CIPHY_ANLPAR_TX 0x0080 /* link partner supports 100bTx */
|
||||
#define CIPHY_ANLPAR_10_FD 0x0040 /* link partner supports 10bT FD */
|
||||
#define CIPHY_ANLPAR_10 0x0020 /* link partner supports 10bT */
|
||||
#define CIPHY_ANLPAR_SEL 0x001F /* selector field, 00001=Ethernet */
|
||||
|
||||
#define CIPHY_SEL_TYPE 0x0001 /* ethernet */
|
||||
|
||||
/* Antoneg expansion register */
|
||||
#define CIPHY_MII_ANER 0x06
|
||||
#define CIPHY_ANER_PDF 0x0010 /* Parallel detection fault */
|
||||
#define CIPHY_ANER_LPNP 0x0008 /* Link partner can next page */
|
||||
#define CIPHY_ANER_NP 0x0004 /* Local PHY can next page */
|
||||
#define CIPHY_ANER_RX 0x0002 /* Next page received */
|
||||
#define CIPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */
|
||||
|
||||
/* Autoneg next page transmit regisyer */
|
||||
#define CIPHY_MII_NEXTP 0x07
|
||||
#define CIPHY_NEXTP_MOREP 0x8000 /* More pages to follow */
|
||||
#define CIPHY_NEXTP_MESS 0x2000 /* 1 = message page, 0 = unformatted */
|
||||
#define CIPHY_NEXTP_ACK2 0x1000 /* MAC acknowledge */
|
||||
#define CIPHY_NEXTP_TOGGLE 0x0800 /* Toggle */
|
||||
#define CIPHY_NEXTP_CODE 0x07FF /* Code bits */
|
||||
|
||||
/* Autoneg link partner next page receive register */
|
||||
#define CIPHY_MII_NEXTP_LP 0x08
|
||||
#define CIPHY_NEXTPLP_MOREP 0x8000 /* More pages to follow */
|
||||
#define CIPHY_NEXTPLP_MESS 0x2000 /* 1 = message page, 0 = unformatted */
|
||||
#define CIPHY_NEXTPLP_ACK2 0x1000 /* MAC acknowledge */
|
||||
#define CIPHY_NEXTPLP_TOGGLE 0x0800 /* Toggle */
|
||||
#define CIPHY_NEXTPLP_CODE 0x07FF /* Code bits */
|
||||
|
||||
/* 1000BT control register */
|
||||
#define CIPHY_MII_1000CTL 0x09
|
||||
#define CIPHY_1000CTL_TST 0xE000 /* test modes */
|
||||
#define CIPHY_1000CTL_MSE 0x1000 /* Master/Slave manual enable */
|
||||
#define CIPHY_1000CTL_MSC 0x0800 /* Master/Slave select */
|
||||
#define CIPHY_1000CTL_RD 0x0400 /* Repeater/DTE */
|
||||
#define CIPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */
|
||||
#define CIPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */
|
||||
|
||||
#define CIPHY_TEST_TX_JITTER 0x2000
|
||||
#define CIPHY_TEST_TX_JITTER_MASTER_MODE 0x4000
|
||||
#define CIPHY_TEST_TX_JITTER_SLAVE_MODE 0x6000
|
||||
#define CIPHY_TEST_TX_DISTORTION 0x8000
|
||||
|
||||
/* 1000BT status register */
|
||||
#define CIPHY_MII_1000STS 0x0A
|
||||
#define CIPHY_1000STS_MSF 0x8000 /* Master/slave fault */
|
||||
#define CIPHY_1000STS_MSR 0x4000 /* Master/slave result */
|
||||
#define CIPHY_1000STS_LRS 0x2000 /* Local receiver status */
|
||||
#define CIPHY_1000STS_RRS 0x1000 /* Remote receiver status */
|
||||
#define CIPHY_1000STS_LPFD 0x0800 /* Link partner can FD */
|
||||
#define CIPHY_1000STS_LPHD 0x0400 /* Link partner can HD */
|
||||
#define CIPHY_1000STS_IEC 0x00FF /* Idle error count */
|
||||
|
||||
#define CIPHY_MII_EXTSTS 0x0F /* Extended status */
|
||||
#define CIPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
|
||||
#define CIPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
|
||||
#define CIPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
|
||||
#define CIPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
|
||||
|
||||
/* 1000BT status extension register #1 */
|
||||
#define CIPHY_MII_1000STS1 0x0F
|
||||
#define CIPHY_1000STS1_1000XFDX 0x8000 /* 1000baseX FDX capable */
|
||||
#define CIPHY_1000STS1_1000XHDX 0x4000 /* 1000baseX HDX capable */
|
||||
#define CIPHY_1000STS1_1000TFDX 0x2000 /* 1000baseT FDX capable */
|
||||
#define CIPHY_1000STS1_1000THDX 0x1000 /* 1000baseT HDX capable */
|
||||
|
||||
/* Vendor-specific PHY registers */
|
||||
|
||||
/* 100baseTX status extention register */
|
||||
#define CIPHY_MII_100STS 0x10
|
||||
#define CIPHY_100STS_DESLCK 0x8000 /* descrambler locked */
|
||||
#define CIPHY_100STS_LKCERR 0x4000 /* lock error detected/lock lost */
|
||||
#define CIPHY_100STS_DISC 0x2000 /* disconnect state */
|
||||
#define CIPHY_100STS_LINK 0x1000 /* current link state */
|
||||
#define CIPHY_100STS_RXERR 0x0800 /* receive error detected */
|
||||
#define CIPHY_100STS_TXERR 0x0400 /* transmit error detected */
|
||||
#define CIPHY_100STS_SSDERR 0x0200 /* false carrier error detected */
|
||||
#define CIPHY_100STS_ESDERR 0x0100 /* premature end of stream error */
|
||||
|
||||
/* 1000BT status extention register #2 */
|
||||
#define CIPHY_MII_1000STS2 0x11
|
||||
#define CIPHY_1000STS2_DESLCK 0x8000 /* descrambler locked */
|
||||
#define CIPHY_1000STS2_LKCERR 0x4000 /* lock error detected/lock lost */
|
||||
#define CIPHY_1000STS2_DISC 0x2000 /* disconnect state */
|
||||
#define CIPHY_1000STS2_LINK 0x1000 /* current link state */
|
||||
#define CIPHY_1000STS2_RXERR 0x0800 /* receive error detected */
|
||||
#define CIPHY_1000STS2_TXERR 0x0400 /* transmit error detected */
|
||||
#define CIPHY_1000STS2_SSDERR 0x0200 /* false carrier error detected */
|
||||
#define CIPHY_1000STS2_ESDERR 0x0100 /* premature end of stream error */
|
||||
#define CIPHY_1000STS2_CARREXT 0x0080 /* carrier extention err detected */
|
||||
#define CIPHY_1000STS2_BCM5400 0x0040 /* non-complient BCM5400 detected */
|
||||
|
||||
/* Bypass control register */
|
||||
#define CIPHY_MII_BYPASS 0x12
|
||||
#define CIPHY_BYPASS_TX 0x8000 /* transmit disable */
|
||||
#define CIPHY_BYPASS_4B5B 0x4000 /* bypass the 4B5B encoder */
|
||||
#define CIPHY_BYPASS_SCRAM 0x2000 /* bypass scrambler */
|
||||
#define CIPHY_BYPASS_DSCAM 0x1000 /* bypass descrambler */
|
||||
#define CIPHY_BYPASS_PCSRX 0x0800 /* bypass PCS receive */
|
||||
#define CIPHY_BYPASS_PCSTX 0x0400 /* bypass PCS transmit */
|
||||
#define CIPHY_BYPASS_LFI 0x0200 /* bypass LFI timer */
|
||||
#define CIPHY_BYPASS_TXCLK 0x0100 /* enable transmit clock on LED4 pin */
|
||||
#define CIPHY_BYPASS_BCM5400_F 0x0080 /* force BCM5400 detect */
|
||||
#define CIPHY_BYPASS_BCM5400 0x0040 /* bypass BCM5400 detect */
|
||||
#define CIPHY_BYPASS_PAIRSWAP 0x0020 /* disable automatic pair swap */
|
||||
#define CIPHY_BYPASS_POLARITY 0x0010 /* disable polarity correction */
|
||||
#define CIPHY_BYPASS_PARALLEL 0x0008 /* parallel detect enable */
|
||||
#define CIPHY_BYPASS_PULSE 0x0004 /* disable pulse shaping filter */
|
||||
#define CIPHY_BYPASS_1000BNP 0x0002 /* disable 1000BT next page exchange */
|
||||
|
||||
/* RX error count register */
|
||||
#define CIPHY_MII_RXERR 0x13
|
||||
|
||||
/* False carrier sense count register */
|
||||
#define CIPHY_MII_FCSERR 0x14
|
||||
|
||||
/* Ddisconnect error counter */
|
||||
#define CIPHY_MII_DISCERR 0x15
|
||||
|
||||
/* 10baseT control/status register */
|
||||
#define CIPHY_MII_10BTCSR 0x16
|
||||
#define CIPHY_10BTCSR_DLIT 0x8000 /* Disable data link integrity test */
|
||||
#define CIPHY_10BTCSR_JABBER 0x4000 /* Disable jabber detect */
|
||||
#define CIPHY_10BTCSR_ECHO 0x2000 /* Disable echo mode */
|
||||
#define CIPHY_10BTCSR_SQE 0x1000 /* Disable signal quality error */
|
||||
#define CIPHY_10BTCSR_SQUENCH 0x0C00 /* Squelch control */
|
||||
#define CIPHY_10BTCSR_EOFERR 0x0100 /* End of Frame error */
|
||||
#define CIPHY_10BTCSR_DISC 0x0080 /* Disconnect status */
|
||||
#define CIPHY_10BTCSR_LINK 0x0040 /* current link state */
|
||||
#define CIPHY_10BTCSR_ITRIM 0x0038 /* current reference trim */
|
||||
#define CIPHY_10BTCSR_CSR 0x0006 /* CSR behavior control */
|
||||
|
||||
#define CIPHY_SQUELCH_300MV 0x0000
|
||||
#define CIPHY_SQUELCH_197MV 0x0400
|
||||
#define CIPHY_SQUELCH_450MV 0x0800
|
||||
#define CIPHY_SQUELCH_RSVD 0x0C00
|
||||
|
||||
#define CIPHY_ITRIM_PLUS2 0x0000
|
||||
#define CIPHY_ITRIM_PLUS4 0x0008
|
||||
#define CIPHY_ITRIM_PLUS6 0x0010
|
||||
#define CIPHY_ITRIM_PLUS6_ 0x0018
|
||||
#define CIPHY_ITRIM_MINUS4 0x0020
|
||||
#define CIPHY_ITRIM_MINUS4_ 0x0028
|
||||
#define CIPHY_ITRIM_MINUS2 0x0030
|
||||
#define CIPHY_ITRIM_ZERO 0x0038
|
||||
|
||||
/* Extended PHY control register #1 */
|
||||
#define CIPHY_MII_ECTL1 0x17
|
||||
#define CIPHY_ECTL1_ACTIPHY 0x0020 /* Enable ActiPHY power saving */
|
||||
#define CIPHY_ECTL1_IOVOL 0x0e00 /* MAC interface and I/O voltage select */
|
||||
#define CIPHY_ECTL1_INTSEL 0xf000 /* select MAC interface */
|
||||
|
||||
#define CIPHY_IOVOL_3300MV 0x0000 /* 3.3V for I/O pins */
|
||||
#define CIPHY_IOVOL_2500MV 0x0200 /* 2.5V for I/O pins */
|
||||
|
||||
#define CIPHY_INTSEL_GMII 0x0000 /* GMII/MII */
|
||||
#define CIPHY_INTSEL_RGMII 0x1000
|
||||
#define CIPHY_INTSEL_TBI 0x2000
|
||||
#define CIPHY_INTSEL_RTBI 0x3000
|
||||
|
||||
/* Extended PHY control register #2 */
|
||||
#define CIPHY_MII_ECTL2 0x18
|
||||
#define CIPHY_ECTL2_ERATE 0xE000 /* 10/1000 edge rate control */
|
||||
#define CIPHY_ECTL2_VTRIM 0x1C00 /* voltage reference trim */
|
||||
#define CIPHY_ECTL2_CABLELEN 0x000E /* Cable quality/length */
|
||||
#define CIPHY_ECTL2_ANALOGLOOP 0x0001 /* 1000BT analog loopback */
|
||||
|
||||
#define CIPHY_CABLELEN_0TO10M 0x0000
|
||||
#define CIPHY_CABLELEN_10TO20M 0x0002
|
||||
#define CIPHY_CABLELEN_20TO40M 0x0004
|
||||
#define CIPHY_CABLELEN_40TO80M 0x0006
|
||||
#define CIPHY_CABLELEN_80TO100M 0x0008
|
||||
#define CIPHY_CABLELEN_100TO140M 0x000A
|
||||
#define CIPHY_CABLELEN_140TO180M 0x000C
|
||||
#define CIPHY_CABLELEN_OVER180M 0x000E
|
||||
|
||||
/* Interrupt mask register */
|
||||
#define CIPHY_MII_IMR 0x19
|
||||
#define CIPHY_IMR_PINENABLE 0x8000 /* Interrupt pin enable */
|
||||
#define CIPHY_IMR_SPEED 0x4000 /* speed changed event */
|
||||
#define CIPHY_IMR_LINK 0x2000 /* link change/ActiPHY event */
|
||||
#define CIPHY_IMR_DPX 0x1000 /* duplex change event */
|
||||
#define CIPHY_IMR_ANEGERR 0x0800 /* autoneg error event */
|
||||
#define CIPHY_IMR_ANEGDONE 0x0400 /* autoneg done event */
|
||||
#define CIPHY_IMR_NPRX 0x0200 /* page received event */
|
||||
#define CIPHY_IMR_SYMERR 0x0100 /* symbol error event */
|
||||
#define CIPHY_IMR_LOCKERR 0x0080 /* descrambler lock lost event */
|
||||
#define CIPHY_IMR_XOVER 0x0040 /* MDI crossover change event */
|
||||
#define CIPHY_IMR_POLARITY 0x0020 /* polarity change event */
|
||||
#define CIPHY_IMR_JABBER 0x0010 /* jabber detect event */
|
||||
#define CIPHY_IMR_SSDERR 0x0008 /* false carrier detect event */
|
||||
#define CIPHY_IMR_ESDERR 0x0004 /* parallel detect error event */
|
||||
#define CIPHY_IMR_MASTERSLAVE 0x0002 /* master/slave resolve done event */
|
||||
#define CIPHY_IMR_RXERR 0x0001 /* RX error event */
|
||||
|
||||
/* Interrupt status register */
|
||||
#define CIPHY_MII_ISR 0x1A
|
||||
#define CIPHY_ISR_IPENDING 0x8000 /* Interrupt is pending */
|
||||
#define CIPHY_ISR_SPEED 0x4000 /* speed changed event */
|
||||
#define CIPHY_ISR_LINK 0x2000 /* link change/ActiPHY event */
|
||||
#define CIPHY_ISR_DPX 0x1000 /* duplex change event */
|
||||
#define CIPHY_ISR_ANEGERR 0x0800 /* autoneg error event */
|
||||
#define CIPHY_ISR_ANEGDONE 0x0400 /* autoneg done event */
|
||||
#define CIPHY_ISR_NPRX 0x0200 /* page received event */
|
||||
#define CIPHY_ISR_SYMERR 0x0100 /* symbol error event */
|
||||
#define CIPHY_ISR_LOCKERR 0x0080 /* descrambler lock lost event */
|
||||
#define CIPHY_ISR_XOVER 0x0040 /* MDI crossover change event */
|
||||
#define CIPHY_ISR_POLARITY 0x0020 /* polarity change event */
|
||||
#define CIPHY_ISR_JABBER 0x0010 /* jabber detect event */
|
||||
#define CIPHY_ISR_SSDERR 0x0008 /* false carrier detect event */
|
||||
#define CIPHY_ISR_ESDERR 0x0004 /* parallel detect error event */
|
||||
#define CIPHY_ISR_MASTERSLAVE 0x0002 /* master/slave resolve done event */
|
||||
#define CIPHY_ISR_RXERR 0x0001 /* RX error event */
|
||||
|
||||
/* LED control register */
|
||||
#define CIPHY_MII_LED 0x1B
|
||||
#define CIPHY_LED_LINK10FORCE 0x8000 /* Force on link10 LED */
|
||||
#define CIPHY_LED_LINK10DIS 0x4000 /* Disable link10 LED */
|
||||
#define CIPHY_LED_LINK100FORCE 0x2000 /* Force on link10 LED */
|
||||
#define CIPHY_LED_LINK100DIS 0x1000 /* Disable link100 LED */
|
||||
#define CIPHY_LED_LINK1000FORCE 0x0800 /* Force on link1000 LED */
|
||||
#define CIPHY_LED_LINK1000DIS 0x0400 /* Disable link1000 LED */
|
||||
#define CIPHY_LED_FDXFORCE 0x0200 /* Force on duplex LED */
|
||||
#define CIPHY_LED_FDXDIS 0x0100 /* Disable duplex LED */
|
||||
#define CIPHY_LED_ACTFORCE 0x0080 /* Force on activity LED */
|
||||
#define CIPHY_LED_ACTDIS 0x0040 /* Disable activity LED */
|
||||
#define CIPHY_LED_PULSE 0x0008 /* LED pulse enable */
|
||||
#define CIPHY_LED_LINKACTBLINK 0x0004 /* enable link/activity LED blink */
|
||||
#define CIPHY_LED_BLINKRATE 0x0002 /* blink rate 0=10hz, 1=5hz */
|
||||
|
||||
/* Auxilliary control and status register */
|
||||
#define CIPHY_MII_AUXCSR 0x1C
|
||||
#define CIPHY_AUXCSR_ANEGDONE 0x8000 /* Autoneg complete */
|
||||
#define CIPHY_AUXCSR_ANEGOFF 0x4000 /* Autoneg disabled */
|
||||
#define CIPHY_AUXCSR_XOVER 0x2000 /* MDI/MDI-X crossover indication */
|
||||
#define CIPHY_AUXCSR_PAIRSWAP 0x1000 /* pair swap indication */
|
||||
#define CIPHY_AUXCSR_APOLARITY 0x0800 /* polarity inversion pair A */
|
||||
#define CIPHY_AUXCSR_BPOLARITY 0x0400 /* polarity inversion pair B */
|
||||
#define CIPHY_AUXCSR_CPOLARITY 0x0200 /* polarity inversion pair C */
|
||||
#define CIPHY_AUXCSR_DPOLARITY 0x0100 /* polarity inversion pair D */
|
||||
#define CIPHY_AUXCSR_FDX 0x0020 /* duplex 1=full, 0=half */
|
||||
#define CIPHY_AUXCSR_SPEED 0x0018 /* speed */
|
||||
#define CIPHY_AUXCSR_MDPPS 0x0004 /* No idea, not documented */
|
||||
#define CIPHY_AUXCSR_STICKYREST 0x0002 /* reset clears sticky bits */
|
||||
|
||||
#define CIPHY_SPEED10 0x0000
|
||||
#define CIPHY_SPEED100 0x0008
|
||||
#define CIPHY_SPEED1000 0x0010
|
||||
|
||||
/* Delay skew status register */
|
||||
#define CIPHY_MII_DSKEW 0x1D
|
||||
#define CIPHY_DSKEW_PAIRA 0x7000 /* Pair A skew in symbol times */
|
||||
#define CIPHY_DSKEW_PAIRB 0x0700 /* Pair B skew in symbol times */
|
||||
#define CIPHY_DSKEW_PAIRC 0x0070 /* Pair C skew in symbol times */
|
||||
#define CIPHY_DSKEW_PAIRD 0x0007 /* Pair D skew in symbol times */
|
||||
|
||||
#endif /* _DEV_CIPHY_MIIREG_H_ */
|
||||
21
src/add-ons/kernel/drivers/network/nforce/dev/mii/miidevs.h
Normal file
21
src/add-ons/kernel/drivers/network/nforce/dev/mii/miidevs.h
Normal file
@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright 2007, Axel Dörfler, axeld@pinc-software.de. All Rights Reserved.
|
||||
* Distributed under the terms of the MIT License.
|
||||
*/
|
||||
#ifndef _FBSD_MII_DEVS_H
|
||||
#define _FBSD_MII_DEVS_H
|
||||
|
||||
#define MII_OUI_CICADA 0x0003f1
|
||||
#define MII_OUI_VITESSE 0x0001c1
|
||||
|
||||
#define MII_MODEL_CICADA_CS8201 0x0001
|
||||
#define MII_MODEL_CICADA_CS8201A 0x0020
|
||||
#define MII_MODEL_CICADA_CS8201B 0x0021
|
||||
#define MII_MODEL_VITESSE_VSC8601 0x0002
|
||||
|
||||
#define MII_STR_CICADA_CS8201 "Cicada CS8201 10/100/1000TX PHY"
|
||||
#define MII_STR_CICADA_CS8201A MII_STR_CICADA_CS8201
|
||||
#define MII_STR_CICADA_CS8201B MII_STR_CICADA_CS8201
|
||||
#define MII_STR_VITESSE_VSC8601 "Vitesse VSC8601 10/100/1000TX PHY"
|
||||
|
||||
#endif /* _FBSD_MII_DEVS_H */
|
||||
220
src/add-ons/kernel/drivers/network/nforce/dev/mii/ukphy.c
Normal file
220
src/add-ons/kernel/drivers/network/nforce/dev/mii/ukphy.c
Normal file
@ -0,0 +1,220 @@
|
||||
/* $NetBSD: ukphy.c,v 1.2 1999/04/23 04:24:32 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
||||
* NASA Ames Research Center, and by Frank van der Linden.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the NetBSD
|
||||
* Foundation, Inc. and its contributors.
|
||||
* 4. Neither the name of The NetBSD Foundation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1997 Manuel Bouyer. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Manuel Bouyer.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy.c,v 1.20 2007/01/20 00:52:29 marius Exp $");
|
||||
|
||||
/*
|
||||
* driver for generic unknown PHYs
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/socket.h>
|
||||
#include <sys/errno.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/bus.h>
|
||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
|
||||
#include <dev/mii/mii.h>
|
||||
#include <dev/mii/miivar.h>
|
||||
|
||||
#include "miibus_if.h"
|
||||
|
||||
static int ukphy_probe(device_t);
|
||||
static int ukphy_attach(device_t);
|
||||
|
||||
static device_method_t ukphy_methods[] = {
|
||||
/* device interface */
|
||||
DEVMETHOD(device_probe, ukphy_probe),
|
||||
DEVMETHOD(device_attach, ukphy_attach),
|
||||
DEVMETHOD(device_detach, mii_phy_detach),
|
||||
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static devclass_t ukphy_devclass;
|
||||
|
||||
static driver_t ukphy_driver = {
|
||||
"ukphy",
|
||||
ukphy_methods,
|
||||
sizeof(struct mii_softc)
|
||||
};
|
||||
|
||||
DRIVER_MODULE(ukphy, miibus, ukphy_driver, ukphy_devclass, 0, 0);
|
||||
|
||||
static int ukphy_service(struct mii_softc *, struct mii_data *, int);
|
||||
|
||||
static int
|
||||
ukphy_probe(device_t dev)
|
||||
{
|
||||
|
||||
/*
|
||||
* We know something is here, so always match at a low priority.
|
||||
*/
|
||||
device_set_desc(dev, "Generic IEEE 802.3u media interface");
|
||||
return (BUS_PROBE_GENERIC);
|
||||
}
|
||||
|
||||
static int
|
||||
ukphy_attach(device_t dev)
|
||||
{
|
||||
struct mii_softc *sc;
|
||||
struct mii_attach_args *ma;
|
||||
struct mii_data *mii;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
ma = device_get_ivars(dev);
|
||||
sc->mii_dev = device_get_parent(dev);
|
||||
mii = device_get_softc(sc->mii_dev);
|
||||
LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
|
||||
|
||||
if (bootverbose)
|
||||
device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
|
||||
MII_OUI(ma->mii_id1, ma->mii_id2),
|
||||
MII_MODEL(ma->mii_id2), MII_REV(ma->mii_id2));
|
||||
|
||||
sc->mii_inst = mii->mii_instance;
|
||||
sc->mii_phy = ma->mii_phyno;
|
||||
sc->mii_service = ukphy_service;
|
||||
sc->mii_pdata = mii;
|
||||
|
||||
mii->mii_instance++;
|
||||
|
||||
mii_phy_reset(sc);
|
||||
|
||||
sc->mii_capabilities =
|
||||
PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
|
||||
if (sc->mii_capabilities & BMSR_EXTSTAT)
|
||||
sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
|
||||
device_printf(dev, " ");
|
||||
mii_phy_add_media(sc);
|
||||
printf("\n");
|
||||
|
||||
MIIBUS_MEDIAINIT(sc->mii_dev);
|
||||
mii_phy_setmedia(sc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
ukphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
|
||||
{
|
||||
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
||||
int reg;
|
||||
|
||||
switch (cmd) {
|
||||
case MII_POLLSTAT:
|
||||
/*
|
||||
* If we're not polling our PHY instance, just return.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
|
||||
return (0);
|
||||
break;
|
||||
|
||||
case MII_MEDIACHG:
|
||||
/*
|
||||
* If the media indicates a different PHY instance,
|
||||
* isolate ourselves.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
|
||||
reg = PHY_READ(sc, MII_BMCR);
|
||||
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* If the interface is not up, don't do anything.
|
||||
*/
|
||||
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
|
||||
break;
|
||||
|
||||
mii_phy_setmedia(sc);
|
||||
break;
|
||||
|
||||
case MII_TICK:
|
||||
/*
|
||||
* If we're not currently selected, just return.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
|
||||
return (0);
|
||||
if (mii_phy_tick(sc) == EJUSTRETURN)
|
||||
return (0);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Update the media status. */
|
||||
ukphy_status(sc);
|
||||
|
||||
/* Callback if something changed. */
|
||||
mii_phy_update(sc, cmd);
|
||||
return (0);
|
||||
}
|
||||
129
src/add-ons/kernel/drivers/network/nforce/dev/mii/ukphy_subr.c
Normal file
129
src/add-ons/kernel/drivers/network/nforce/dev/mii/ukphy_subr.c
Normal file
@ -0,0 +1,129 @@
|
||||
/* $NetBSD: ukphy_subr.c,v 1.2 1998/11/05 04:08:02 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
|
||||
* NASA Ames Research Center, and by Frank van der Linden.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the NetBSD
|
||||
* Foundation, Inc. and its contributors.
|
||||
* 4. Neither the name of The NetBSD Foundation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy_subr.c,v 1.9 2006/05/19 03:51:42 yongari Exp $");
|
||||
|
||||
/*
|
||||
* Subroutines shared by the ukphy driver and other PHY drivers.
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/socket.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/bus.h>
|
||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
|
||||
#include <dev/mii/mii.h>
|
||||
#include <dev/mii/miivar.h>
|
||||
|
||||
#include "miibus_if.h"
|
||||
|
||||
/*
|
||||
* Media status subroutine. If a PHY driver does media detection simply
|
||||
* by decoding the NWay autonegotiation, use this routine.
|
||||
*/
|
||||
void
|
||||
ukphy_status(struct mii_softc *phy)
|
||||
{
|
||||
struct mii_data *mii = phy->mii_pdata;
|
||||
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
||||
int bmsr, bmcr, anlpar, gtcr, gtsr;
|
||||
|
||||
mii->mii_media_status = IFM_AVALID;
|
||||
mii->mii_media_active = IFM_ETHER;
|
||||
|
||||
bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR);
|
||||
if (bmsr & BMSR_LINK)
|
||||
mii->mii_media_status |= IFM_ACTIVE;
|
||||
|
||||
bmcr = PHY_READ(phy, MII_BMCR);
|
||||
if (bmcr & BMCR_ISO) {
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
mii->mii_media_status = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
if (bmcr & BMCR_LOOP)
|
||||
mii->mii_media_active |= IFM_LOOP;
|
||||
|
||||
if (bmcr & BMCR_AUTOEN) {
|
||||
/*
|
||||
* NWay autonegotiation takes the highest-order common
|
||||
* bit of the ANAR and ANLPAR (i.e. best media advertised
|
||||
* both by us and our link partner).
|
||||
*/
|
||||
if ((bmsr & BMSR_ACOMP) == 0) {
|
||||
/* Erg, still trying, I guess... */
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
return;
|
||||
}
|
||||
|
||||
anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR);
|
||||
if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 &&
|
||||
(phy->mii_extcapabilities &
|
||||
(EXTSR_1000THDX | EXTSR_1000TFDX)) != 0) {
|
||||
gtcr = PHY_READ(phy, MII_100T2CR);
|
||||
gtsr = PHY_READ(phy, MII_100T2SR);
|
||||
} else
|
||||
gtcr = gtsr = 0;
|
||||
|
||||
if ((gtcr & GTCR_ADV_1000TFDX) && (gtsr & GTSR_LP_1000TFDX))
|
||||
mii->mii_media_active |= IFM_1000_T|IFM_FDX;
|
||||
else if ((gtcr & GTCR_ADV_1000THDX) &&
|
||||
(gtsr & GTSR_LP_1000THDX))
|
||||
mii->mii_media_active |= IFM_1000_T;
|
||||
else if (anlpar & ANLPAR_T4)
|
||||
mii->mii_media_active |= IFM_100_T4;
|
||||
else if (anlpar & ANLPAR_TX_FD)
|
||||
mii->mii_media_active |= IFM_100_TX|IFM_FDX;
|
||||
else if (anlpar & ANLPAR_TX)
|
||||
mii->mii_media_active |= IFM_100_TX;
|
||||
else if (anlpar & ANLPAR_10_FD)
|
||||
mii->mii_media_active |= IFM_10_T|IFM_FDX;
|
||||
else if (anlpar & ANLPAR_10)
|
||||
mii->mii_media_active |= IFM_10_T;
|
||||
else
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
} else
|
||||
mii->mii_media_active = ife->ifm_media;
|
||||
}
|
||||
15
src/add-ons/kernel/drivers/network/nforce/dev/nfe/Jamfile
Normal file
15
src/add-ons/kernel/drivers/network/nforce/dev/nfe/Jamfile
Normal file
@ -0,0 +1,15 @@
|
||||
SubDir HAIKU_TOP src add-ons kernel drivers network nforce dev nfe ;
|
||||
|
||||
UsePrivateHeaders kernel net ;
|
||||
|
||||
UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ;
|
||||
UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
|
||||
|
||||
SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ;
|
||||
|
||||
KernelAddon nforce :
|
||||
if_nfe.c
|
||||
|
||||
glue.c
|
||||
: libfreebsd_network.a nforce_mii.a
|
||||
;
|
||||
31
src/add-ons/kernel/drivers/network/nforce/dev/nfe/glue.c
Normal file
31
src/add-ons/kernel/drivers/network/nforce/dev/nfe/glue.c
Normal file
@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright 2007, Axel Dörfler, axeld@pinc-software.de. All Rights Reserved.
|
||||
* Distributed under the terms of the MIT License.
|
||||
*/
|
||||
|
||||
|
||||
#include <sys/bus.h>
|
||||
|
||||
|
||||
HAIKU_FBSD_DRIVER_GLUE(nforce, nfe, pci)
|
||||
|
||||
HAIKU_DRIVER_REQUIREMENTS(FBSD_TASKQUEUES | FBSD_FAST_TASKQUEUE);
|
||||
NO_HAIKU_CHECK_DISABLE_INTERRUPTS();
|
||||
NO_HAIKU_REENABLE_INTERRUPTS();
|
||||
|
||||
extern driver_t *DRIVER_MODULE_NAME(ciphy, miibus);
|
||||
extern driver_t *DRIVER_MODULE_NAME(ukphy, miibus);
|
||||
|
||||
|
||||
driver_t *
|
||||
__haiku_select_miibus_driver(device_t dev)
|
||||
{
|
||||
driver_t *drivers[] = {
|
||||
DRIVER_MODULE_NAME(ciphy, miibus),
|
||||
DRIVER_MODULE_NAME(ukphy, miibus),
|
||||
NULL
|
||||
};
|
||||
|
||||
return __haiku_probe_miibus(dev, drivers);
|
||||
}
|
||||
|
||||
3218
src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfe.c
Normal file
3218
src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfe.c
Normal file
File diff suppressed because it is too large
Load Diff
322
src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfereg.h
Normal file
322
src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfereg.h
Normal file
@ -0,0 +1,322 @@
|
||||
/* $OpenBSD: if_nfereg.h,v 1.16 2006/02/22 19:23:44 damien Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2005 Jonathan Gray <jsg@openbsd.org>
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $FreeBSD: src/sys/dev/nfe/if_nfereg.h,v 1.10 2007/06/12 10:51:47 yongari Exp $
|
||||
*/
|
||||
|
||||
#define NFE_RX_RING_COUNT 256
|
||||
#define NFE_JUMBO_RX_RING_COUNT NFE_RX_RING_COUNT
|
||||
#define NFE_TX_RING_COUNT 256
|
||||
|
||||
#define NFE_PROC_DEFAULT ((NFE_RX_RING_COUNT * 3) / 4)
|
||||
#define NFE_PROC_MIN 50
|
||||
#define NFE_PROC_MAX (NFE_RX_RING_COUNT - 1)
|
||||
|
||||
#define NFE_INC(x, y) (x) = ((x) + 1) % y
|
||||
|
||||
/* RX/TX MAC addr + type + VLAN + align + slack */
|
||||
#define NFE_RX_HEADERS 64
|
||||
|
||||
/* Maximum MTU size. */
|
||||
#define NV_PKTLIMIT_1 ETH_DATA_LEN /* Hard limit not known. */
|
||||
#define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia:9202 */
|
||||
|
||||
#define NFE_JUMBO_FRAMELEN NV_PKTLIMIT_2
|
||||
#define NFE_JUMBO_MTU \
|
||||
(NFE_JUMBO_FRAMELEN - NFE_RX_HEADERS)
|
||||
#define NFE_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
|
||||
#define NFE_JSLOTS ((NFE_JUMBO_RX_RING_COUNT * 3) / 2)
|
||||
|
||||
#define NFE_JRAWLEN (NFE_JUMBO_FRAMELEN + ETHER_ALIGN)
|
||||
#define NFE_JLEN \
|
||||
(NFE_JRAWLEN + (sizeof(uint64_t) - (NFE_JRAWLEN % sizeof(uint64_t))))
|
||||
#define NFE_JPAGESZ PAGE_SIZE
|
||||
#define NFE_RESID \
|
||||
(NFE_JPAGESZ - (NFE_JLEN * NFE_JSLOTS) % NFE_JPAGESZ)
|
||||
#define NFE_JMEM ((NFE_JLEN * NFE_JSLOTS) + NFE_RESID)
|
||||
|
||||
#define NFE_MAX_SCATTER 32
|
||||
#define NFE_TSO_MAXSGSIZE 4096
|
||||
#define NFE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header))
|
||||
|
||||
#define NFE_IRQ_STATUS 0x000
|
||||
#define NFE_IRQ_MASK 0x004
|
||||
#define NFE_SETUP_R6 0x008
|
||||
#define NFE_IMTIMER 0x00c
|
||||
#define NFE_MSI_MAP0 0x020
|
||||
#define NFE_MSI_MAP1 0x024
|
||||
#define NFE_MSI_IRQ_MASK 0x030
|
||||
#define NFE_MAC_RESET 0x03c
|
||||
#define NFE_MISC1 0x080
|
||||
#define NFE_TX_CTL 0x084
|
||||
#define NFE_TX_STATUS 0x088
|
||||
#define NFE_RXFILTER 0x08c
|
||||
#define NFE_RXBUFSZ 0x090
|
||||
#define NFE_RX_CTL 0x094
|
||||
#define NFE_RX_STATUS 0x098
|
||||
#define NFE_RNDSEED 0x09c
|
||||
#define NFE_SETUP_R1 0x0a0
|
||||
#define NFE_SETUP_R2 0x0a4
|
||||
#define NFE_MACADDR_HI 0x0a8
|
||||
#define NFE_MACADDR_LO 0x0ac
|
||||
#define NFE_MULTIADDR_HI 0x0b0
|
||||
#define NFE_MULTIADDR_LO 0x0b4
|
||||
#define NFE_MULTIMASK_HI 0x0b8
|
||||
#define NFE_MULTIMASK_LO 0x0bc
|
||||
#define NFE_PHY_IFACE 0x0c0
|
||||
#define NFE_TX_RING_ADDR_LO 0x100
|
||||
#define NFE_RX_RING_ADDR_LO 0x104
|
||||
#define NFE_RING_SIZE 0x108
|
||||
#define NFE_TX_UNK 0x10c
|
||||
#define NFE_LINKSPEED 0x110
|
||||
#define NFE_SETUP_R5 0x130
|
||||
#define NFE_SETUP_R3 0x13C
|
||||
#define NFE_SETUP_R7 0x140
|
||||
#define NFE_RXTX_CTL 0x144
|
||||
#define NFE_TX_RING_ADDR_HI 0x148
|
||||
#define NFE_RX_RING_ADDR_HI 0x14c
|
||||
#define NFE_TX_PAUSE_FRAME 0x170
|
||||
#define NFE_PHY_STATUS 0x180
|
||||
#define NFE_SETUP_R4 0x184
|
||||
#define NFE_STATUS 0x188
|
||||
#define NFE_PHY_SPEED 0x18c
|
||||
#define NFE_PHY_CTL 0x190
|
||||
#define NFE_PHY_DATA 0x194
|
||||
#define NFE_WOL_CTL 0x200
|
||||
#define NFE_PATTERN_CRC 0x204
|
||||
#define NFE_PATTERN_MASK 0x208
|
||||
#define NFE_PWR_CAP 0x268
|
||||
#define NFE_PWR_STATE 0x26c
|
||||
#define NFE_VTAG_CTL 0x300
|
||||
#define NFE_MSIX_MAP0 0x3e0
|
||||
#define NFE_MSIX_MAP1 0x3e4
|
||||
#define NFE_MSIX_IRQ_STATUS 0x3f0
|
||||
#define NFE_PWR2_CTL 0x600
|
||||
|
||||
#define NFE_MAC_RESET_MAGIC 0x00f3
|
||||
|
||||
#define NFE_MAC_ADDR_INORDER 0x8000
|
||||
|
||||
#define NFE_PHY_ERROR 0x00001
|
||||
#define NFE_PHY_WRITE 0x00400
|
||||
#define NFE_PHY_BUSY 0x08000
|
||||
#define NFE_PHYADD_SHIFT 5
|
||||
|
||||
#define NFE_STATUS_MAGIC 0x140000
|
||||
|
||||
#define NFE_R1_MAGIC_1000 0x14050f
|
||||
#define NFE_R1_MAGIC_10_100 0x16070f
|
||||
#define NFE_R1_MAGIC_DEFAULT 0x15050f
|
||||
#define NFE_R2_MAGIC 0x16
|
||||
#define NFE_R4_MAGIC 0x08
|
||||
#define NFE_R6_MAGIC 0x03
|
||||
#define NFE_WOL_MAGIC 0x1111
|
||||
#define NFE_RX_START 0x01
|
||||
#define NFE_TX_START 0x01
|
||||
|
||||
#define NFE_IRQ_RXERR 0x0001
|
||||
#define NFE_IRQ_RX 0x0002
|
||||
#define NFE_IRQ_RX_NOBUF 0x0004
|
||||
#define NFE_IRQ_TXERR 0x0008
|
||||
#define NFE_IRQ_TX_DONE 0x0010
|
||||
#define NFE_IRQ_TIMER 0x0020
|
||||
#define NFE_IRQ_LINK 0x0040
|
||||
#define NFE_IRQ_TXERR2 0x0080
|
||||
#define NFE_IRQ_TX1 0x0100
|
||||
|
||||
#define NFE_IRQ_WANTED \
|
||||
(NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX | \
|
||||
NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE | \
|
||||
NFE_IRQ_LINK)
|
||||
|
||||
#define NFE_RXTX_KICKTX 0x0001
|
||||
#define NFE_RXTX_BIT1 0x0002
|
||||
#define NFE_RXTX_BIT2 0x0004
|
||||
#define NFE_RXTX_RESET 0x0010
|
||||
#define NFE_RXTX_VTAG_STRIP 0x0040
|
||||
#define NFE_RXTX_VTAG_INSERT 0x0080
|
||||
#define NFE_RXTX_RXCSUM 0x0400
|
||||
#define NFE_RXTX_V2MAGIC 0x2100
|
||||
#define NFE_RXTX_V3MAGIC 0x2200
|
||||
#define NFE_RXFILTER_MAGIC 0x007f0000
|
||||
#define NFE_PFF_RX_PAUSE (1 << 3)
|
||||
#define NFE_PFF_LOOPBACK (1 << 4)
|
||||
#define NFE_PFF_U2M (1 << 5)
|
||||
#define NFE_PFF_PROMISC (1 << 7)
|
||||
#define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
|
||||
|
||||
/* default interrupt moderation timer of 128us */
|
||||
#define NFE_IM_DEFAULT ((128 * 100) / 1024)
|
||||
|
||||
#define NFE_VTAG_ENABLE (1 << 13)
|
||||
|
||||
#define NFE_PWR_VALID (1 << 8)
|
||||
#define NFE_PWR_WAKEUP (1 << 15)
|
||||
|
||||
#define NFE_PWR2_WAKEUP_MASK 0x0f11
|
||||
#define NFE_PWR2_REVA3 (1 << 0)
|
||||
|
||||
#define NFE_MEDIA_SET 0x10000
|
||||
#define NFE_MEDIA_1000T 0x00032
|
||||
#define NFE_MEDIA_100TX 0x00064
|
||||
#define NFE_MEDIA_10T 0x003e8
|
||||
|
||||
#define NFE_PHY_100TX (1 << 0)
|
||||
#define NFE_PHY_1000T (1 << 1)
|
||||
#define NFE_PHY_HDX (1 << 8)
|
||||
|
||||
#define NFE_MISC1_MAGIC 0x003b0f3c
|
||||
#define NFE_MISC1_TX_PAUSE (1 << 0)
|
||||
#define NFE_MISC1_HDX (1 << 1)
|
||||
|
||||
#define NFE_TX_PAUSE_FRAME_DISABLE 0x1ff0080
|
||||
#define NFE_TX_PAUSE_FRAME_ENABLE 0x0c00030
|
||||
|
||||
#define NFE_SEED_MASK 0x0003ff00
|
||||
#define NFE_SEED_10T 0x00007f00
|
||||
#define NFE_SEED_100TX 0x00002d00
|
||||
#define NFE_SEED_1000T 0x00007400
|
||||
|
||||
#define NFE_MSI_MESSAGES 8
|
||||
#define NFE_MSI_VECTOR_0_ENABLED 0x01
|
||||
|
||||
/*
|
||||
* It seems that nForce supports only the lower 40 bits of a DMA address.
|
||||
*/
|
||||
#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF)
|
||||
#define NFE_DMA_MAXADDR BUS_SPACE_MAXADDR
|
||||
#else
|
||||
#define NFE_DMA_MAXADDR 0xFFFFFFFFFF
|
||||
#endif
|
||||
|
||||
#define NFE_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff)
|
||||
#define NFE_ADDR_HI(x) ((u_int64_t) (x) >> 32)
|
||||
|
||||
/* Rx/Tx descriptor */
|
||||
struct nfe_desc32 {
|
||||
uint32_t physaddr;
|
||||
uint16_t length;
|
||||
uint16_t flags;
|
||||
#define NFE_RX_FIXME_V1 0x6004
|
||||
#define NFE_RX_VALID_V1 (1 << 0)
|
||||
#define NFE_TX_ERROR_V1 0x7808
|
||||
#define NFE_TX_LASTFRAG_V1 (1 << 0)
|
||||
#define NFE_RX_ERROR1_V1 (1<<7)
|
||||
#define NFE_RX_ERROR2_V1 (1<<8)
|
||||
#define NFE_RX_ERROR3_V1 (1<<9)
|
||||
#define NFE_RX_ERROR4_V1 (1<<10)
|
||||
} __packed;
|
||||
|
||||
#define NFE_V1_TXERR "\020" \
|
||||
"\14TXERROR\13UNDERFLOW\12LATECOLLISION\11LOSTCARRIER\10DEFERRED" \
|
||||
"\08FORCEDINT\03RETRY\00LASTPACKET"
|
||||
|
||||
/* V2 Rx/Tx descriptor */
|
||||
struct nfe_desc64 {
|
||||
uint32_t physaddr[2];
|
||||
uint32_t vtag;
|
||||
#define NFE_RX_VTAG (1 << 16)
|
||||
#define NFE_TX_VTAG (1 << 18)
|
||||
uint16_t length;
|
||||
uint16_t flags;
|
||||
#define NFE_RX_FIXME_V2 0x4300
|
||||
#define NFE_RX_VALID_V2 (1 << 13)
|
||||
#define NFE_TX_ERROR_V2 0x5c04
|
||||
#define NFE_TX_LASTFRAG_V2 (1 << 13)
|
||||
#define NFE_RX_ERROR1_V2 (1<<2)
|
||||
#define NFE_RX_ERROR2_V2 (1<<3)
|
||||
#define NFE_RX_ERROR3_V2 (1<<4)
|
||||
#define NFE_RX_ERROR4_V2 (1<<5)
|
||||
} __packed;
|
||||
|
||||
#define NFE_V2_TXERR "\020" \
|
||||
"\14FORCEDINT\13LASTPACKET\12UNDERFLOW\10LOSTCARRIER\09DEFERRED\02RETRY"
|
||||
|
||||
#define NFE_RING_ALIGN (sizeof(struct nfe_desc64))
|
||||
|
||||
/* flags common to V1/V2 descriptors */
|
||||
#define NFE_RX_UDP_CSUMOK (1 << 10)
|
||||
#define NFE_RX_TCP_CSUMOK (1 << 11)
|
||||
#define NFE_RX_IP_CSUMOK (1 << 12)
|
||||
#define NFE_RX_ERROR (1 << 14)
|
||||
#define NFE_RX_READY (1 << 15)
|
||||
#define NFE_RX_LEN_MASK 0x3fff
|
||||
#define NFE_TX_TCP_UDP_CSUM (1 << 10)
|
||||
#define NFE_TX_IP_CSUM (1 << 11)
|
||||
#define NFE_TX_TSO (1 << 12)
|
||||
#define NFE_TX_TSO_SHIFT 14
|
||||
#define NFE_TX_VALID (1 << 15)
|
||||
|
||||
#define NFE_READ(sc, reg) \
|
||||
bus_read_4((sc)->nfe_res[0], (reg))
|
||||
|
||||
#define NFE_WRITE(sc, reg, val) \
|
||||
bus_write_4((sc)->nfe_res[0], (reg), (val))
|
||||
|
||||
#define NFE_TIMEOUT 1000
|
||||
|
||||
#ifndef PCI_VENDOR_NVIDIA
|
||||
#define PCI_VENDOR_NVIDIA 0x10DE
|
||||
#endif
|
||||
|
||||
#define PCI_PRODUCT_NVIDIA_NFORCE_LAN 0x01C3
|
||||
#define PCI_PRODUCT_NVIDIA_NFORCE2_LAN 0x0066
|
||||
#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 0x00D6
|
||||
#define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 0x0086
|
||||
#define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 0x008C
|
||||
#define PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 0x00E6
|
||||
#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 0x00DF
|
||||
#define PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 0x0056
|
||||
#define PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 0x0057
|
||||
#define PCI_PRODUCT_NVIDIA_MCP04_LAN1 0x0037
|
||||
#define PCI_PRODUCT_NVIDIA_MCP04_LAN2 0x0038
|
||||
#define PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 0x0268
|
||||
#define PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 0x0269
|
||||
#define PCI_PRODUCT_NVIDIA_MCP55_LAN1 0x0372
|
||||
#define PCI_PRODUCT_NVIDIA_MCP55_LAN2 0x0373
|
||||
#define PCI_PRODUCT_NVIDIA_MCP61_LAN1 0x03e5
|
||||
#define PCI_PRODUCT_NVIDIA_MCP61_LAN2 0x03e6
|
||||
#define PCI_PRODUCT_NVIDIA_MCP61_LAN3 0x03ee
|
||||
#define PCI_PRODUCT_NVIDIA_MCP61_LAN4 0x03ef
|
||||
#define PCI_PRODUCT_NVIDIA_MCP65_LAN1 0x0450
|
||||
#define PCI_PRODUCT_NVIDIA_MCP65_LAN2 0x0451
|
||||
#define PCI_PRODUCT_NVIDIA_MCP65_LAN3 0x0452
|
||||
#define PCI_PRODUCT_NVIDIA_MCP65_LAN4 0x0453
|
||||
#define PCI_PRODUCT_NVIDIA_MCP67_LAN1 0x054c
|
||||
#define PCI_PRODUCT_NVIDIA_MCP67_LAN2 0x054d
|
||||
#define PCI_PRODUCT_NVIDIA_MCP67_LAN3 0x054e
|
||||
#define PCI_PRODUCT_NVIDIA_MCP67_LAN4 0x054f
|
||||
|
||||
#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1
|
||||
#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2
|
||||
#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN
|
||||
#define PCI_PRODUCT_NVIDIA_CK804_LAN1 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1
|
||||
#define PCI_PRODUCT_NVIDIA_CK804_LAN2 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2
|
||||
#define PCI_PRODUCT_NVIDIA_MCP51_LAN1 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1
|
||||
#define PCI_PRODUCT_NVIDIA_MCP51_LAN2 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2
|
||||
|
||||
#define NFE_DEBUG 0x0000
|
||||
#define NFE_DEBUG_INIT 0x0001
|
||||
#define NFE_DEBUG_RUNNING 0x0002
|
||||
#define NFE_DEBUG_DEINIT 0x0004
|
||||
#define NFE_DEBUG_IOCTL 0x0008
|
||||
#define NFE_DEBUG_INTERRUPT 0x0010
|
||||
#define NFE_DEBUG_API 0x0020
|
||||
#define NFE_DEBUG_LOCK 0x0040
|
||||
#define NFE_DEBUG_BROKEN 0x0080
|
||||
#define NFE_DEBUG_MII 0x0100
|
||||
#define NFE_DEBUG_ALL 0xFFFF
|
||||
138
src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfevar.h
Normal file
138
src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfevar.h
Normal file
@ -0,0 +1,138 @@
|
||||
/* $OpenBSD: if_nfevar.h,v 1.11 2006/02/19 13:57:02 damien Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2005 Jonathan Gray <jsg@openbsd.org>
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $FreeBSD: src/sys/dev/nfe/if_nfevar.h,v 1.5 2007/07/24 01:11:00 yongari Exp $
|
||||
*/
|
||||
|
||||
struct nfe_tx_data {
|
||||
bus_dmamap_t tx_data_map;
|
||||
struct mbuf *m;
|
||||
};
|
||||
|
||||
struct nfe_tx_ring {
|
||||
bus_dma_tag_t tx_desc_tag;
|
||||
bus_dmamap_t tx_desc_map;
|
||||
bus_addr_t physaddr;
|
||||
struct nfe_desc32 *desc32;
|
||||
struct nfe_desc64 *desc64;
|
||||
bus_dma_tag_t tx_data_tag;
|
||||
struct nfe_tx_data data[NFE_TX_RING_COUNT];
|
||||
int queued;
|
||||
int cur;
|
||||
int next;
|
||||
};
|
||||
|
||||
struct nfe_jpool_entry {
|
||||
int slot;
|
||||
SLIST_ENTRY(nfe_jpool_entry) jpool_entries;
|
||||
};
|
||||
|
||||
struct nfe_rx_data {
|
||||
bus_dmamap_t rx_data_map;
|
||||
bus_addr_t paddr;
|
||||
struct mbuf *m;
|
||||
};
|
||||
|
||||
struct nfe_rx_ring {
|
||||
bus_dma_tag_t rx_desc_tag;
|
||||
bus_dmamap_t rx_desc_map;
|
||||
bus_addr_t physaddr;
|
||||
struct nfe_desc32 *desc32;
|
||||
struct nfe_desc64 *desc64;
|
||||
bus_dma_tag_t rx_data_tag;
|
||||
bus_dmamap_t rx_spare_map;
|
||||
struct nfe_rx_data data[NFE_RX_RING_COUNT];
|
||||
int cur;
|
||||
int next;
|
||||
};
|
||||
|
||||
struct nfe_jrx_ring {
|
||||
bus_dma_tag_t jrx_desc_tag;
|
||||
bus_dmamap_t jrx_desc_map;
|
||||
bus_dma_tag_t jrx_jumbo_tag;
|
||||
bus_dmamap_t jrx_jumbo_map;
|
||||
void *jpool;
|
||||
caddr_t jslots[NFE_JSLOTS];
|
||||
bus_addr_t jphysaddr;
|
||||
struct nfe_desc32 *jdesc32;
|
||||
struct nfe_desc64 *jdesc64;
|
||||
bus_dma_tag_t jrx_data_tag;
|
||||
bus_dmamap_t jrx_spare_map;
|
||||
struct nfe_rx_data jdata[NFE_JUMBO_RX_RING_COUNT];
|
||||
int jcur;
|
||||
int jnext;
|
||||
};
|
||||
|
||||
struct nfe_softc {
|
||||
struct ifnet *nfe_ifp;
|
||||
device_t nfe_dev;
|
||||
uint16_t nfe_devid;
|
||||
uint16_t nfe_revid;
|
||||
device_t nfe_miibus;
|
||||
struct mtx nfe_mtx;
|
||||
struct resource *nfe_res[1];
|
||||
struct resource *nfe_msix_res;
|
||||
struct resource *nfe_msix_pba_res;
|
||||
struct resource *nfe_irq[NFE_MSI_MESSAGES];
|
||||
void *nfe_intrhand[NFE_MSI_MESSAGES];
|
||||
struct callout nfe_stat_ch;
|
||||
int nfe_watchdog_timer;
|
||||
|
||||
bus_dma_tag_t nfe_parent_tag;
|
||||
|
||||
int nfe_if_flags;
|
||||
uint32_t nfe_flags;
|
||||
#define NFE_JUMBO_SUP 0x0001
|
||||
#define NFE_40BIT_ADDR 0x0002
|
||||
#define NFE_HW_CSUM 0x0004
|
||||
#define NFE_HW_VLAN 0x0008
|
||||
#define NFE_PWR_MGMT 0x0010
|
||||
#define NFE_CORRECT_MACADDR 0x0020
|
||||
#define NFE_TX_FLOW_CTRL 0x0040
|
||||
int nfe_jumbo_disable;
|
||||
uint32_t rxtxctl;
|
||||
uint8_t mii_phyaddr;
|
||||
uint8_t eaddr[ETHER_ADDR_LEN];
|
||||
struct taskqueue *nfe_tq;
|
||||
struct task nfe_int_task;
|
||||
struct task nfe_tx_task;
|
||||
struct task nfe_link_task;
|
||||
int nfe_link;
|
||||
int nfe_suspended;
|
||||
int nfe_framesize;
|
||||
int nfe_process_limit;
|
||||
int nfe_force_tx;
|
||||
uint32_t nfe_irq_status;
|
||||
uint32_t nfe_irq_mask;
|
||||
uint32_t nfe_intrs;
|
||||
uint32_t nfe_nointrs;
|
||||
uint32_t nfe_msi;
|
||||
uint32_t nfe_msix;
|
||||
|
||||
struct nfe_tx_ring txq;
|
||||
struct nfe_rx_ring rxq;
|
||||
struct nfe_jrx_ring jrxq;
|
||||
SLIST_HEAD(__nfe_jfreehead, nfe_jpool_entry) nfe_jfree_listhead;
|
||||
SLIST_HEAD(__nfe_jinusehead, nfe_jpool_entry) nfe_jinuse_listhead;
|
||||
struct mtx nfe_jlist_mtx;
|
||||
};
|
||||
|
||||
struct nfe_type {
|
||||
uint16_t vid_id;
|
||||
uint16_t dev_id;
|
||||
char *name;
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user