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RCS file: /cvsroot/open-beos/current/src/add-ons/accelerants/nvidia/engine/nv_maven.c,v Working file: nv_maven.c head: 1.2 branch: locks: strict access list: symbolic names: openBeOS_Nvidia_V0_07_src: 1.1 openBeOS_Nvidia_V0_06_src: 1.1 openBeOS_Nvidia_V0_05_src: 1.1 openBeOS_Nvidia_V0_04_src: 1.1 openBeOS_Nvidia_V0_03_src: 1.1 openBeOS_Nvidia_V0_02_src: 1.1 keyword substitution: kv total revisions: 2; selected revisions: 2 description: ---------------------------- revision 1.2 date: 2004/01/15 21:14:20; author: rudolfc; state: Exp; lines: +185 -148 secondary head updates, cardrecognition updates (fx5950, fx5700) ---------------------------- revision 1.1 date: 2003/11/23 05:30:14; author: shatty; state: Exp; add nvidia accelerant --------------------------------------------------------------------------------------- git-svn-id: file:///srv/svn/repos/haiku/trunk/current@6140 a95241bf-73f2-0310-859d-f6bbb57e9c96
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shatty
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307
src/add-ons/accelerants/nvidia/engine/nv_dac2.c
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307
src/add-ons/accelerants/nvidia/engine/nv_dac2.c
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/* program the secondary DAC */
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/* Author:
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Rudolf Cornelissen 12/2003-1/2004
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*/
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#define MODULE_BIT 0x00001000
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#include "nv_std.h"
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static status_t nv10_nv20_dac2_pix_pll_find(
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display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test);
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/*set the mode, brightness is a value from 0->2 (where 1 is equivalent to direct)*/
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status_t nv_dac2_mode(int mode,float brightness)
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{
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uint8 *r,*g,*b;
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int i, ri;
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/*set colour arrays to point to space reserved in shared info*/
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r = si->color_data;
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g = r + 256;
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b = g + 256;
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LOG(4,("DAC2: Setting screen mode %d brightness %f\n", mode, brightness));
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/* init the palette for brightness specified */
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/* (Nvidia cards always use MSbits from screenbuffer as index for PAL) */
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for (i = 0; i < 256; i++)
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{
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ri = i * brightness;
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if (ri > 255) ri = 255;
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b[i] = g[i] = r[i] = ri;
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}
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if (nv_dac2_palette(r,g,b) != B_OK) return B_ERROR;
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/*set the mode - also sets VCLK dividor*/
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// DXIW(MULCTRL, mode);
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// LOG(2,("DAC: mulctrl 0x%02x\n", DXIR(MULCTRL)));
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/* disable palette RAM adressing mask */
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NV_REG8(NV8_PAL2MASK) = 0xff;
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LOG(2,("DAC2: PAL pixrdmsk readback $%02x\n", NV_REG8(NV8_PAL2MASK)));
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return B_OK;
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}
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/*program the DAC palette using the given r,g,b values*/
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status_t nv_dac2_palette(uint8 r[256],uint8 g[256],uint8 b[256])
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{
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int i;
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LOG(4,("DAC2: setting palette\n"));
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/* select first PAL adress before starting programming */
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NV_REG8(NV8_PAL2INDW) = 0x00;
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/* loop through all 256 to program DAC */
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for (i = 0; i < 256; i++)
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{
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/* the 6 implemented bits are on b0-b5 of the bus */
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NV_REG8(NV8_PAL2DATA) = r[i];
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NV_REG8(NV8_PAL2DATA) = g[i];
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NV_REG8(NV8_PAL2DATA) = b[i];
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}
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if (NV_REG8(NV8_PAL2INDW) != 0x00)
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{
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LOG(8,("DAC2: PAL write index incorrect after programming\n"));
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return B_ERROR;
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}
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if (1)
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{//reread LUT
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uint8 R, G, B;
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/* select first PAL adress to read (modulo 3 counter) */
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NV_REG8(NV8_PAL2INDR) = 0x00;
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for (i = 0; i < 256; i++)
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{
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R = NV_REG8(NV8_PAL2DATA);
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G = NV_REG8(NV8_PAL2DATA);
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B = NV_REG8(NV8_PAL2DATA);
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if ((r[i] != R) || (g[i] != G) || (b[i] != B))
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LOG(1,("DAC2 palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed
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}
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}
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return B_OK;
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}
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/*program the pixpll - frequency in kHz*/
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/*important notes:
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* PIXPLLC is used - others should be kept as is
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* BESCLK,CRTC2 are not touched
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*/
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status_t nv_dac2_set_pix_pll(display_mode target)
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{
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uint8 m=0,n=0,p=0;
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// uint time = 0;
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float pix_setting, req_pclk;
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status_t result;
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req_pclk = (target.timing.pixel_clock)/1000.0;
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LOG(4,("DAC2: Setting PIX PLL for pixelclock %f\n", req_pclk));
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/* signal that we actually want to set the mode */
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result = nv_dac2_pix_pll_find(target,&pix_setting,&m,&n,&p, 1);
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if (result != B_OK)
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{
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return result;
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}
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/*reprogram (disable,select,wait for stability,enable)*/
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// DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0F)|0x04); /*disable the PIXPLL*/
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// DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0C)|0x01); /*select the PIXPLL*/
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/* select pixelPLL registerset C */
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DAC2W(PLLSEL, 0x10000700);
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/* program new frequency */
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DAC2W(PIXPLLC, ((p << 16) | (n << 8) | m));
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/* Wait for the PIXPLL frequency to lock until timeout occurs */
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//fixme: do NV cards have a LOCK indication bit??
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/* while((!(DXIR(PIXPLLSTAT)&0x40)) & (time <= 2000))
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{
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time++;
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snooze(1);
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}
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if (time > 2000)
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LOG(2,("DAC: PIX PLL frequency not locked!\n"));
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else
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LOG(2,("DAC: PIX PLL frequency locked\n"));
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DXIW(PIXCLKCTRL,DXIR(PIXCLKCTRL)&0x0B); //enable the PIXPLL
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*/
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//for now:
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/* Give the PIXPLL frequency some time to lock... */
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snooze(1000);
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LOG(2,("DAC2: PIX PLL frequency should be locked now...\n"));
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return B_OK;
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}
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/* find nearest valid pix pll */
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status_t nv_dac2_pix_pll_find
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(display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test)
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{
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switch (si->ps.card_type) {
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default: return nv10_nv20_dac2_pix_pll_find(target, calc_pclk, m_result, n_result, p_result, test);
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}
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return B_ERROR;
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}
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/* find nearest valid pixel PLL setting */
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static status_t nv10_nv20_dac2_pix_pll_find(
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display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test)
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{
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int m = 0, n = 0, p = 0/*, m_max*/;
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float error, error_best = 999999999;
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int best[3];
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float f_vco, max_pclk;
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float req_pclk = target.timing.pixel_clock/1000.0;
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/* determine the max. reference-frequency postscaler setting for the
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* current card (see G100, G200 and G400 specs). */
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/* switch(si->ps.card_type)
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{
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case G100:
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LOG(4,("DAC: G100 restrictions apply\n"));
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m_max = 7;
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break;
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case G200:
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LOG(4,("DAC: G200 restrictions apply\n"));
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m_max = 7;
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break;
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default:
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LOG(4,("DAC: G400/G400MAX restrictions apply\n"));
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m_max = 32;
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break;
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}
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*/
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LOG(4,("DAC2: NV10/NV20 restrictions apply\n"));
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/* determine the max. pixelclock for the current videomode */
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switch (target.space)
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{
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case B_CMAP8:
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max_pclk = si->ps.max_dac2_clock_8;
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break;
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case B_RGB15_LITTLE:
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case B_RGB16_LITTLE:
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max_pclk = si->ps.max_dac2_clock_16;
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break;
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case B_RGB24_LITTLE:
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max_pclk = si->ps.max_dac2_clock_24;
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break;
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case B_RGB32_LITTLE:
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max_pclk = si->ps.max_dac2_clock_32;
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break;
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default:
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/* use fail-safe value */
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max_pclk = si->ps.max_dac2_clock_32;
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break;
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}
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/* if some dualhead mode is active, an extra restriction might apply */
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if ((target.flags & DUALHEAD_BITS) && (target.space == B_RGB32_LITTLE))
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max_pclk = si->ps.max_dac2_clock_32dh;
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/* Make sure the requested pixelclock is within the PLL's operational limits */
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/* lower limit is min_pixel_vco divided by highest postscaler-factor */
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if (req_pclk < (si->ps.min_video_vco / 16.0))
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{
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LOG(4,("DAC2: clamping pixclock: requested %fMHz, set to %fMHz\n",
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req_pclk, (float)(si->ps.min_video_vco / 16.0)));
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req_pclk = (si->ps.min_video_vco / 16.0);
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}
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/* upper limit is given by pins in combination with current active mode */
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if (req_pclk > max_pclk)
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{
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LOG(4,("DAC2: clamping pixclock: requested %fMHz, set to %fMHz\n",
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req_pclk, (float)max_pclk));
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req_pclk = max_pclk;
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}
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/* iterate through all valid PLL postscaler settings */
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for (p=0x01; p < 0x20; p = p<<1)
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{
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/* calculate the needed VCO frequency for this postscaler setting */
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f_vco = req_pclk * p;
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/* check if this is within range of the VCO specs */
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if ((f_vco >= si->ps.min_video_vco) && (f_vco <= si->ps.max_video_vco))
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{
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/* NV31 (FX5600) tweak (missing register for 2nd VCO postscaler) */
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f_vco /= si->pixpll_vco_div2;
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/* iterate trough all valid reference-frequency postscaler settings */
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for (m = 7; m <= 14; m++)
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{
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/* check if phase-discriminator will be within operational limits */
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if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue;
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/* calculate VCO postscaler setting for current setup.. */
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n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);
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/* ..and check for validity */
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if ((n < 1) || (n > 255)) continue;
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/* find error in frequency this setting gives */
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/* si->pixpll_vco_div2 below is NV31 (FX5600) tweak (missing register) */
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error =
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fabs((req_pclk / si->pixpll_vco_div2) - (((si->ps.f_ref / m) * n) / p));
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/* note the setting if best yet */
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if (error < error_best)
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{
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error_best = error;
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best[0]=m;
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best[1]=n;
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best[2]=p;
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}
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}
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}
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}
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/* setup the scalers programming values for found optimum setting */
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m = best[0];
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n = best[1];
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p = best[2];
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/* log the VCO frequency found */
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f_vco = ((si->ps.f_ref / m) * n);
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/* NV31 (FX5600) tweak (missing register for 2nd VCO postscaler) */
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f_vco *= si->pixpll_vco_div2;
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LOG(2,("DAC2: pix VCO frequency found %fMhz\n", f_vco));
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/* return the results */
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*calc_pclk = (f_vco / p);
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*m_result = m;
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*n_result = n;
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switch(p)
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{
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case 1:
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p = 0x00;
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break;
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case 2:
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p = 0x01;
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break;
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case 4:
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p = 0x02;
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break;
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case 8:
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p = 0x03;
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break;
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case 16:
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p = 0x04;
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break;
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}
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*p_result = p;
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/* display the found pixelclock values */
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LOG(2,("DAC2: pix PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n",
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req_pclk, *calc_pclk, *m_result, *n_result, *p_result));
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return B_OK;
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}
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