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fixed get_timing_constraints hook, also added extra modeline validity checks befor modes are actually set in case user does not adhere to info provided in that hook.

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@8250 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2004-07-01 09:58:44 +00:00
parent ae2555ef40
commit 0ecea71b00
3 changed files with 34 additions and 19 deletions
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37
src/add-ons/accelerants/nvidia/GetTimingConstraints.c
View File

@ -1,7 +1,6 @@
/*
Authors:
Mark Watson - 21/6/00,
Apsed
Author:
Rudolf Cornelissen 7/2004
*/
#define MODULE_BIT 0x01000000
@ -11,20 +10,24 @@
/* Used to help generate mode lines */
status_t GET_TIMING_CONSTRAINTS(display_timing_constraints * dtc)
{
// apsed, TODO, is that following card capabilities ??
LOG(4, ("GET_TIMING_CONSTRAINTS\n"));
dtc->h_res=8;
dtc->h_sync_min=8;
dtc->h_sync_max=248;
dtc->h_blank_min=8;
dtc->h_blank_max=504;
dtc->v_res=1;
dtc->v_sync_min=1;
dtc->v_sync_max=15;
dtc->v_blank_min=1;
dtc->v_blank_max=255;
LOG(4, ("GET_TIMING_CONSTRAINTS: returning info\n"));
/* specs are identical for all nVidia cards */
dtc->h_res = 8;
dtc->h_sync_min = 8;
dtc->h_sync_max = 248;
/* Note:
* h_blank info is used to determine the max. diff. between h_total and h_display! */
dtc->h_blank_min = 8;
dtc->h_blank_max = 1016;
dtc->v_res = 1;
dtc->v_sync_min = 1;
dtc->v_sync_max = 15;
/* Note:
* v_blank info is used to determine the max. diff. between v_total and v_display! */
dtc->v_blank_min = 1;
dtc->v_blank_max = 255;
return B_OK;
}

8
src/add-ons/accelerants/nvidia/engine/nv_crtc.c
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@ -1,6 +1,6 @@
/* CTRC functionality */
/* Author:
Rudolf Cornelissen 11/2002-6/2004
Rudolf Cornelissen 11/2002-7/2004
*/
#define MODULE_BIT 0x00040000
@ -41,6 +41,9 @@ status_t nv_crtc_validate_timing(
/* if hor. total does not leave room for a sensible sync pulse, increase it! */
if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80);
/* if hor. total does not adhere to max. blanking pulse width, decrease it! */
if (*ht > (*hd_e + 0x3f8)) *ht = (*hd_e + 0x3f8);
/* make sure sync pulse is not during display */
if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8);
if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8);
@ -71,6 +74,9 @@ status_t nv_crtc_validate_timing(
/*if vertical total does not leave room for a sync pulse, increase it!*/
if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3);
/* if vert. total does not adhere to max. blanking pulse width, decrease it! */
if (*vt > (*vd_e + 0xff)) *vt = (*vd_e + 0xff);
/* make sure sync pulse is not during display */
if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1);
if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1);

8
src/add-ons/accelerants/nvidia/engine/nv_crtc2.c
View File

@ -1,6 +1,6 @@
/* second CTRC functionality for GeForce cards */
/* Author:
Rudolf Cornelissen 11/2002-6/2004
Rudolf Cornelissen 11/2002-7/2004
*/
#define MODULE_BIT 0x00020000
@ -34,6 +34,9 @@ status_t nv_crtc2_validate_timing(
/* if hor. total does not leave room for a sensible sync pulse, increase it! */
if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80);
/* if hor. total does not adhere to max. blanking pulse width, decrease it! */
if (*ht > (*hd_e + 0x3f8)) *ht = (*hd_e + 0x3f8);
/* make sure sync pulse is not during display */
if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8);
if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8);
@ -57,6 +60,9 @@ status_t nv_crtc2_validate_timing(
/*if vertical total does not leave room for a sync pulse, increase it!*/
if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3);
/* if vert. total does not adhere to max. blanking pulse width, decrease it! */
if (*vt > (*vd_e + 0xff)) *vt = (*vd_e + 0xff);
/* make sure sync pulse is not during display */
if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1);
if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1);