completed experimental TVout support for singlehead cards using BT868/869, Conexant CX25870/CX25871 chips. As setups with laptop or DVI panels will probably mess up, it's still disabled apart from enabling a testimage. Now starting actual testing..
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@14317 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
parent
c8c6353050
commit
0b36eea44d
@ -90,6 +90,11 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
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/* disable interrupts using the kernel driver */
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interrupt_enable(false);
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/* disable TVout (set GPU CRTC to master mode) */
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//fixme: testing on singlehead cards only for now...
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//tmp disabled:
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// if (!(si->ps.secondary_head)) BT_stop_tvout();
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/* find current DPMS state, then turn off screen(s) */
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head1_dpms_fetch(&display, &h, &v);
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head1_dpms(false, false, false);
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@ -1576,72 +1576,61 @@ status_t BT_stop_tvout(void)
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//fixme: see if better DPMS state fetching can be setup for crtc.c (!)
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CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0x3f));
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//fixme: setup...
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/*
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uint32 temp32;
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unsigned char VertRetrace;
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//SEQ:
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*(dev->pcio_base + 0x3c4) = 0x01;
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*(dev->pcio_base + 0x3c5) = 0x01;
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//fixme: is this needed? does b5 have a special meaning in nvidia cards?
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//normal in this driver is:
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// SEQW(CLKMODE, 0x21);
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//betvout:
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SEQW(CLKMODE, 0x01);
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//wait for 1 image to be generated to make sure VGA has kicked in and is
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//running OK before continuing...
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//(Kick in will fail often if we do not wait here: You'll notice this most
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// prominently in VESA 640x480 mode. Just try switching about 10 times and
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// you'll probably see... (re-checked for PCI V0.20))
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VertRetrace = 1;
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//(make sure we are 'in' active VGA picture:)
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do VertRetrace = (*(dev->pcio_base + 0x3da) & 0x08);
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while (VertRetrace);
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//(wait for vertical retrace start on VGA:)
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do VertRetrace = (*(dev->pcio_base + 0x3da) & 0x08);
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while (!VertRetrace);
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//(make sure we are 'in' active VGA picture again:)
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do VertRetrace = (*(dev->pcio_base + 0x3da) & 0x08);
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while (VertRetrace);
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//'update' PIXEL/TV:
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*(dev->pcio_base + AdresReg) = 0x28;
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*(dev->pcio_base + DataReg) &= 0x03;
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/* wait for one image to be generated to make sure VGA has kicked in and is
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* running OK before continuing...
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* (Kicking in will fail often if we do not wait here) */
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/* make sure we are 'in' active VGA picture */
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while (NV_REG8(NV8_INSTAT1) & 0x08) snooze(1);
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/* wait for next vertical retrace start on VGA */
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while (!(NV_REG8(NV8_INSTAT1) & 0x08)) snooze(1);
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/* now wait until we are 'in' active VGA picture again */
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while (NV_REG8(NV8_INSTAT1) & 0x08) snooze(1);
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/* set CRTC to master mode (b7 = 0) and clear TVadjust (b3-5 = %000) */
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//fixme:
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//update this to take flatpanels into consideration..
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CRTCW(PIXEL, (CRTCR(PIXEL) & 0x03));
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//fixme: checkout...
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//CAUTION:
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//On the TNT1, these memadresses apparantly cannot be read (sometimes)!;
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//write actions do succeed though... (tested on ISA...)
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//($00680700 b1-23 and b25-31 apparantly are 'don't cares'...)
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//write actions do succeed though... (tested only on ISA bus yet..)
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//SWITCH RIVA pixelclock to be RIVA's own (so: directly):
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//MEMADR $00680700:
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temp32 = (*(dev->regs + (0x00680700 >> 2)) & ~0x00000001);
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*(dev->regs + (0x00680700 >> 2)) = (temp32 | 0x01000000);
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/* setup TVencoder connection */
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/* b1-0 = %00: encoder type is SLAVE;
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* b24 = 1: VIP datapos is b0-7 */
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//fixme: setup completely instead of relying on pre-init by BIOS..
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DACW(TV_SETUP, ((DACR(TV_SETUP) & ~0x00000001) | 0x01000000));
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//switch RIVA PLL phase-lock to lock to RIVA's own internal pixelclock:
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//MEMADR $0068050c: PLLSEL: warning dualhead is killed here! (PLL2 shutoff)
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*(dev->regs + (0x0068050c >> 2)) = 0x10000700;
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/* tell GPU to use pixelclock from internal source instead of using TVencoder */
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DACW(PLLSEL, 0x10000700);
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if (si->ps.secondary_head) DACW(PLLSEL, (DACR(PLLSEL) | 0x20000800));
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//TREG:
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*(dev->pcio_base + AdresReg) = 0x3d;
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*(dev->pcio_base + DataReg) = 0x00;
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/* HTOTAL, VTOTAL and OVERFLOW return their default CRTC use, instead of
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* H, V-low and V-high 'shadow' counters(?)(b0, 4 and 6 = 0) (b7 use = unknown) */
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CRTCW(TREG, 0x00);
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//make sure LCD is switched off:
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//MEMADR $00680880:
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*(dev->regs + (0x00680880 >> 2)) |= 0x10000000;
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/* powerdown FPclock (not touching TMDS power) */
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//fixme: do we need this? might kill off panel support...
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DACW(FP_DEBUG0, (DACR(FP_DEBUG0) | 0x10000000));
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//LCD:
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*(dev->pcio_base + AdresReg) = 0x33;
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*(dev->pcio_base + DataReg) &= 0xfc;
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//Set overscan color to 'black':
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//Disable this part if you're trying to center the output on TV,
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//you'll get blue overscan range color then. Use this as a guide-'line' ;-)
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//(select index adress register:)
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*(dev->pcio_base + 0x3da);
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//(write index for 'overscan color' register:)
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*(dev->pcio_base + 0x3c0) = 0x11;
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//(write data for 'overscan color' register:)
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*(dev->pcio_base + 0x3c0) = 0x00;
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*/
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/* select TV encoder, not panel encoder (b0 = 0).
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* Note:
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* Both are devices using the CRTC in slaved mode. */
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//fixme:
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//update this to take flatpanels into consideration..
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//fixme2:
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//probably better don't touch b1: it's used for powering ext. TMDS (or so) (?)
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CRTCW(LCD, (CRTCR(LCD) & 0xfc));
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/* fixme if needed:
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* a full encoder chip reset could be done here (so after decoupling crtc)... */
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