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completed engine command struct defines so on-the-fly FIFO channel re-assignments can be done. Will be expanded more to include used 3D commands.

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@10509 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2004-12-20 15:34:56 +00:00
parent 9c609269f4
commit 07e14ea9ad
3 changed files with 62 additions and 11 deletions
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9
headers/private/graphics/nvidia/DriverInterface.h
View File

@ -96,13 +96,12 @@ enum {
#define MAXBUFFERS 3
/* internal used info on overlay buffers */
typedef struct
{
typedef struct {
uint16 slopspace;
uint32 size;
} int_buf_info;
typedef struct settings { // apsed, see comments in nv.settings
typedef struct { // apsed, see comments in nv.settings
// for driver
char accelerant[B_FILE_NAME_LENGTH];
bool dumprom;
@ -115,7 +114,7 @@ typedef struct settings { // apsed, see comments in nv.settings
bool force_pci;
bool unhide_fw;
bool pgm_panel;
} settings;
} nv_settings;
/*shared info*/
typedef struct {
@ -311,7 +310,7 @@ typedef struct {
uint8 rom_mirror[65536];
/* some configuration settings from ~/config/settings/kernel/drivers/nv.settings if exists */
settings settings;
nv_settings settings;
struct
{

58
headers/private/graphics/nvidia/nv_acc.h
View File

@ -47,6 +47,64 @@ typedef struct {
} cmd_nv_image_blit;
typedef struct {
uint32 reserved00[0x0004];
uint16 FifoFree; /* little endian (FIFO internal register) */
uint16 Nop; /* little endian (FIFO internal register) */
uint32 reserved01[0x00fa];
uint32 Color1A; /* b0-31 is color */
struct
{
uint32 LeftTop; /* b0-15 is top, b16-31 is left */
uint32 WidthHeight; /* b0-15 is height, b16-31 is width */
} UnclippedRectangle[0x40]; /* command can handle upto 64 unclipped rects */
//XFree also defines: (not used AFAIK ATM)
/*
U032 reserved04[(0x080)-3];
struct
{
U032 TopLeft;
U032 BottomRight;
} ClipB;
U032 Color1B;
struct
{
U032 TopLeft;
U032 BottomRight;
} ClippedRectangle[64];
U032 reserved05[(0x080)-5];
struct
{
U032 TopLeft;
U032 BottomRight;
} ClipC;
U032 Color1C;
U032 WidthHeightC;
U032 PointC;
U032 MonochromeData1C;
U032 reserved06[(0x080)+121];
struct
{
U032 TopLeft;
U032 BottomRight;
} ClipD;
U032 Color1D;
U032 WidthHeightInD;
U032 WidthHeightOutD;
U032 PointD;
U032 MonochromeData1D;
U032 reserved07[(0x080)+120];
struct
{
U032 TopLeft;
U032 BottomRight;
} ClipE;
U032 Color0E;
U032 Color1E;
U032 WidthHeightInE;
U032 WidthHeightOutE;
U032 PointE;
U032 MonochromeData01E;
*/
} cmd_nv3_gdi_rectangle_text;
typedef struct {

6
headers/private/graphics/nvidia/nv_macros.h
View File

@ -442,12 +442,6 @@
#define NVACC_FIFO_CH6 0x0080c000
#define NVACC_FIFO_CH7 0x0080e000
/* used bitmap registers */
#define NV16_BMP_FIFOFREE 0x0080a010 /* little endian */
#define NVACC_BMP_COLOR1A 0x0080a3fc /* 'mapped' from 0x006b03fc */
#define NVACC_BMP_UCRECTL_0 0x0080a400 /* 'mapped' from 0x006b0400 */
#define NVACC_BMP_UCRECSZ_0 0x0080a404 /* 'mapped' from 0x006b0404 */
/* Nvidia PCI direct registers */
#define NV32_PWRUPCTRL 0x00000200
#define NV32_DUALHEAD_CTRL 0x000010f0//verify!!!