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emulex_oce: Remove.

Browse Source 
It doesn't seem to work anymore, and it doesn't look to be particularly
maintained on FreeBSD's side of things. I think kallisti5 was the only
person who ever even attempted to use it.
This commit is contained in:
Augustin Cavalier 2022-04-25 19:26:10 -04:00
parent acfde4597c
commit 07b83028cd
13 changed files with 0 additions and 14890 deletions
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1
build/jam/images/definitions/minimum
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@ -196,7 +196,6 @@ SYSTEM_ADD_ONS_DRIVERS_NET = [ FFilterByBuildFeatures
atheros813x atheros81xx attansic_l1 attansic_l2
broadcom440x broadcom570x
dec21xxx
emulex_oce
ipro100 ipro1000
intel22x
jmicron2x0

1
src/add-ons/kernel/drivers/network/ether/Jamfile
View File

@ -16,7 +16,6 @@ HaikuSubInclude attansic_l1 ;
HaikuSubInclude attansic_l2 ;
HaikuSubInclude broadcom440x ;
HaikuSubInclude dec21xxx ;
HaikuSubInclude emulex_oce ;
HaikuSubInclude ipro100 ;
HaikuSubInclude jmicron2x0 ;
HaikuSubInclude marvell_yukon ;

23
src/add-ons/kernel/drivers/network/ether/emulex_oce/Jamfile
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@ -1,23 +0,0 @@
SubDir HAIKU_TOP src add-ons kernel drivers network ether emulex_oce ;
UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ]
: true ;
UsePrivateHeaders net system ;
UsePrivateKernelHeaders ;
SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 _XOPEN_SOURCE ] ;
UseHeaders [ FDirName $(SUBDIR) ] : true ;
SEARCH_SOURCE += [ FDirName $(SUBDIR) dev oce ] ;
KernelAddon emulex_oce :
glue.c
oce_hw.c
oce_if.c
oce_mbox.c
oce_queue.c
oce_sysctl.c
oce_util.c
: libfreebsd_network.a
;

597
src/add-ons/kernel/drivers/network/ether/emulex_oce/dev/oce/oce_hw.c
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@ -1,597 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (C) 2013 Emulex
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Emulex Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* Contact Information:
* freebsd-drivers@emulex.com
*
* Emulex
* 3333 Susan Street
* Costa Mesa, CA 92626
*/
/* $FreeBSD: releng/12.0/sys/dev/oce/oce_hw.c 333813 2018-05-18 20:13:34Z mmacy $ */
#include "oce_if.h"
static int oce_POST(POCE_SOFTC sc);
/**
* @brief Function to post status
* @param sc software handle to the device
*/
static int
oce_POST(POCE_SOFTC sc)
{
mpu_ep_semaphore_t post_status;
int tmo = 60000;
/* read semaphore CSR */
post_status.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc));
/* if host is ready then wait for fw ready else send POST */
if (post_status.bits.stage <= POST_STAGE_AWAITING_HOST_RDY) {
post_status.bits.stage = POST_STAGE_CHIP_RESET;
OCE_WRITE_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc), post_status.dw0);
}
/* wait for FW ready */
for (;;) {
if (--tmo == 0)
break;
DELAY(1000);
post_status.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc));
if (post_status.bits.error) {
device_printf(sc->dev,
"POST failed: %x\n", post_status.dw0);
return ENXIO;
}
if (post_status.bits.stage == POST_STAGE_ARMFW_READY)
return 0;
}
device_printf(sc->dev, "POST timed out: %x\n", post_status.dw0);
return ENXIO;
}
/**
* @brief Function for hardware initialization
* @param sc software handle to the device
*/
int
oce_hw_init(POCE_SOFTC sc)
{
int rc = 0;
rc = oce_POST(sc);
if (rc)
return rc;
/* create the bootstrap mailbox */
rc = oce_dma_alloc(sc, sizeof(struct oce_bmbx), &sc->bsmbx, 0);
if (rc) {
device_printf(sc->dev, "Mailbox alloc failed\n");
return rc;
}
rc = oce_reset_fun(sc);
if (rc)
goto error;
rc = oce_mbox_init(sc);
if (rc)
goto error;
rc = oce_get_fw_version(sc);
if (rc)
goto error;
rc = oce_get_fw_config(sc);
if (rc)
goto error;
sc->macaddr.size_of_struct = 6;
rc = oce_read_mac_addr(sc, 0, 1, MAC_ADDRESS_TYPE_NETWORK,
&sc->macaddr);
if (rc)
goto error;
if ((IS_BE(sc) && (sc->flags & OCE_FLAGS_BE3)) || IS_SH(sc)) {
rc = oce_mbox_check_native_mode(sc);
if (rc)
goto error;
} else
sc->be3_native = 0;
return rc;
error:
oce_dma_free(sc, &sc->bsmbx);
device_printf(sc->dev, "Hardware initialisation failed\n");
return rc;
}
/**
* @brief Releases the obtained pci resources
* @param sc software handle to the device
*/
void
oce_hw_pci_free(POCE_SOFTC sc)
{
int pci_cfg_barnum = 0;
if (IS_BE(sc) && (sc->flags & OCE_FLAGS_BE2))
pci_cfg_barnum = OCE_DEV_BE2_CFG_BAR;
else
pci_cfg_barnum = OCE_DEV_CFG_BAR;
if (sc->devcfg_res != NULL) {
bus_release_resource(sc->dev,
SYS_RES_MEMORY,
PCIR_BAR(pci_cfg_barnum), sc->devcfg_res);
sc->devcfg_res = (struct resource *)NULL;
sc->devcfg_btag = (bus_space_tag_t) 0;
sc->devcfg_bhandle = (bus_space_handle_t)0;
sc->devcfg_vhandle = (void *)NULL;
}
if (sc->csr_res != NULL) {
bus_release_resource(sc->dev,
SYS_RES_MEMORY,
PCIR_BAR(OCE_PCI_CSR_BAR), sc->csr_res);
sc->csr_res = (struct resource *)NULL;
sc->csr_btag = (bus_space_tag_t)0;
sc->csr_bhandle = (bus_space_handle_t)0;
sc->csr_vhandle = (void *)NULL;
}
if (sc->db_res != NULL) {
bus_release_resource(sc->dev,
SYS_RES_MEMORY,
PCIR_BAR(OCE_PCI_DB_BAR), sc->db_res);
sc->db_res = (struct resource *)NULL;
sc->db_btag = (bus_space_tag_t)0;
sc->db_bhandle = (bus_space_handle_t)0;
sc->db_vhandle = (void *)NULL;
}
}
/**
* @brief Function to get the PCI capabilities
* @param sc software handle to the device
*/
static
void oce_get_pci_capabilities(POCE_SOFTC sc)
{
uint32_t val;
#if __FreeBSD_version >= 1000000
#define pci_find_extcap pci_find_cap
#endif
if (pci_find_extcap(sc->dev, PCIY_PCIX, &val) == 0) {
if (val != 0)
sc->flags |= OCE_FLAGS_PCIX;
}
if (pci_find_extcap(sc->dev, PCIY_EXPRESS, &val) == 0) {
if (val != 0) {
uint16_t link_status =
pci_read_config(sc->dev, val + 0x12, 2);
sc->flags |= OCE_FLAGS_PCIE;
sc->pcie_link_speed = link_status & 0xf;
sc->pcie_link_width = (link_status >> 4) & 0x3f;
}
}
if (pci_find_extcap(sc->dev, PCIY_MSI, &val) == 0) {
if (val != 0)
sc->flags |= OCE_FLAGS_MSI_CAPABLE;
}
if (pci_find_extcap(sc->dev, PCIY_MSIX, &val) == 0) {
if (val != 0) {
val = pci_msix_count(sc->dev);
sc->flags |= OCE_FLAGS_MSIX_CAPABLE;
}
}
}
/**
* @brief Allocate PCI resources.
*
* @param sc software handle to the device
* @returns 0 if successful, or error
*/
int
oce_hw_pci_alloc(POCE_SOFTC sc)
{
int rr, pci_cfg_barnum = 0;
pci_sli_intf_t intf;
pci_enable_busmaster(sc->dev);
oce_get_pci_capabilities(sc);
sc->fn = pci_get_function(sc->dev);
/* setup the device config region */
if (IS_BE(sc) && (sc->flags & OCE_FLAGS_BE2))
pci_cfg_barnum = OCE_DEV_BE2_CFG_BAR;
else
pci_cfg_barnum = OCE_DEV_CFG_BAR;
rr = PCIR_BAR(pci_cfg_barnum);
if (IS_BE(sc) || IS_SH(sc))
sc->devcfg_res = bus_alloc_resource_any(sc->dev,
SYS_RES_MEMORY, &rr,
RF_ACTIVE|RF_SHAREABLE);
else
sc->devcfg_res = bus_alloc_resource_anywhere(sc->dev,
SYS_RES_MEMORY, &rr, 32768,
RF_ACTIVE|RF_SHAREABLE);
if (!sc->devcfg_res)
goto error;
sc->devcfg_btag = rman_get_bustag(sc->devcfg_res);
sc->devcfg_bhandle = rman_get_bushandle(sc->devcfg_res);
sc->devcfg_vhandle = rman_get_virtual(sc->devcfg_res);
/* Read the SLI_INTF register and determine whether we
* can use this port and its features
*/
intf.dw0 = pci_read_config((sc)->dev,OCE_INTF_REG_OFFSET,4);
if (intf.bits.sli_valid != OCE_INTF_VALID_SIG)
goto error;
if (intf.bits.sli_rev != OCE_INTF_SLI_REV4) {
device_printf(sc->dev, "Adapter doesnt support SLI4\n");
goto error;
}
if (intf.bits.sli_if_type == OCE_INTF_IF_TYPE_1)
sc->flags |= OCE_FLAGS_MBOX_ENDIAN_RQD;
if (intf.bits.sli_hint1 == OCE_INTF_FUNC_RESET_REQD)
sc->flags |= OCE_FLAGS_FUNCRESET_RQD;
if (intf.bits.sli_func_type == OCE_INTF_VIRT_FUNC)
sc->flags |= OCE_FLAGS_VIRTUAL_PORT;
/* Lancer has one BAR (CFG) but BE3 has three (CFG, CSR, DB) */
if (IS_BE(sc) || IS_SH(sc)) {
/* set up CSR region */
rr = PCIR_BAR(OCE_PCI_CSR_BAR);
sc->csr_res = bus_alloc_resource_any(sc->dev,
SYS_RES_MEMORY, &rr, RF_ACTIVE|RF_SHAREABLE);
if (!sc->csr_res)
goto error;
sc->csr_btag = rman_get_bustag(sc->csr_res);
sc->csr_bhandle = rman_get_bushandle(sc->csr_res);
sc->csr_vhandle = rman_get_virtual(sc->csr_res);
/* set up DB doorbell region */
rr = PCIR_BAR(OCE_PCI_DB_BAR);
sc->db_res = bus_alloc_resource_any(sc->dev,
SYS_RES_MEMORY, &rr, RF_ACTIVE|RF_SHAREABLE);
if (!sc->db_res)
goto error;
sc->db_btag = rman_get_bustag(sc->db_res);
sc->db_bhandle = rman_get_bushandle(sc->db_res);
sc->db_vhandle = rman_get_virtual(sc->db_res);
}
return 0;
error:
oce_hw_pci_free(sc);
return ENXIO;
}
/**
* @brief Function for device shutdown
* @param sc software handle to the device
* @returns 0 on success, error otherwise
*/
void
oce_hw_shutdown(POCE_SOFTC sc)
{
oce_stats_free(sc);
/* disable hardware interrupts */
oce_hw_intr_disable(sc);
#if defined(INET6) || defined(INET)
/* Free LRO resources */
oce_free_lro(sc);
#endif
/* Release queue*/
oce_queue_release_all(sc);
/*Delete Network Interface*/
oce_delete_nw_interface(sc);
/* After fw clean we dont send any cmds to fw.*/
oce_fw_clean(sc);
/* release intr resources */
oce_intr_free(sc);
/* release PCI resources */
oce_hw_pci_free(sc);
/* free mbox specific resources */
LOCK_DESTROY(&sc->bmbx_lock);
LOCK_DESTROY(&sc->dev_lock);
oce_dma_free(sc, &sc->bsmbx);
}
/**
* @brief Function for creating nw interface.
* @param sc software handle to the device
* @returns 0 on success, error otherwise
*/
int
oce_create_nw_interface(POCE_SOFTC sc)
{
int rc;
uint32_t capab_flags;
uint32_t capab_en_flags;
/* interface capabilities to give device when creating interface */
capab_flags = OCE_CAPAB_FLAGS;
/* capabilities to enable by default (others set dynamically) */
capab_en_flags = OCE_CAPAB_ENABLE;
if (IS_XE201(sc)) {
/* LANCER A0 workaround */
capab_en_flags &= ~MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR;
capab_flags &= ~MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR;
}
if (IS_SH(sc) || IS_XE201(sc))
capab_flags |= MBX_RX_IFACE_FLAGS_MULTICAST;
if (sc->enable_hwlro) {
capab_flags |= MBX_RX_IFACE_FLAGS_LRO;
capab_en_flags |= MBX_RX_IFACE_FLAGS_LRO;
}
/* enable capabilities controlled via driver startup parameters */
if (is_rss_enabled(sc))
capab_en_flags |= MBX_RX_IFACE_FLAGS_RSS;
else {
capab_en_flags &= ~MBX_RX_IFACE_FLAGS_RSS;
capab_flags &= ~MBX_RX_IFACE_FLAGS_RSS;
}
rc = oce_if_create(sc,
capab_flags,
capab_en_flags,
0, &sc->macaddr.mac_addr[0], &sc->if_id);
if (rc)
return rc;
atomic_inc_32(&sc->nifs);
sc->if_cap_flags = capab_en_flags;
/* set default flow control */
rc = oce_set_flow_control(sc, sc->flow_control);
if (rc)
goto error;
rc = oce_rxf_set_promiscuous(sc, sc->promisc);
if (rc)
goto error;
return rc;
error:
oce_delete_nw_interface(sc);
return rc;
}
/**
* @brief Function to delete a nw interface.
* @param sc software handle to the device
*/
void
oce_delete_nw_interface(POCE_SOFTC sc)
{
/* currently only single interface is implmeneted */
if (sc->nifs > 0) {
oce_if_del(sc, sc->if_id);
atomic_dec_32(&sc->nifs);
}
}
/**
* @brief Soft reset.
* @param sc software handle to the device
* @returns 0 on success, error otherwise
*/
int
oce_pci_soft_reset(POCE_SOFTC sc)
{
int rc;
mpu_ep_control_t ctrl;
ctrl.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_CONTROL);
ctrl.bits.cpu_reset = 1;
OCE_WRITE_CSR_MPU(sc, csr, MPU_EP_CONTROL, ctrl.dw0);
DELAY(50);
rc=oce_POST(sc);
return rc;
}
/**
* @brief Function for hardware start
* @param sc software handle to the device
* @returns 0 on success, error otherwise
*/
int
oce_hw_start(POCE_SOFTC sc)
{
struct link_status link = { 0 };
int rc = 0;
rc = oce_get_link_status(sc, &link);
if (rc)
return 1;
if (link.logical_link_status == NTWK_LOGICAL_LINK_UP) {
sc->link_status = NTWK_LOGICAL_LINK_UP;
if_link_state_change(sc->ifp, LINK_STATE_UP);
} else {
sc->link_status = NTWK_LOGICAL_LINK_DOWN;
if_link_state_change(sc->ifp, LINK_STATE_DOWN);
}
sc->link_speed = link.phys_port_speed;
sc->qos_link_speed = (uint32_t )link.qos_link_speed * 10;
rc = oce_start_mq(sc->mq);
/* we need to get MCC aync events. So enable intrs and arm
first EQ, Other EQs will be armed after interface is UP
*/
oce_hw_intr_enable(sc);
oce_arm_eq(sc, sc->eq[0]->eq_id, 0, TRUE, FALSE);
/* Send first mcc cmd and after that we get gracious
MCC notifications from FW
*/
oce_first_mcc_cmd(sc);
return rc;
}
/**
* @brief Function for hardware enable interupts.
* @param sc software handle to the device
*/
void
oce_hw_intr_enable(POCE_SOFTC sc)
{
uint32_t reg;
reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL);
reg |= HOSTINTR_MASK;
OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg);
}
/**
* @brief Function for hardware disable interupts
* @param sc software handle to the device
*/
void
oce_hw_intr_disable(POCE_SOFTC sc)
{
uint32_t reg;
reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL);
reg &= ~HOSTINTR_MASK;
OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg);
}
/**
* @brief Function for hardware update multicast filter
* @param sc software handle to the device
*/
int
oce_hw_update_multicast(POCE_SOFTC sc)
{
struct ifnet *ifp = sc->ifp;
struct ifmultiaddr *ifma;
struct mbx_set_common_iface_multicast *req = NULL;
OCE_DMA_MEM dma;
int rc = 0;
/* Allocate DMA mem*/
if (oce_dma_alloc(sc, sizeof(struct mbx_set_common_iface_multicast),
&dma, 0))
return ENOMEM;
req = OCE_DMAPTR(&dma, struct mbx_set_common_iface_multicast);
bzero(req, sizeof(struct mbx_set_common_iface_multicast));
#if __FreeBSD_version > 800000
if_maddr_rlock(ifp);
#endif
TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
if (ifma->ifma_addr->sa_family != AF_LINK)
continue;
if (req->params.req.num_mac == OCE_MAX_MC_FILTER_SIZE) {
/*More multicast addresses than our hardware table
So Enable multicast promiscus in our hardware to
accept all multicat packets
*/
req->params.req.promiscuous = 1;
break;
}
bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
&req->params.req.mac[req->params.req.num_mac],
ETH_ADDR_LEN);
req->params.req.num_mac = req->params.req.num_mac + 1;
}
#if __FreeBSD_version > 800000
if_maddr_runlock(ifp);
#endif
req->params.req.if_id = sc->if_id;
rc = oce_update_multicast(sc, &dma);
oce_dma_free(sc, &dma);
return rc;
}

4199
src/add-ons/kernel/drivers/network/ether/emulex_oce/dev/oce/oce_hw.h
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3002
src/add-ons/kernel/drivers/network/ether/emulex_oce/dev/oce/oce_if.c
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1274
src/add-ons/kernel/drivers/network/ether/emulex_oce/dev/oce/oce_if.h
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2372
src/add-ons/kernel/drivers/network/ether/emulex_oce/dev/oce/oce_mbox.c
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1407
src/add-ons/kernel/drivers/network/ether/emulex_oce/dev/oce/oce_queue.c
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1597
src/add-ons/kernel/drivers/network/ether/emulex_oce/dev/oce/oce_sysctl.c
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121
src/add-ons/kernel/drivers/network/ether/emulex_oce/dev/oce/oce_user.h
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@ -1,121 +0,0 @@
/*-
* Copyright (C) 2013 Emulex
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Emulex Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* Contact Information:
* freebsd-drivers@emulex.com
*
* Emulex
* 3333 Susan Street
* Costa Mesa, CA 92626
*/
/* $FreeBSD: releng/12.0/sys/dev/oce/oce_user.h 306219 2016-09-22 22:51:11Z jpaetzel $ */
struct oce_mbx;
struct oce_softc;
struct mbx_hdr;
enum oce_interrupt_mode {
OCE_INTERRUPT_MODE_MSIX = 0,
OCE_INTERRUPT_MODE_INTX = 1,
OCE_INTERRUPT_MODE_MSI = 2,
};
#define MAX_ROCE_MSIX_VECTORS 16
#define MIN_ROCE_MSIX_VECTORS 1
#define ROCE_MSIX_VECTORS 2
struct oce_dev_info {
device_t dev;
struct ifnet *ifp;
struct oce_softc *softc;
bus_space_handle_t db_bhandle;
bus_space_tag_t db_btag;
uint64_t unmapped_db;
uint32_t unmapped_db_len;
uint32_t db_page_size;
uint64_t dpp_unmapped_addr;
uint32_t dpp_unmapped_len;
uint8_t mac_addr[6];
uint32_t dev_family;
uint16_t vendor_id;
uint16_t dev_id;
enum oce_interrupt_mode intr_mode;
struct {
int num_vectors;
int start_vector;
uint32_t vector_list[MAX_ROCE_MSIX_VECTORS];
} msix;
uint32_t flags;
#define OCE_RDMA_INFO_RDMA_SUPPORTED 0x00000001
};
#define OCE_GEN2_FAMILY 2
#ifdef notdef
struct oce_mbx_ctx {
struct oce_mbx *mbx;
void (*cb) (void *ctx);
void *cb_ctx;
};
#endif
struct oce_mbx_ctx;
typedef struct oce_rdma_info {
int size;
void (*close)(void);
int (*mbox_post)(struct oce_softc *sc,
struct oce_mbx *mbx,
struct oce_mbx_ctx *mbxctx);
void (*common_req_hdr_init)(struct mbx_hdr *hdr,
uint8_t dom,
uint8_t port,
uint8_t subsys,
uint8_t opcode,
uint32_t timeout,
uint32_t pyld_len,
uint8_t version);
void (*get_mac_addr)(struct oce_softc *sc,
uint8_t *macaddr);
} OCE_RDMA_INFO, *POCE_RDMA_INFO;
#define OCE_RDMA_INFO_SIZE (sizeof(OCE_RDMA_INFO))
typedef struct oce_rdma_if {
int size;
int (*announce)(struct oce_dev_info *devinfo);
} OCE_RDMA_IF, *POCE_RDMA_IF;
#define OCE_RDMA_IF_SIZE (sizeof(OCE_RDMA_IF))
int oce_register_rdma(POCE_RDMA_INFO rdma_info, POCE_RDMA_IF rdma_if);

271
src/add-ons/kernel/drivers/network/ether/emulex_oce/dev/oce/oce_util.c
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@ -1,271 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (C) 2013 Emulex
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the Emulex Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* Contact Information:
* freebsd-drivers@emulex.com
*
* Emulex
* 3333 Susan Street
* Costa Mesa, CA 92626
*/
/* $FreeBSD: releng/12.0/sys/dev/oce/oce_util.c 326022 2017-11-20 19:36:21Z pfg $ */
#include "oce_if.h"
static void oce_dma_map_ring(void *arg,
bus_dma_segment_t *segs,
int nseg,
int error);
/**
* @brief Allocate DMA memory
* @param sc software handle to the device
* @param size bus size
* @param dma dma memory area
* @param flags creation flags
* @returns 0 on success, error otherwize
*/
int
oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags)
{
int rc;
memset(dma, 0, sizeof(OCE_DMA_MEM));
rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev),
8, 0,
BUS_SPACE_MAXADDR,
BUS_SPACE_MAXADDR,
NULL, NULL,
size, 1, size, 0, NULL, NULL, &dma->tag);
if (rc == 0) {
rc = bus_dmamem_alloc(dma->tag,
&dma->ptr,
BUS_DMA_NOWAIT | BUS_DMA_COHERENT |
BUS_DMA_ZERO,
&dma->map);
}
dma->paddr = 0;
if (rc == 0) {
rc = bus_dmamap_load(dma->tag,
dma->map,
dma->ptr,
size,
oce_dma_map_addr,
&dma->paddr, flags | BUS_DMA_NOWAIT);
if (dma->paddr == 0)
rc = ENXIO;
}
if (rc != 0)
oce_dma_free(sc, dma);
return rc;
}
/**
* @brief Free DMA memory
* @param sc software handle to the device
* @param dma dma area to free
*/
void
oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma)
{
if (dma->tag == NULL)
return;
if (dma->paddr != 0) {
bus_dmamap_sync(dma->tag, dma->map,
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(dma->tag, dma->map);
dma->paddr = 0;
}
if (dma->ptr != NULL) {
bus_dmamem_free(dma->tag, dma->ptr, dma->map);
dma->ptr = NULL;
}
bus_dma_tag_destroy(dma->tag);
dma->tag = NULL;
return;
}
/**
* @brief Map DMA memory segment addresses
* @param arg physical address pointer
* @param segs dma memory segments
* @param nseg number of dma memory segments
* @param error if error, zeroes the physical address
*/
void
oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error)
{
bus_addr_t *paddr = arg;
if (error)
*paddr = 0;
else
*paddr = segs->ds_addr;
}
/**
* @brief Destroy a ring buffer
* @param sc software handle to the device
* @param ring ring buffer
*/
void
oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring)
{
oce_dma_free(sc, &ring->dma);
free(ring, M_DEVBUF);
}
oce_ring_buffer_t *
oce_create_ring_buffer(POCE_SOFTC sc,
uint32_t q_len, uint32_t item_size)
{
uint32_t size = q_len * item_size;
int rc;
oce_ring_buffer_t *ring;
ring = malloc(sizeof(oce_ring_buffer_t), M_DEVBUF, M_NOWAIT | M_ZERO);
if (ring == NULL)
return NULL;
ring->item_size = item_size;
ring->num_items = q_len;
rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev),
4096, 0,
BUS_SPACE_MAXADDR,
BUS_SPACE_MAXADDR,
NULL, NULL,
size, 8, 4096, 0, NULL, NULL, &ring->dma.tag);
if (rc)
goto fail;
rc = bus_dmamem_alloc(ring->dma.tag,
&ring->dma.ptr,
BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
&ring->dma.map);
if (rc)
goto fail;
bzero(ring->dma.ptr, size);
bus_dmamap_sync(ring->dma.tag, ring->dma.map,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
ring->dma.paddr = 0;
return ring;
fail:
oce_dma_free(sc, &ring->dma);
free(ring, M_DEVBUF);
ring = NULL;
return NULL;
}
struct _oce_dmamap_paddr_table {
uint32_t max_entries;
uint32_t num_entries;
struct phys_addr *paddrs;
};
/**
* @brief Map ring buffer
* @param arg dma map phyical address table pointer
* @param segs dma memory segments
* @param nseg number of dma memory segments
* @param error maps only if error is 0
*/
static void
oce_dma_map_ring(void *arg, bus_dma_segment_t * segs, int nseg, int error)
{
int i;
struct _oce_dmamap_paddr_table *dpt =
(struct _oce_dmamap_paddr_table *)arg;
if (error == 0) {
if (nseg <= dpt->max_entries) {
for (i = 0; i < nseg; i++) {
dpt->paddrs[i].lo = ADDR_LO(segs[i].ds_addr);
dpt->paddrs[i].hi = ADDR_HI(segs[i].ds_addr);
}
dpt->num_entries = nseg;
}
}
}
/**
* @brief Load bus dma map for a ring buffer
* @param ring ring buffer pointer
* @param pa_list physical address list
* @returns number entries
*/
uint32_t
oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list)
{
struct _oce_dmamap_paddr_table dpt;
dpt.max_entries = 8;
dpt.num_entries = 0;
dpt.paddrs = pa_list;
bus_dmamap_load(ring->dma.tag,
ring->dma.map,
ring->dma.ptr,
ring->item_size * ring->num_items,
oce_dma_map_ring, &dpt, BUS_DMA_NOWAIT);
return dpt.num_entries;
}

25
src/add-ons/kernel/drivers/network/ether/emulex_oce/glue.c
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@ -1,25 +0,0 @@
/*
* Copyright 2018, Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#include <sys/bus.h>
#include <sys/kernel.h>
#include <machine/bus.h>
#include <net/if.h>
#include <net/if_media.h>
#include <dev/oce/oce_if.h>
HAIKU_FBSD_DRIVER_GLUE(emulex_oce, oce, pci);
HAIKU_DRIVER_REQUIREMENTS(FBSD_TASKQUEUES | FBSD_SWI_TASKQUEUE);
NO_HAIKU_FBSD_MII_DRIVER();
NO_HAIKU_CHECK_DISABLE_INTERRUPTS();
NO_HAIKU_REENABLE_INTERRUPTS();
HAIKU_FIRMWARE_VERSION(0);
NO_HAIKU_FIRMWARE_NAME_MAP();