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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@21969 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Marcus Overhagen 2007-08-15 21:56:44 +00:00
parent f6ed9e7b0a
commit 07580bfab4
4 changed files with 0 additions and 86 deletions
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1
src/add-ons/kernel/busses/scsi/Jamfile
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SubDir HAIKU_TOP src add-ons kernel busses scsi ;
SubInclude HAIKU_TOP src add-ons kernel busses scsi 53c8xx ;
# SubInclude HAIKU_TOP src add-ons kernel busses scsi ahci ;
SubInclude HAIKU_TOP src add-ons kernel busses scsi buslogic ;
SubInclude HAIKU_TOP src add-ons kernel busses scsi usb ;

5
src/add-ons/kernel/busses/scsi/ahci/Jamfile
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SubDir HAIKU_TOP src add-ons kernel busses scsi ahci ;
KernelAddon ahci_scsi :
ahci_sim.c
;

49
src/add-ons/kernel/busses/scsi/ahci/ahci.h
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/*
* Copyright 2007, Marcus Overhagen. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _AHCI_H
#define _AHCI_H
typedef struct
{
uint32 clb; // Command List Base Address
uint32 clbu; // Command List Base Address Upper 32-Bits
uint32 fb; // FIS Base Address
uint32 fbu; // FIS Base Address Upper 32-Bits
uint32 is; // Interrupt Status
uint32 ie; // Interrupt Enable
uint32 cmd; // Command and Status
uint32 res1; // Reserved
uint32 tfd; // Task File Data
uint32 sig; // Signature
uint32 ssts; // Serial ATA Status (SCR0: SStatus)
uint32 sctl; // Serial ATA Control (SCR2: SControl)
uint32 serr; // Serial ATA Error (SCR1: SError)
uint32 sact; // Serial ATA Active (SCR3: SActive)
uint32 ci; // Command Issue
uint32 sntf; // SNotification
uint32 res2; // Reserved for FIS-based Switching Definition
uint32 res[11]; // Reserved
uint32 vendor[2]; // Vendor Specific
} ahci_port;
typedef struct
{
uint32 cap; // Host Capabilities
uint32 ghc; // Global Host Control
uint32 is; // Interrupt Status
uint32 pi; // Ports Implemented
uint32 vs; // Version
uint32 ccc_ctl; // Command Completion Coalescing Control
uint32 ccc_ports; // Command Completion Coalsecing Ports
uint32 em_loc; // Enclosure Management Location
uint32 em_ctl; // Enclosure Management Control
uint32 res[31]; // Reserved
uint32 vendor[24]; // Vendor Specific registers
ahci_port port[32];
} ahci_hba;
#endif

31
src/add-ons/kernel/busses/scsi/ahci/ahci_sim.c
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/*
* Copyright 2007, Marcus Overhagen. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#define TRACE(a...) dprintf("ahci: " a)
#define FLOW(a...) dprintf("ahci: " a)
#if 0
uint16 vendor_id;
uint16 device_id;
uint8 base_class;
uint8 sub_class;
uint8 class_api;
status_t res;
if (base_class != PCI_mass_storage || sub_class != PCI_sata || class_api != PCI_sata_ahci)
return 0.0f;
TRACE("controller found! vendor 0x%04x, device 0x%04x\n", vendor_id, device_id);
res = pci->find_pci_capability(device, PCI_cap_id_sata, &cap_ofs);
if (res == B_OK) {
uint32 satacr0;
uint32 satacr1;
TRACE("PCI SATA capability found at offset 0x%x\n", cap_ofs);
satacr0 = pci->read_pci_config(device, cap_ofs, 4);
satacr1 = pci->read_pci_config(device, cap_ofs + 4, 4);
TRACE("satacr0 = 0x%08x, satacr1 = 0x%08x\n", satacr0, satacr1);
}
#endif