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- Another patch by Hervé W.

Browse Source 
- Updated code so Processor IDs for older processor do not have to be 
modified.



git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@24979 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Bruno G. Albuquerque 2008-04-15 23:51:17 +00:00
parent bf6f088436
commit 044f45b2db
2 changed files with 61 additions and 61 deletions
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116
headers/os/kernel/OS.h
View File

@ -429,31 +429,31 @@ typedef enum cpu_types {
* the CPUID instruction (Table 4)
* AP-485 Intel - 24161832.pdf
*/
B_CPU_INTEL_x86 = 0x100000,
B_CPU_INTEL_PENTIUM = 0x100501,
B_CPU_INTEL_x86 = 0x1000,
B_CPU_INTEL_PENTIUM = 0x1051,
B_CPU_INTEL_PENTIUM75,
B_CPU_INTEL_PENTIUM_486_OVERDRIVE,
B_CPU_INTEL_PENTIUM_MMX,
B_CPU_INTEL_PENTIUM_MMX_MODEL_4 = B_CPU_INTEL_PENTIUM_MMX,
B_CPU_INTEL_PENTIUM_MMX_MODEL_8 = 0x100508,
B_CPU_INTEL_PENTIUM_MMX_MODEL_8 = 0x1058,
B_CPU_INTEL_PENTIUM75_486_OVERDRIVE,
B_CPU_INTEL_PENTIUM_PRO = 0x100601,
B_CPU_INTEL_PENTIUM_II = 0x100603,
B_CPU_INTEL_PENTIUM_II_MODEL_3 = 0x100603,
B_CPU_INTEL_PENTIUM_II_MODEL_5 = 0x100605,
B_CPU_INTEL_CELERON = 0x100606,
B_CPU_INTEL_CELERON_MODEL_22 = 0x101606,
B_CPU_INTEL_PENTIUM_III = 0x100607,
B_CPU_INTEL_PENTIUM_III_MODEL_8 = 0x100608,
B_CPU_INTEL_PENTIUM_M = 0x100609,
B_CPU_INTEL_PENTIUM_III_XEON = 0x10060a,
B_CPU_INTEL_PENTIUM_III_MODEL_11 = 0x10060b,
B_CPU_INTEL_PENTIUM_M_MODEL_13 = 0x10060d, /* Dothan */
B_CPU_INTEL_PENTIUM_PRO = 0x1061,
B_CPU_INTEL_PENTIUM_II = 0x1063,
B_CPU_INTEL_PENTIUM_II_MODEL_3 = 0x1063,
B_CPU_INTEL_PENTIUM_II_MODEL_5 = 0x1065,
B_CPU_INTEL_CELERON = 0x1066,
B_CPU_INTEL_CELERON_MODEL_22 = 0x11066,
B_CPU_INTEL_PENTIUM_III = 0x1067,
B_CPU_INTEL_PENTIUM_III_MODEL_8 = 0x1068,
B_CPU_INTEL_PENTIUM_M = 0x1069,
B_CPU_INTEL_PENTIUM_III_XEON = 0x106a,
B_CPU_INTEL_PENTIUM_III_MODEL_11 = 0x106b,
B_CPU_INTEL_PENTIUM_M_MODEL_13 = 0x106d, /* Dothan */
B_CPU_INTEL_PENTIUM_CORE,
B_CPU_INTEL_PENTIUM_CORE_2,
B_CPU_INTEL_PENTIUM_CORE_2_EXTREME = 0x101607, /* Core 2 Extreme or Xeon
B_CPU_INTEL_PENTIUM_CORE_2_EXTREME = 0x11067, /* Core 2 Extreme or Xeon
model 23 on 45 nm */
B_CPU_INTEL_PENTIUM_IV = 0x100f00,
B_CPU_INTEL_PENTIUM_IV = 0x10f0,
B_CPU_INTEL_PENTIUM_IV_MODEL_1,
B_CPU_INTEL_PENTIUM_IV_MODEL_2,
B_CPU_INTEL_PENTIUM_IV_MODEL_3,
@ -465,29 +465,29 @@ typedef enum cpu_types {
* (Table 3)
* 20734.pdf
*/
B_CPU_AMD_x86 = 0x110000,
B_CPU_AMD_K5_MODEL_0 = 0x110500,
B_CPU_AMD_x86 = 0x1100,
B_CPU_AMD_K5_MODEL_0 = 0x1150,
B_CPU_AMD_K5_MODEL_1,
B_CPU_AMD_K5_MODEL_2,
B_CPU_AMD_K5_MODEL_3,
B_CPU_AMD_K6_MODEL_6 = 0x110506,
B_CPU_AMD_K6_MODEL_7 = 0x110507,
B_CPU_AMD_K6_MODEL_8 = 0x110508,
B_CPU_AMD_K6_2 = 0x110508,
B_CPU_AMD_K6_MODEL_9 = 0x110509,
B_CPU_AMD_K6_III = 0x110509,
B_CPU_AMD_K6_III_MODEL_13 = 0x11050d,
B_CPU_AMD_K6_MODEL_6 = 0x1156,
B_CPU_AMD_K6_MODEL_7 = 0x1157,
B_CPU_AMD_K6_MODEL_8 = 0x1158,
B_CPU_AMD_K6_2 = 0x1158,
B_CPU_AMD_K6_MODEL_9 = 0x1159,
B_CPU_AMD_K6_III = 0x1159,
B_CPU_AMD_K6_III_MODEL_13 = 0x115d,
B_CPU_AMD_ATHLON_MODEL_1 = 0x110601,
B_CPU_AMD_ATHLON_MODEL_2 = 0x110602,
B_CPU_AMD_DURON = 0x110603,
B_CPU_AMD_ATHLON_THUNDERBIRD = 0x110604,
B_CPU_AMD_ATHLON_XP = 0x110606,
B_CPU_AMD_ATHLON_MODEL_1 = 0x1161,
B_CPU_AMD_ATHLON_MODEL_2 = 0x1162,
B_CPU_AMD_DURON = 0x1163,
B_CPU_AMD_ATHLON_THUNDERBIRD = 0x1164,
B_CPU_AMD_ATHLON_XP = 0x1166,
B_CPU_AMD_ATHLON_XP_MODEL_7,
B_CPU_AMD_ATHLON_XP_MODEL_8,
B_CPU_AMD_ATHLON_XP_MODEL_10 = 0x11060a, /* Barton */
B_CPU_AMD_ATHLON_XP_MODEL_10 = 0x116a, /* Barton */
B_CPU_AMD_SEMPRON_MODEL_8 = B_CPU_AMD_ATHLON_XP_MODEL_8,
B_CPU_AMD_SEMPRON_MODEL_10 = B_CPU_AMD_ATHLON_XP_MODEL_10,
@ -495,48 +495,48 @@ typedef enum cpu_types {
/* According to "Revision guide for AMD Athlon 64
* and AMD Opteron Processors" (25759.pdf)
*/
B_CPU_AMD_ATHLON_64_MODEL_3 = 0x110f03,
B_CPU_AMD_ATHLON_64_MODEL_3 = 0x11f3,
B_CPU_AMD_ATHLON_64_MODEL_4,
B_CPU_AMD_ATHLON_64_MODEL_5,
B_CPU_AMD_OPTERON = B_CPU_AMD_ATHLON_64_MODEL_5,
B_CPU_AMD_ATHLON_64_FX = B_CPU_AMD_ATHLON_64_MODEL_5,
B_CPU_AMD_ATHLON_64_MODEL_7 = 0x110f07,
B_CPU_AMD_ATHLON_64_MODEL_7 = 0x11f7,
B_CPU_AMD_ATHLON_64_MODEL_8,
B_CPU_AMD_ATHLON_64_MODEL_11 = 0x110f0b,
B_CPU_AMD_ATHLON_64_MODEL_11 = 0x11fb,
B_CPU_AMD_ATHLON_64_MODEL_12,
B_CPU_AMD_ATHLON_64_MODEL_14 = 0x110f0e,
B_CPU_AMD_ATHLON_64_MODEL_14 = 0x11fe,
B_CPU_AMD_ATHLON_64_MODEL_15,
B_CPU_AMD_GEODE_LX = 0x11050a,
B_CPU_AMD_GEODE_LX = 0x115a,
/* VIA/Cyrix */
B_CPU_CYRIX_x86 = 0x120000,
B_CPU_VIA_CYRIX_x86 = 0x120000,
B_CPU_CYRIX_GXm = 0x120504,
B_CPU_CYRIX_6x86MX = 0x120600,
B_CPU_CYRIX_x86 = 0x1200,
B_CPU_VIA_CYRIX_x86 = 0x1200,
B_CPU_CYRIX_GXm = 0x1254,
B_CPU_CYRIX_6x86MX = 0x1260,
/* VIA/IDT */
B_CPU_IDT_x86 = 0x130000,
B_CPU_VIA_IDT_x86 = 0x130000,
B_CPU_IDT_WINCHIP_C6 = 0x130504,
B_CPU_IDT_WINCHIP_2 = 0x130508,
B_CPU_IDT_x86 = 0x1300,
B_CPU_VIA_IDT_x86 = 0x1300,
B_CPU_IDT_WINCHIP_C6 = 0x1354,
B_CPU_IDT_WINCHIP_2 = 0x1358,
B_CPU_IDT_WINCHIP_3,
B_CPU_VIA_C3_SAMUEL = 0x130606,
B_CPU_VIA_C3_SAMUEL_2 = 0x130607,
B_CPU_VIA_C3_EZRA_T = 0x130608,
B_CPU_VIA_C3_NEHEMIAH = 0x130609,
B_CPU_VIA_C3_SAMUEL = 0x1366,
B_CPU_VIA_C3_SAMUEL_2 = 0x1367,
B_CPU_VIA_C3_EZRA_T = 0x1368,
B_CPU_VIA_C3_NEHEMIAH = 0x1369,
/* Transmeta */
B_CPU_TRANSMETA_x86 = 0x160000,
B_CPU_TRANSMETA_CRUSOE = 0x160504,
B_CPU_TRANSMETA_x86 = 0x1600,
B_CPU_TRANSMETA_CRUSOE = 0x1654,
/* Rise */
B_CPU_RISE_x86 = 0x140000,
B_CPU_RISE_mP6 = 0x140500,
B_CPU_RISE_x86 = 0x1400,
B_CPU_RISE_mP6 = 0x1450,
/* National Semiconductor */
B_CPU_NATIONAL_x86 = 0x150000,
B_CPU_NATIONAL_GEODE_GX1 = 0x150504,
B_CPU_NATIONAL_x86 = 0x1500,
B_CPU_NATIONAL_GEODE_GX1 = 0x1554,
B_CPU_NATIONAL_GEODE_GX2,
/* For compatibility */
@ -553,7 +553,7 @@ typedef enum cpu_types {
B_CPU_SPARC
} cpu_type;
#define B_CPU_x86_VENDOR_MASK 0xff0000
#define B_CPU_x86_VENDOR_MASK 0xff00
#ifdef __INTEL__
typedef union {

6
src/system/kernel/arch/x86/arch_system_info.c
View File

@ -116,10 +116,10 @@ arch_system_info_init(struct kernel_args *args)
if (base != B_CPU_x86)
if (base == B_CPU_INTEL_x86)
model = (cpu->arch.extended_family + cpu->arch.family << 8) +
(cpu->arch.extended_model << 4) + cpu->arch.model;
model = (cpu->arch.extended_family << 20) + (cpu->arch.extended_model << 16) +
(cpu->arch.family << 4) + cpu->arch.model;
else
model = (cpu->arch.family << 8) +
model = (cpu->arch.family << 4) +
cpu->arch.model;
/* There isn't much useful information yet in the extended
family and extended model fields of AMD processors