* Changed EHCI register access from port to memory mapped io (which is required)
* Added individual register operations for operational and capability registers * Added resetting the host controller which appearantly actually works Note that you shouldn't install the ehci module if you want uhci to work. It disables the companion host controller drivers (uhci and ohci) because it takes port ownership and does not yet give it back for low and fullspeed devices. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@18648 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Michael Lotz
parent
a17c3a48b8
commit
01595708f3
@ -11,6 +11,7 @@
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#include <USB3.h>
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#include <KernelExport.h>
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#define TRACE_USB
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#include "ehci.h"
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pci_module_info *EHCI::sPCIModule = NULL;
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@ -60,8 +61,6 @@ EHCI::EHCI(pci_info *info, Stack *stack)
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fStack(stack),
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fPeriodicFrameListArea(-1),
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fPeriodicFrameList(NULL),
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fAsyncFrameListArea(-1),
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fAsyncFrameList(NULL),
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fFirstTransfer(NULL),
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fLastTransfer(NULL),
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fFinishTransfers(false),
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@ -70,7 +69,7 @@ EHCI::EHCI(pci_info *info, Stack *stack)
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fRootHub(NULL),
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fRootHubAddress(0)
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{
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if (!fInitOK) {
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if (BusManager::InitCheck() < B_OK) {
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TRACE_ERROR(("usb_ehci: bus manager failed to init\n"));
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return;
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}
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@ -78,49 +77,49 @@ EHCI::EHCI(pci_info *info, Stack *stack)
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TRACE(("usb_ehci: constructing new EHCI Host Controller Driver\n"));
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fInitOK = false;
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fRegisterBase = sPCIModule->read_pci_config(fPCIInfo->bus,
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fPCIInfo->device, fPCIInfo->function, PCI_memory_base, 4);
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fRegisterBase &= PCI_address_io_mask;
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TRACE(("usb_ehci: register base: 0x%08x\n", fRegisterBase));
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// enable pci address access
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uint16 command = PCI_command_io | PCI_command_master | PCI_command_memory;
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command |= sPCIModule->read_pci_config(fPCIInfo->bus, fPCIInfo->device,
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fPCIInfo->function, PCI_command, 2);
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sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device,
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fPCIInfo->function, PCI_command, 2, command);
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// make sure we take the controller away from BIOS
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sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 2,
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PCI_LEGSUP, 2, PCI_LEGSUP_USBPIRQDEN);
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// disable interrupts
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WriteReg16(EHCI_USBINTR, 0);
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// enable busmaster and memory mapped access
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uint16 command = sPCIModule->read_pci_config(fPCIInfo->bus,
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fPCIInfo->device, fPCIInfo->function, PCI_command, 2);
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command &= ~PCI_command_io;
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command |= PCI_command_master | PCI_command_memory;
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// reset the host controller
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// ToDo...
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sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device,
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fPCIInfo->function, PCI_command, 2, command);
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// allocate the periodic frame list
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void *physicalAddress;
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fPeriodicFrameListArea = fStack->AllocateArea((void **)&fPeriodicFrameList,
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&physicalAddress, B_PAGE_SIZE, "USB EHCI Periodic Framelist");
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if (fPeriodicFrameListArea < B_OK) {
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TRACE_ERROR(("usb_ehci: unable to allocate periodic framelist\n"));
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// map the registers
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uint32 offset = fPCIInfo->u.h0.base_registers[0] & (B_PAGE_SIZE - 1);
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addr_t physicalAddress = fPCIInfo->u.h0.base_registers[0] - offset;
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size_t mapSize = (fPCIInfo->u.h0.base_register_sizes[0] + offset
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+ B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1);
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TRACE(("usb_ehci: map physical memory 0x%08x (base: 0x%08x; offset: %x); size: %d -> %d\n", fPCIInfo->u.h0.base_registers[0], physicalAddress, offset, fPCIInfo->u.h0.base_register_sizes[0], mapSize));
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fRegisterArea = map_physical_memory("EHCI memory mapped registers",
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(void *)physicalAddress, mapSize, B_ANY_KERNEL_BLOCK_ADDRESS,
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B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA | B_READ_AREA | B_WRITE_AREA,
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(void **)&fCapabilityRegisters);
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if (fRegisterArea < B_OK) {
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TRACE(("usb_ehci: failed to map register memory\n"));
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return;
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}
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WriteReg32(EHCI_PERIODICLISTBASE, (uint32)physicalAddress);
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fCapabilityRegisters += offset;
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fOperationalRegisters = fCapabilityRegisters + ReadCapReg8(EHCI_CAPLENGTH);
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TRACE(("usb_ehci: mapped capability registers: 0x%08x\n", fCapabilityRegisters));
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TRACE(("usb_ehci: mapped operational registers: 0x%08x\n", fOperationalRegisters));
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// allocate the async frame list
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fAsyncFrameListArea = fStack->AllocateArea((void **)&fAsyncFrameList,
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&physicalAddress, B_PAGE_SIZE, "USB EHCI Async Framelist");
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if (fAsyncFrameListArea < B_OK) {
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TRACE_ERROR(("usb_ehci: unable to allocate async framelist\n"));
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// disable interrupts
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WriteOpReg(EHCI_USBINTR, 0);
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// reset the host controller
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if (ControllerReset() < B_OK) {
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TRACE_ERROR(("usb_ehci: host controller failed to reset\n"));
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return;
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}
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WriteReg32(EHCI_ASYNCLISTADDR, (uint32)physicalAddress);
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// create finisher service thread
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fFinishThread = spawn_kernel_thread(FinishThread, "ehci finish thread",
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B_NORMAL_PRIORITY, (void *)this);
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@ -129,9 +128,26 @@ EHCI::EHCI(pci_info *info, Stack *stack)
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// install the interrupt handler and enable interrupts
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install_io_interrupt_handler(fPCIInfo->u.h0.interrupt_line,
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InterruptHandler, (void *)this, 0);
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WriteReg16(EHCI_USBINTR, EHCI_USBINTR_HOSTSYSERR
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WriteOpReg(EHCI_USBINTR, EHCI_USBINTR_HOSTSYSERR
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| EHCI_USBINTR_USBERRINT | EHCI_USBINTR_USBINT);
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// allocate the periodic frame list
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fPeriodicFrameListArea = fStack->AllocateArea((void **)&fPeriodicFrameList,
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(void **)&physicalAddress, B_PAGE_SIZE, "USB EHCI Periodic Framelist");
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if (fPeriodicFrameListArea < B_OK) {
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TRACE_ERROR(("usb_ehci: unable to allocate periodic framelist\n"));
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return;
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}
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// terminate all elements
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for (int32 i = 0; i < 1024; i++)
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fPeriodicFrameList[i] = EHCI_PFRAMELIST_TERM;
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WriteOpReg(EHCI_PERIODICLISTBASE, (uint32)physicalAddress);
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// route all ports to us
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WriteOpReg(EHCI_CONFIGFLAG, EHCI_CONFIGFLAG_FLAG);
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TRACE(("usb_ehci: EHCI Host Controller Driver constructed\n"));
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fInitOK = true;
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}
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@ -149,8 +165,7 @@ EHCI::~EHCI()
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delete fRootHub;
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delete_area(fPeriodicFrameListArea);
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delete_area(fAsyncFrameListArea);
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delete_area(fRegisterArea);
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put_module(B_PCI_MODULE_NAME);
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}
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@ -159,13 +174,13 @@ status_t
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EHCI::Start()
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{
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TRACE(("usb_ehci: starting EHCI Host Controller\n"));
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TRACE(("usb_ehci: usbcmd: 0x%08x; usbsts: 0x%08x\n", ReadReg32(EHCI_USBCMD), ReadReg32(EHCI_USBSTS)));
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TRACE(("usb_ehci: usbcmd: 0x%08x; usbsts: 0x%08x\n", ReadOpReg(EHCI_USBCMD), ReadOpReg(EHCI_USBSTS)));
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WriteReg32(EHCI_USBCMD, ReadReg32(EHCI_USBCMD) | EHCI_USBCMD_RUNSTOP);
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WriteOpReg(EHCI_USBCMD, ReadOpReg(EHCI_USBCMD) | EHCI_USBCMD_RUNSTOP);
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bool running = false;
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for (int32 i = 0; i < 10; i++) {
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uint32 status = ReadReg32(EHCI_USBSTS);
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uint32 status = ReadOpReg(EHCI_USBSTS);
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TRACE(("usb_ehci: try %ld: status 0x%08x\n", i, status));
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if (status & EHCI_USBSTS_HCHALTED) {
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@ -295,7 +310,16 @@ EHCI::ResetPort(int32 index)
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status_t
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EHCI::ControllerReset()
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{
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return B_ERROR;
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WriteOpReg(EHCI_USBCMD, EHCI_USBCMD_HCRESET);
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int32 tries = 5;
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while (ReadOpReg(EHCI_USBCMD) & EHCI_USBCMD_HCRESET) {
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snooze(10000);
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if (tries-- < 0)
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return B_ERROR;
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}
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return B_OK;
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}
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@ -534,42 +558,35 @@ EHCI::ReadActualLength(ehci_qtd *topDescriptor, uint8 *lastDataToggle)
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inline void
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EHCI::WriteReg8(uint32 reg, uint8 value)
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EHCI::WriteOpReg(uint32 reg, uint32 value)
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{
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sPCIModule->write_io_8(fRegisterBase + reg, value);
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}
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inline void
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EHCI::WriteReg16(uint32 reg, uint16 value)
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{
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sPCIModule->write_io_16(fRegisterBase + reg, value);
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}
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inline void
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EHCI::WriteReg32(uint32 reg, uint32 value)
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{
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sPCIModule->write_io_32(fRegisterBase + reg, value);
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}
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inline uint8
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EHCI::ReadReg8(uint32 reg)
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{
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return sPCIModule->read_io_8(fRegisterBase + reg);
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}
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inline uint16
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EHCI::ReadReg16(uint32 reg)
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{
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return sPCIModule->read_io_16(fRegisterBase + reg);
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*(volatile uint32 *)(fOperationalRegisters + reg) = value;
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}
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inline uint32
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EHCI::ReadReg32(uint32 reg)
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EHCI::ReadOpReg(uint32 reg)
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{
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return sPCIModule->read_io_32(fRegisterBase + reg);
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return *(volatile uint32 *)(fOperationalRegisters + reg);
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}
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inline uint8
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EHCI::ReadCapReg8(uint32 reg)
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{
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return *(volatile uint8 *)(fCapabilityRegisters + reg);
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}
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inline uint16
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EHCI::ReadCapReg16(uint32 reg)
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{
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return *(volatile uint16 *)(fCapabilityRegisters + reg);
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}
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inline uint32
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EHCI::ReadCapReg32(uint32 reg)
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{
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return *(volatile uint32 *)(fCapabilityRegisters + reg);
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}
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@ -87,25 +87,26 @@ static int32 FinishThread(void *data);
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size_t ReadActualLength(ehci_qtd *topDescriptor,
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uint8 *lastDataToggle);
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// Register functions
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inline void WriteReg8(uint32 reg, uint8 value);
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inline void WriteReg16(uint32 reg, uint16 value);
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inline void WriteReg32(uint32 reg, uint32 value);
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inline uint8 ReadReg8(uint32 reg);
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inline uint16 ReadReg16(uint32 reg);
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inline uint32 ReadReg32(uint32 reg);
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// Operational register functions
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inline void WriteOpReg(uint32 reg, uint32 value);
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inline uint32 ReadOpReg(uint32 reg);
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// Capability register functions
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inline uint8 ReadCapReg8(uint32 reg);
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inline uint16 ReadCapReg16(uint32 reg);
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inline uint32 ReadCapReg32(uint32 reg);
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static pci_module_info *sPCIModule;
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uint32 fRegisterBase;
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uint8 *fCapabilityRegisters;
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uint8 *fOperationalRegisters;
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area_id fRegisterArea;
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pci_info *fPCIInfo;
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Stack *fStack;
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// Framelist memory
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area_id fPeriodicFrameListArea;
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addr_t *fPeriodicFrameList;
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area_id fAsyncFrameListArea;
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addr_t *fAsyncFrameList;
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// Maintain a linked list of transfers
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transfer_data *fFirstTransfer;
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@ -9,6 +9,14 @@
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#ifndef EHCI_HARDWARE_H
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#define EHCI_HARDWARE_H
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// Host Controller Capability Registers (EHCI Spec 2.2)
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#define EHCI_CAPLENGTH 0x00 // Capability Register Length
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#define EHCI_HCIVERSION 0x02 // Interface Version Number
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#define EHCI_HCSPARAMS 0x04 // Structural Parameters
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#define EHCI_HCCPARAMS 0x08 // Capability Parameters
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#define EHCI_HCSP_PORTROUTE 0x0c // Companion Port Route Description
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// Host Controller Operational Registers (EHCI Spec 2.3)
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#define EHCI_USBCMD 0x00 // USB Command
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#define EHCI_USBSTS 0x04 // USB Status
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@ -88,16 +96,17 @@
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// PCI Registers
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#define PCI_LEGSUP 0xc0 // PCI Legacy Support
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#define PCI_LEGSUP_USBPIRQDEN 0x2000 // USBP IRQ Deny
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#define PCI_LEGSUP_USBPIRQDEN 0x2000 // USB PIRQ
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// Data Structures (EHCI Spec 3)
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// Periodic Frame List Element Flags (EHCI Spec 3.1)
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#define EHCI_PFRAMELIST_ITD 0x00 // Isochronous Transfer Descriptor
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#define EHCI_PFRAMELIST_QH 0x01 // Queue Head
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#define EHCI_PFRAMELIST_SITD 0x10 // Split Transaction Isochronous TD
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#define EHCI_PFRAMELIST_FSTN 0x11 // Frame Span Traversal Node
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#define EHCI_PFRAMELIST_TERM (1 << 0) // Terminate
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#define EHCI_PFRAMELIST_ITD (0 << 1) // Isochronous Transfer Descriptor
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#define EHCI_PFRAMELIST_QH (1 << 1) // Queue Head
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#define EHCI_PFRAMELIST_SITD (2 << 1) // Split Transaction Isochronous TD
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#define EHCI_PFRAMELIST_FSTN (3 << 1) // Frame Span Traversal Node
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// ToDo: Isochronous (High-Speed) Transfer Descriptors (iTD, EHCI Spec 3.2)
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@ -339,10 +339,12 @@ UHCI::UHCI(pci_info *info, Stack *stack)
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fRegisterBase = sPCIModule->read_pci_config(fPCIInfo->bus,
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fPCIInfo->device, fPCIInfo->function, PCI_memory_base, 4);
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fRegisterBase &= PCI_address_io_mask;
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TRACE(("usb_uhci: iospace offset: 0x%08x\n", fRegisterBase));
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TRACE_ERROR(("usb_uhci: iospace offset: 0x%08x\n", fRegisterBase));
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//fRegisterBase = fPCIInfo->u.h0.base_registers[0];
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//TRACE(("usb_uhci: register base: 0x%08x\n", fRegisterBase));
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if (fRegisterBase == 0) {
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fRegisterBase = fPCIInfo->u.h0.base_registers[0];
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TRACE_ERROR(("usb_uhci: register base: 0x%08x\n", fRegisterBase));
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}
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// enable pci address access
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uint16 command = PCI_command_io | PCI_command_master | PCI_command_memory;
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