75 lines
1.9 KiB
C
75 lines
1.9 KiB
C
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/*
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* Copyright 2005, Ingo Weinhold, bonefish@users.sf.net.
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* Distributed under the terms of the MIT License.
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*/
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#ifndef _KERNEL_ARCH_X86_USER_DEBUGGER_H
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#define _KERNEL_ARCH_X86_USER_DEBUGGER_H
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// number of breakpoints the CPU supports
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enum {
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X86_BREAKPOINT_COUNT = 4,
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};
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// debug control register DR7 layout:
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// 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
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// LEN3 R/W3 LEN2 R/W2 LEN1 R/W1 LEN0 R/W0
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//
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// 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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// 0 0 GD 0 0 1 GE LE G3 L3 G2 L2 G1 L1 G0 L0
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//
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enum {
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X86_DR7_LEN3_LSB = 30, // breakpoints len and type
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X86_DR7_RW3_LSB = 28, //
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X86_DR7_LEN2_LSB = 26, //
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X86_DR7_RW2_LSB = 24, //
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X86_DR7_LEN1_LSB = 22, //
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X86_DR7_RW1_LSB = 20, //
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X86_DR7_LEN0_LSB = 18, //
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X86_DR7_RW0_LSB = 16, //
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X86_DR7_GD = 13, // general detect enable: disallows debug
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// register access
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X86_DR7_GE = 9, // global/local exact breakpoint
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X86_DR7_LE = 8, //
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X86_DR7_G3 = 7, // global/local breakpoints enable
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X86_DR7_L3 = 6, //
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X86_DR7_G2 = 5, //
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X86_DR7_L2 = 4, //
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X86_DR7_G1 = 3, //
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X86_DR7_L1 = 2, //
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X86_DR7_G0 = 1, //
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X86_DR7_L0 = 0, //
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X86_BREAKPOINTS_DISABLED_DR7
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= (1 << 10) | (1 << X86_DR7_GE) | (1 << X86_DR7_LE),
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// all breakpoints disabled
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};
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// x86 breakpoint types
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enum {
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X86_INSTRUCTION_BREAKPOINT = 0x0,
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X86_DATA_WRITE_BREAKPOINT = 0x1,
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X86_IO_READ_WRITE_BREAKPOINT = 0x2, // >= 586
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X86_DATA_READ_WRITE_BREAKPOINT = 0x3,
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};
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// x86 breakpoint lengths
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enum {
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X86_BREAKPOINT_LENGTH_1 = 0x0,
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X86_BREAKPOINT_LENGTH_2 = 0x1,
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X86_BREAKPOINT_LENGTH_4 = 0x3,
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};
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struct arch_breakpoint {
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void *address; // NULL, if deactivated
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uint32 type; // one of the architecture types above
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uint32 length; // one of the length values above
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};
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struct arch_team_debug_info {
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struct arch_breakpoint breakpoints[X86_BREAKPOINT_COUNT];
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uint32 dr7; // debug control register DR7
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};
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#endif // _KERNEL_ARCH_X86_USER_DEBUGGER_H
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