2009-07-27 20:23:08 +04:00
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/*
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* Copyright (c) 2008 Travis Geiselbrecht
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __PLATFORM_OMAP3_H
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#define __PLATFORM_OMAP3_H
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#define SDRAM_BASE 0x80000000
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2010-06-30 21:25:08 +04:00
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#define VECT_BASE 0x00000000
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#define VECT_SIZE 0x1000
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#define DEVICE_BASE 0x48000000
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#define DEVICE_SIZE 0x2000000
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/* framebuffer */
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#define FB_BASE 0x88000000
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#define FB_SIZE 0x200000
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2009-07-27 20:23:08 +04:00
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#define L4_BASE 0x48000000
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#define L4_WKUP_BASE 0x48300000
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#define L4_PER_BASE 0x49000000
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#define L4_EMU_BASE 0x54000000
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#define GFX_BASE 0x50000000
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#define L3_BASE 0x68000000
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#define SMS_BASE 0x6C000000
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#define SDRC_BASE 0x6D000000
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#define GPMC_BASE 0x6E000000
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#define SCM_BASE 0x48002000
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/* clocks */
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#define CM_CLKSEL_PER (L4_BASE + 0x5040)
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/* PRCM */
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#define CM_FCLKEN_IVA2 (L4_BASE + 0x4000)
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#define CM_CLKEN_PLL_IVA2 (L4_BASE + 0x4004)
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#define CM_IDLEST_PLL_IVA2 (L4_BASE + 0x4024)
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#define CM_CLKSEL1_PLL_IVA2 (L4_BASE + 0x4040)
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#define CM_CLKSEL2_PLL_IVA2 (L4_BASE + 0x4044)
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#define CM_CLKEN_PLL_MPU (L4_BASE + 0x4904)
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#define CM_IDLEST_PLL_MPU (L4_BASE + 0x4924)
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#define CM_CLKSEL1_PLL_MPU (L4_BASE + 0x4940)
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#define CM_CLKSEL2_PLL_MPU (L4_BASE + 0x4944)
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#define CM_FCLKEN1_CORE (L4_BASE + 0x4a00)
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#define CM_ICLKEN1_CORE (L4_BASE + 0x4a10)
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#define CM_ICLKEN2_CORE (L4_BASE + 0x4a14)
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#define CM_CLKSEL_CORE (L4_BASE + 0x4a40)
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#define CM_FCLKEN_GFX (L4_BASE + 0x4b00)
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#define CM_ICLKEN_GFX (L4_BASE + 0x4b10)
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#define CM_CLKSEL_GFX (L4_BASE + 0x4b40)
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#define CM_FCLKEN_WKUP (L4_BASE + 0x4c00)
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#define CM_ICLKEN_WKUP (L4_BASE + 0x4c10)
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#define CM_CLKSEL_WKUP (L4_BASE + 0x4c40)
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#define CM_IDLEST_WKUP (L4_BASE + 0x4c20)
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#define CM_CLKEN_PLL (L4_BASE + 0x4d00)
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#define CM_IDLEST_CKGEN (L4_BASE + 0x4d20)
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#define CM_CLKSEL1_PLL (L4_BASE + 0x4d40)
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#define CM_CLKSEL2_PLL (L4_BASE + 0x4d44)
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#define CM_CLKSEL3_PLL (L4_BASE + 0x4d48)
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#define CM_FCLKEN_DSS (L4_BASE + 0x4e00)
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#define CM_ICLKEN_DSS (L4_BASE + 0x4e10)
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#define CM_CLKSEL_DSS (L4_BASE + 0x4e40)
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#define CM_FCLKEN_CAM (L4_BASE + 0x4f00)
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#define CM_ICLKEN_CAM (L4_BASE + 0x4f10)
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#define CM_CLKSEL_CAM (L4_BASE + 0x4F40)
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#define CM_FCLKEN_PER (L4_BASE + 0x5000)
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#define CM_ICLKEN_PER (L4_BASE + 0x5010)
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#define CM_CLKSEL_PER (L4_BASE + 0x5040)
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#define CM_CLKSEL1_EMU (L4_BASE + 0x5140)
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#define PRM_CLKSEL (L4_BASE + 0x306d40)
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#define PRM_RSTCTRL (L4_BASE + 0x307250)
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#define PRM_CLKSRC_CTRL (L4_BASE + 0x307270)
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/* General Purpose Timers */
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#define OMAP34XX_GPT1 (L4_BASE + 0x318000)
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#define OMAP34XX_GPT2 (L4_BASE + 0x1032000)
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#define OMAP34XX_GPT3 (L4_BASE + 0x1034000)
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#define OMAP34XX_GPT4 (L4_BASE + 0x1036000)
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#define OMAP34XX_GPT5 (L4_BASE + 0x1038000)
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#define OMAP34XX_GPT6 (L4_BASE + 0x103A000)
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#define OMAP34XX_GPT7 (L4_BASE + 0x103C000)
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#define OMAP34XX_GPT8 (L4_BASE + 0x103E000)
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#define OMAP34XX_GPT9 (L4_BASE + 0x1040000)
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#define OMAP34XX_GPT10 (L4_BASE + 0x86000)
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#define OMAP34XX_GPT11 (L4_BASE + 0x88000)
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#define OMAP34XX_GPT12 (L4_BASE + 0x304000)
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#define TIDR 0x00
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#define TIOCP_CFG 0x10
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#define TISTAT 0x14
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#define TISR 0x18
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#define TIER 0x1C
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#define TWER 0x20
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#define TCLR 0x24
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#define TCRR 0x28
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#define TLDR 0x2C
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#define TTGR 0x30
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#define TWPS 0x34
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#define TMAR 0x38
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#define TCAR1 0x3C
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#define TSICR 0x40
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#define TCAR2 0x44
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#define TPIR 0x48
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#define TNIR 0x4C
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#define TCVR 0x50
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#define TOCR 0x54
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#define TOWR 0x58
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/* WatchDog Timers (1 secure, 3 GP) */
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#define WD1_BASE (0x4830C000)
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#define WD2_BASE (0x48314000)
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#define WD3_BASE (0x49030000)
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#define WIDR 0x00
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#define WD_SYSCONFIG 0x10
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#define WD_SYSSTATUS 0x14
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#define WISR 0x18
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#define WIER 0x1C
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#define WCLR 0x24
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#define WCRR 0x28
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#define WLDR 0x2C
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#define WTGR 0x30
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#define WWPS 0x34
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#define WSPR 0x48
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#define W_PEND_WCLR (1<<0)
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#define W_PEND_WCRR (1<<1)
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#define W_PEND_WLDR (1<<2)
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#define W_PEND_WTGR (1<<3)
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#define W_PEND_WSPR (1<<4)
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#define WD_UNLOCK1 0xAAAA
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#define WD_UNLOCK2 0x5555
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/* 32KTIMER */
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#define TIMER32K_BASE (L4_BASE + 0x320000)
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#define TIMER32K_REV (TIMER32K_BASE + 0x00)
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#define TIMER32K_CR (TIMER32K_BASE + 0x10)
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/* UART */
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#define OMAP_UART1_BASE (L4_BASE + 0x6a000)
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#define OMAP_UART2_BASE (L4_BASE + 0x6c000)
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#define OMAP_UART3_BASE (L4_BASE + 0x01020000)
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#define UART_RHR 0
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#define UART_THR 0
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#define UART_DLL 0
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#define UART_IER 1
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#define UART_DLH 1
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#define UART_IIR 2
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#define UART_FCR 2
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#define UART_EFR 2
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#define UART_LCR 3
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#define UART_MCR 4
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#define UART_LSR 5
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#define UART_MSR 6
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#define UART_TCR 6
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#define UART_SPR 7
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#define UART_TLR 7
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#define UART_MDR1 8
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#define UART_MDR2 9
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#define UART_SFLSR 10
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#define UART_RESUME 11
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#define UART_TXFLL 10
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#define UART_TXFLH 11
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#define UART_SFREGL 12
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#define UART_SFREGH 13
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#define UART_RXFLL 12
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#define UART_RXFLH 13
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#define UART_BLR 14
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#define UART_UASR 14
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#define UART_ACREG 15
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#define UART_SCR 16
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#define UART_SSR 17
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#define UART_EBLR 18
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#define UART_MVR 19
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#define UART_SYSC 20
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/* MPU INTC */
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#define INTC_BASE (L4_BASE + 0x200000)
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#define INTC_REVISION (INTC_BASE + 0x000)
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#define INTC_SYSCONFIG (INTC_BASE + 0x010)
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#define INTC_SYSSTATUS (INTC_BASE + 0x014)
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#define INTC_SIR_IRQ (INTC_BASE + 0x040)
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#define INTC_SIR_FIQ (INTC_BASE + 0x044)
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#define INTC_CONTROL (INTC_BASE + 0x048)
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#define INTC_PROTECTION (INTC_BASE + 0x04C)
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#define INTC_IDLE (INTC_BASE + 0x050)
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#define INTC_IRQ_PRIORITY (INTC_BASE + 0x060)
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#define INTC_FIQ_PRIORITY (INTC_BASE + 0x064)
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#define INTC_THRESHOLD (INTC_BASE + 0x068)
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#define INTC_ITR(n) (INTC_BASE + 0x080 + (n) * 0x20)
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#define INTC_MIR(n) (INTC_BASE + 0x084 + (n) * 0x20)
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#define INTC_MIR_CLEAR(n) (INTC_BASE + 0x088 + (n) * 0x20)
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#define INTC_MIR_SET(n) (INTC_BASE + 0x08C + (n) * 0x20)
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#define INTC_ISR_SET(n) (INTC_BASE + 0x090 + (n) * 0x20)
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#define INTC_ISR_CLEAR(n) (INTC_BASE + 0x094 + (n) * 0x20)
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#define INTC_PENDING_IRQ(n) (INTC_BASE + 0x098 + (n) * 0x20)
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#define INTC_PENDING_FIQ(n) (INTC_BASE + 0x09C + (n) * 0x20)
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#define INTC_ILR(n) (INTC_BASE + 0x100 + (n) * 4)
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/* interrupts */
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#define INT_VECTORS 96
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#define GPT2_IRQ 38
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/* HS USB */
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#define USB_HS_BASE (L4_BASE + 0xab000)
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/* USB OTG */
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#define OTG_BASE (L4_BASE + 0xab400)
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#define OTG_REVISION (OTG_BASE + 0x00)
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#define OTG_SYSCONFIG (OTG_BASE + 0x04)
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#define OTG_SYSSTATUS (OTG_BASE + 0x08)
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#define OTG_INTERFSEL (OTG_BASE + 0x0C)
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#define OTG_SIMENABLE (OTG_BASE + 0x10)
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#define OTG_FORCESTDBY (OTG_BASE + 0x14)
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/* I2C */
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#define I2C1_BASE (L4_BASE + 0x70000)
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#define I2C2_BASE (L4_BASE + 0x72000)
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#define I2C3_BASE (L4_BASE + 0x60000)
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#define I2C_REV (0x00)
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#define I2C_IE (0x04)
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#define I2C_STAT (0x08)
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#define I2C_WE (0x0C)
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#define I2C_SYSS (0x10)
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#define I2C_BUF (0x14)
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#define I2C_CNT (0x18)
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#define I2C_DATA (0x1C)
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#define I2C_SYSC (0x20)
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#define I2C_CON (0x24)
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#define I2C_OA0 (0x28)
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#define I2C_SA (0x2C)
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#define I2C_PSC (0x30)
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#define I2C_SCLL (0x34)
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#define I2C_SCLH (0x38)
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#define I2C_SYSTEST (0x3C)
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#define I2C_BUFSTAT (0x40)
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#define I2C_OA1 (0x44)
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#define I2C_OA2 (0x48)
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#define I2C_OA3 (0x4C)
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#define I2C_ACTOA (0x50)
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#define I2C_SBLOCK (0x54)
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2010-06-30 21:39:36 +04:00
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/* GPIO */
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#define GPIO1_BASE 0x48310000
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#define GPIO2_BASE 0x49050000
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#define GPIO3_BASE 0x49052000
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#define GPIO4_BASE 0x49054000
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#define GPIO5_BASE 0x49056000
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#define GPIO6_BASE 0x49058000
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/* (incomplete) */
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#define GPIO_OE 0x034
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#define GPIO_DATAIN 0x038
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#define GPIO_DATAOUT 0x03C
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#define GPIO_SETDATAOUT 0x094
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2009-07-27 20:23:08 +04:00
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#endif
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