287 lines
10 KiB
C
287 lines
10 KiB
C
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/* MGA registers definitions and macros for access to */
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/* apsed : merged mga_macro.h and mga_regs.c with #define for speed */
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/* PCI_config_space */
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#define MGACFG_DEVID 0x00
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#define MGACFG_DEVCTRL 0x04
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#define MGACFG_CLASS 0x08
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#define MGACFG_HEADER 0x0c
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#define MGACFG_MGABASE2 0x10
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#define MGACFG_MGABASE1 0x14
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#define MGACFG_MGABASE3 0x18 // >= MYST
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#define MGACFG_SUBSYSIDR 0x2c // >= MYST
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#define MGACFG_ROMBASE 0x30
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#define MGACFG_CAP_PTR 0x34 // >= MIL2
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#define MGACFG_INTCTRL 0x3c
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#define MGACFG_OPTION 0x40
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#define MGACFG_MGA_INDEX 0x44
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#define MGACFG_MGA_DATA 0x48
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#define MGACFG_SUBSYSIDW 0x4c // >= MYST
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#define MGACFG_OPTION2 0x50 // >= G100
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#define MGACFG_OPTION3 0x54 // >= G400
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#define MGACFG_OPTION4 0x58 // >= G400
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#define MGACFG_PM_IDENT 0xdc // >= G100
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#define MGACFG_PM_CSR 0xe0 // >= G100
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#define MGACFG_AGP_IDENT 0xf0 // >= MIL2
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#define MGACFG_AGP_STS 0xf4 // >= MIL2
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#define MGACFG_AGP_CMD 0xf8 // >= MIL2
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/*VGA registers - these are byte wide*/
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#define MGAVGA_ATTR_I 0x1FC0 // apsed as SEQ
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#define MGAVGA_ATTR_D 0x1FC1 // apsed as SEQ
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#define MGAVGA_MISCW 0x1FC2
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#define MGAVGA_SEQ_I 0x1FC4
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#define MGAVGA_SEQ_D 0x1FC5
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#define MGAVGA_DACSTAT 0x1FC7
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#define MGAVGA_FEATR 0x1FCA
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#define MGAVGA_MISCR 0x1FCC
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#define MGAVGA_GCTL_I 0x1FCE
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#define MGAVGA_GCTL_D 0x1FCF
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#define MGAVGA_CRTC_I 0x1FD4
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#define MGAVGA_CRTC_D 0x1FD5
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#define MGAVGA_INSTS1 0x1FDA
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#define MGAVGA_FEATW 0x1FDA
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#define MGAVGA_CRTCEXT_I 0x1FDE
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#define MGAVGA_CRTCEXT_D 0x1FDF
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/*DAC registers (>= g100) */
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#define MGADAC_PALWTADD 0x3C00
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#define MGADAC_PALDATA 0x3C01
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#define MGADAC_PIXRDMSK 0x3C02
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#define MGADAC_PALRDADD 0x3C03
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#define MGADAC_X_DATAREG 0x3C0A
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#define MGADAC_CURSPOSXL 0x3C0C
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#define MGADAC_CURSPOSXH 0x3C0D
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#define MGADAC_CURSPOSYL 0x3C0E
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#define MGADAC_CURSPOSYH 0x3C0F
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/*(D)AC (X) (I)ndexed registers (>= g100) */
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#define MGADXI_CURADDL 0x04
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#define MGADXI_CURADDH 0x05
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#define MGADXI_CURCTRL 0x06
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#define MGADXI_CURCOL0RED 0x08
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#define MGADXI_CURCOL0GREEN 0x09
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#define MGADXI_CURCOL0BLUE 0x0A
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#define MGADXI_CURCOL1RED 0x0C
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#define MGADXI_CURCOL1GREEN 0x0D
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#define MGADXI_CURCOL1BLUE 0x0E
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#define MGADXI_CURCOL2RED 0x10
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#define MGADXI_CURCOL2GREEN 0x11
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#define MGADXI_CURCOL2BLUE 0x12
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#define MGADXI_VREFCTRL 0x18
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#define MGADXI_MULCTRL 0x19
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#define MGADXI_PIXCLKCTRL 0x1A
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#define MGADXI_GENCTRL 0x1D
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#define MGADXI_MISCCTRL 0x1E
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#define MGADXI_PANELMODE 0x1F
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#define MGADXI_MAFCDEL 0x20
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#define MGADXI_GENIOCTRL 0x2A
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#define MGADXI_GENIODATA 0x2B
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#define MGADXI_SYSPLLM 0x2C
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#define MGADXI_SYSPLLN 0x2D
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#define MGADXI_SYSPLLP 0x2E
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#define MGADXI_SYSPLLSTAT 0x2F
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#define MGADXI_ZOOMCTRL 0x38
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#define MGADXI_SENSETEST 0x3A
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#define MGADXI_CRCREML 0x3C
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#define MGADXI_CRCREMH 0x3D
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#define MGADXI_CRCBITSEL 0x3E
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#define MGADXI_COLMSK 0x40
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#define MGADXI_COLKEY 0x42
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#define MGADXI_PIXPLLAM 0x44
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#define MGADXI_PIXPLLAN 0x45
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#define MGADXI_PIXPLLAP 0x46
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#define MGADXI_PIXPLLBM 0x48
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#define MGADXI_PIXPLLBN 0x49
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#define MGADXI_PIXPLLBP 0x4A
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#define MGADXI_PIXPLLCM 0x4C
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#define MGADXI_PIXPLLCN 0x4D
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#define MGADXI_PIXPLLCP 0x4E
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#define MGADXI_PIXPLLSTAT 0x4F
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#define MGADXI_CURCOLEXT 0x60 /*sequential from CURCOL3->15, RGB*/
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//rudolf: missing registers!
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/*(D)AC (X) (I)ndexed registers (>= g200) */
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#define MGADXI_KEYOPMODE 0x51
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#define MGADXI_COLMSK0RED 0x52
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#define MGADXI_COLMSK0GREEN 0x53
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#define MGADXI_COLMSK0BLUE 0x54
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#define MGADXI_COLKEY0RED 0x55
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#define MGADXI_COLKEY0GREEN 0x56
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#define MGADXI_COLKEY0BLUE 0x57
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/*MGA 1st CRTC registers */
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#define MGACR1_VCOUNT 0x1E20
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//end rudolf.
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/*MGA 2nd CRTC registers >= ?? TODO */
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#define MGACR2_CTL 0x3C10
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#define MGACR2_HPARAM 0x3C14
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#define MGACR2_HSYNC 0x3C18
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#define MGACR2_VPARAM 0x3C1C
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#define MGACR2_VSYNC 0x3C20
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#define MGACR2_PRELOAD 0x3C24
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#define MGACR2_STARTADD0 0x3C28
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#define MGACR2_OFFSET 0x3C40
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#define MGACR2_MISC 0x3C44
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#define MGACR2_VCOUNT 0x3C48
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#define MGACR2_DATACTL 0x3C4C
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/*MGA ACCeleration registers*/
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#define MGAACC_DWGCTL 0x1C00
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#define MGAACC_MACCESS 0x1C04
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#define MGAACC_MCTLWTST 0x1C08
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#define MGAACC_ZORG 0x1C0C
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#define MGAACC_PLNWT 0x1C1C
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#define MGAACC_BCOL 0x1C20
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#define MGAACC_FCOL 0x1C24
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#define MGAACC_XYSTRT 0x1C40
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#define MGAACC_XYEND 0x1C44
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#define MGAACC_SGN 0x1C58
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#define MGAACC_LEN 0x1C5C
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#define MGAACC_AR0 0x1C60
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#define MGAACC_AR3 0x1C6C
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#define MGAACC_AR5 0x1C74
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#define MGAACC_CXBNDRY 0x1C80
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#define MGAACC_FXBNDRY 0x1C84
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#define MGAACC_YDSTLEN 0x1C88
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#define MGAACC_PITCH 0x1C8C
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#define MGAACC_YDST 0x1C90
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#define MGAACC_YDSTORG 0x1C94
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#define MGAACC_YTOP 0x1C98
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#define MGAACC_YBOT 0x1C9C
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#define MGAACC_CXLEFT 0x1CA0
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#define MGAACC_CXRIGHT 0x1CA4
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#define MGAACC_FXLEFT 0x1CA8
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#define MGAACC_FXRIGHT 0x1CAC
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#define MGAACC_STATUS 0x1E14
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#define MGAACC_ICLEAR 0x1E18 /* required for interrupt stuff */
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#define MGAACC_IEN 0x1E1C /* required for interrupt stuff */
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#define MGAACC_RST 0x1E40
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#define MGAACC_MEMRDBK 0x1E44
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#define MGAACC_OPMODE 0x1E54
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#define MGAACC_PRIMADDRESS 0x1E58
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#define MGAACC_PRIMEND 0x1E5C
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#define MGAACC_TEXORG 0x2C24 // >= G100
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#define MGAACC_DWGSYNC 0x2C4C // >= G200
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#define MGAACC_TEXORG1 0x2CA4 // >= G200
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#define MGAACC_TEXORG2 0x2CA8 // >= G200
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#define MGAACC_TEXORG3 0x2CAC // >= G200
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#define MGAACC_TEXORG4 0x2CB0 // >= G200
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#define MGAACC_SRCORG 0x2CB4 // >= G200
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#define MGAACC_DSTORG 0x2CB8 // >= G200
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/*MGA BES (Back End Scaler) registers >= TODO */
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#define MGABES_A1ORG 0x3D00
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#define MGABES_A2ORG 0x3D04
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#define MGABES_B1ORG 0x3D08
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#define MGABES_B2ORG 0x3D0C
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#define MGABES_A1CORG 0x3D10
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#define MGABES_A2CORG 0x3D14
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#define MGABES_B1CORG 0x3D18
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#define MGABES_B2CORG 0x3D1C
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#define MGABES_CTL 0x3D20
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#define MGABES_PITCH 0x3D24
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#define MGABES_HCOORD 0x3D28
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#define MGABES_VCOORD 0x3D2C
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#define MGABES_HISCAL 0x3D30
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#define MGABES_VISCAL 0x3D34
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#define MGABES_HSRCST 0x3D38
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#define MGABES_HSRCEND 0x3D3C
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#define MGABES_LUMACTL 0x3D40
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#define MGABES_V1WGHT 0x3D48
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#define MGABES_V2WGHT 0x3D4C
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#define MGABES_HSRCLST 0x3D50
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#define MGABES_V1SRCLST 0x3D54
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#define MGABES_V2SRCLST 0x3D58
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#define MGABES_A1C3ORG 0x3D60
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#define MGABES_A2C3ORG 0x3D64
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#define MGABES_B1C3ORG 0x3D68
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#define MGABES_B2C3ORG 0x3D6C
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#define MGABES_GLOBCTL 0x3DC0
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#define MGABES_STATUS 0x3DC4
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/*MAVEN registers >= TODO */
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#define MGAMAV_PIXPLLM 0x80
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#define MGAMAV_PIXPLLN 0x81
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#define MGAMAV_PIXPLLP 0x82
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#define MGAMAV_MONSET 0x8C
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#define MGAMAV_TEST 0x8D
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#define MGAMAV_MONEN 0x94
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#define MGAMAV_LASTLINEL 0x96
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#define MGAMAV_LASTLINEH 0x97
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#define MGAMAV_HSYNCLENL 0x9A
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#define MGAMAV_HSYNCLENH 0x9B
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#define MGAMAV_HSYNCSTRL 0x9C
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#define MGAMAV_HSYNCSTRH 0x9D
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#define MGAMAV_HDISPLAYL 0x9E
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#define MGAMAV_HDISPLAYH 0x9F
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#define MGAMAV_HTOTALL 0xA0
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#define MGAMAV_HTOTALH 0xA1
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#define MGAMAV_VSYNCLENL 0xA2
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#define MGAMAV_VSYNCLENH 0xA3
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#define MGAMAV_VSYNCSTRL 0xA4
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#define MGAMAV_VSYNCSTRH 0xA5
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#define MGAMAV_VDISPLAYL 0xA6
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#define MGAMAV_VDISPLAYH 0xA7
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#define MGAMAV_VTOTALL 0xA8
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#define MGAMAV_VTOTALH 0xA9
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#define MGAMAV_HVIDRSTL 0xAA
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#define MGAMAV_HVIDRSTH 0xAB
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#define MGAMAV_VVIDRSTL 0xAC
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#define MGAMAV_VVIDRSTH 0xAD
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#define MGAMAV_OUTMODE 0xB0
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#define MGAMAV_LOCK 0xB3
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#define MGAMAV_LUMA 0xB9
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#define MGAMAV_STABLE 0xBF
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/*Macros for convenient accesses to the G400*/
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#define MGA_REG8(r_) ((vuint8 *)regs)[(r_)]
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#define MGA_REG32(r_) ((vuint32 *)regs)[(r_) >> 2]
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/*read and write to PCI config space*/
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#define CFGR(A) (gx00_pci_access.offset=MGACFG_##A, ioctl(fd,GX00_GET_PCI, &gx00_pci_access,sizeof(gx00_pci_access)), gx00_pci_access.value)
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#define CFGW(A,B) (gx00_pci_access.offset=MGACFG_##A, gx00_pci_access.value = B, ioctl(fd,GX00_SET_PCI,&gx00_pci_access,sizeof(gx00_pci_access)))
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/*read and write from the dac registers*/
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#define DACR(A) (MGA_REG8(MGADAC_##A))
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#define DACW(A,B) (MGA_REG8(MGADAC_##A)=B)
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/*read and write from the dac index register*/
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#define DXIR(A) (DACW(PALWTADD,MGADXI_##A),DACR(X_DATAREG))
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#define DXIW(A,B) (DACW(PALWTADD,MGADXI_##A),DACW(X_DATAREG,B))
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/*read and write from the vga registers*/
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#define VGAR(A) (MGA_REG8(MGAVGA_##A))
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#define VGAW(A,B) (MGA_REG8(MGAVGA_##A)=B)
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/*read and write from the indexed vga registers*/
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#define VGAR_I(A,B) (VGAW(A##_I,B),VGAR(A##_D))
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#define VGAW_I(A,B,C) (VGAW(A##_I,B),VGAW(A##_D,C))
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/*read and write from the powergraphics registers*/
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#define ACCR(A) (MGA_REG32(MGAACC_##A))
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#define ACCW(A,B) (MGA_REG32(MGAACC_##A)=B)
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#define ACCGO(A,B) (MGA_REG32(MGAACC_##A + 0x0100)=B)
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/*read and write from the backend scaler registers*/
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#define BESR(A) (MGA_REG32(MGABES_##A))
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#define BESW(A,B) (MGA_REG32(MGABES_##A)=B)
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/*read and write from first CRTC*/
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#define CR1R(A) (MGA_REG32(MGACR1_##A))
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#define CR1W(A,B) (MGA_REG32(MGACR1_##A)=B)
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/*read and write from second CRTC*/
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#define CR2R(A) (MGA_REG32(MGACR2_##A))
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#define CR2W(A,B) (MGA_REG32(MGACR2_##A)=B)
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/*read and write from maven*/
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#define MAVR(A) (i2c_maven_read (MGAMAV_##A ))
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#define MAVW(A,B) (i2c_maven_write(MGAMAV_##A ,B))
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#define MAVRW(A) (i2c_maven_read (MGAMAV_##A )|(i2c_maven_read(MGAMAV_##A +1)<<8))
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#define MAVWW(A,B) (i2c_maven_write(MGAMAV_##A ,B &0xFF),i2c_maven_write(MGAMAV_##A +1,B >>8))
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#define MAVWWP(A,B) (i2c_maven_write(A ,B &0xFF),i2c_maven_write(A +1,B >>8))
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