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haiku/headers/private/graphics/radeon_hd/sea_reg.h

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radeon_hd: Properly and consistently pick HPD ID
2015-07-16 02:03:02 +03:00
/*
* DCE_8_0 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef DCE_8_0_D_H
#define DCE_8_0_D_H
#define SEA_mmPIPE0_PG_CONFIG 0x1760
#define SEA_mmPIPE0_PG_ENABLE 0x1761
#define SEA_mmPIPE0_PG_STATUS 0x1762
#define SEA_mmPIPE1_PG_CONFIG 0x1764
#define SEA_mmPIPE1_PG_ENABLE 0x1765
#define SEA_mmPIPE1_PG_STATUS 0x1766
#define SEA_mmPIPE2_PG_CONFIG 0x1768
#define SEA_mmPIPE2_PG_ENABLE 0x1769
#define SEA_mmPIPE2_PG_STATUS 0x176a
#define SEA_mmPIPE3_PG_CONFIG 0x176c
#define SEA_mmPIPE3_PG_ENABLE 0x176d
#define SEA_mmPIPE3_PG_STATUS 0x176e
#define SEA_mmPIPE4_PG_CONFIG 0x1770
#define SEA_mmPIPE4_PG_ENABLE 0x1771
#define SEA_mmPIPE4_PG_STATUS 0x1772
#define SEA_mmPIPE5_PG_CONFIG 0x1774
#define SEA_mmPIPE5_PG_ENABLE 0x1775
#define SEA_mmPIPE5_PG_STATUS 0x1776
#define SEA_mmDC_IP_REQUEST_CNTL 0x1778
#define SEA_mmDC_PGFSM_CONFIG_REG 0x177c
#define SEA_mmDC_PGFSM_WRITE_REG 0x177d
#define SEA_mmDC_PGCNTL_STATUS_REG 0x177e
#define SEA_mmDCPG_TEST_DEBUG_INDEX 0x1779
#define SEA_mmDCPG_TEST_DEBUG_DATA 0x177b
#define SEA_mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628
#define SEA_mmBL1_PWM_USER_LEVEL 0x1629
#define SEA_mmBL1_PWM_TARGET_ABM_LEVEL 0x162a
#define SEA_mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b
#define SEA_mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c
#define SEA_mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d
#define SEA_mmBL1_PWM_ABM_CNTL 0x162e
#define SEA_mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f
#define SEA_mmBL1_PWM_GRP2_REG_LOCK 0x1630
#define SEA_mmDC_ABM1_CNTL 0x1638
#define SEA_mmDC_ABM1_IPCSC_COEFF_SEL 0x1639
#define SEA_mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a
#define SEA_mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b
#define SEA_mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c
#define SEA_mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d
#define SEA_mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e
#define SEA_mmDC_ABM1_ACE_THRES_12 0x163f
#define SEA_mmDC_ABM1_ACE_THRES_34 0x1640
#define SEA_mmDC_ABM1_ACE_CNTL_MISC 0x1641
#define SEA_mmDC_ABM1_DEBUG_MISC 0x1649
#define SEA_mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a
#define SEA_mmDC_ABM1_HG_MISC_CTRL 0x164b
#define SEA_mmDC_ABM1_LS_SUM_OF_LUMA 0x164c
#define SEA_mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d
#define SEA_mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e
#define SEA_mmDC_ABM1_LS_PIXEL_COUNT 0x164f
#define SEA_mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650
#define SEA_mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651
#define SEA_mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652
#define SEA_mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653
#define SEA_mmDC_ABM1_HG_SAMPLE_RATE 0x1654
#define SEA_mmDC_ABM1_LS_SAMPLE_RATE 0x1655
#define SEA_mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656
#define SEA_mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657
#define SEA_mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658
#define SEA_mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659
#define SEA_mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a
#define SEA_mmDC_ABM1_HG_RESULT_1 0x165b
#define SEA_mmDC_ABM1_HG_RESULT_2 0x165c
#define SEA_mmDC_ABM1_HG_RESULT_3 0x165d
#define SEA_mmDC_ABM1_HG_RESULT_4 0x165e
#define SEA_mmDC_ABM1_HG_RESULT_5 0x165f
#define SEA_mmDC_ABM1_HG_RESULT_6 0x1660
#define SEA_mmDC_ABM1_HG_RESULT_7 0x1661
#define SEA_mmDC_ABM1_HG_RESULT_8 0x1662
#define SEA_mmDC_ABM1_HG_RESULT_9 0x1663
#define SEA_mmDC_ABM1_HG_RESULT_10 0x1664
#define SEA_mmDC_ABM1_HG_RESULT_11 0x1665
#define SEA_mmDC_ABM1_HG_RESULT_12 0x1666
#define SEA_mmDC_ABM1_HG_RESULT_13 0x1667
#define SEA_mmDC_ABM1_HG_RESULT_14 0x1668
#define SEA_mmDC_ABM1_HG_RESULT_15 0x1669
#define SEA_mmDC_ABM1_HG_RESULT_16 0x166a
#define SEA_mmDC_ABM1_HG_RESULT_17 0x166b
#define SEA_mmDC_ABM1_HG_RESULT_18 0x166c
#define SEA_mmDC_ABM1_HG_RESULT_19 0x166d
#define SEA_mmDC_ABM1_HG_RESULT_20 0x166e
#define SEA_mmDC_ABM1_HG_RESULT_21 0x166f
#define SEA_mmDC_ABM1_HG_RESULT_22 0x1670
#define SEA_mmDC_ABM1_HG_RESULT_23 0x1671
#define SEA_mmDC_ABM1_HG_RESULT_24 0x1672
#define SEA_mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b
#define SEA_mmDC_ABM1_BL_MASTER_LOCK 0x169c
#define SEA_mmABM_TEST_DEBUG_INDEX 0x169e
#define SEA_mmABM_TEST_DEBUG_DATA 0x169f
#define SEA_mmCRTC_DCFE_CLOCK_CONTROL 0x1b7c
#define SEA_mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0x1b7c
#define SEA_mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0x1e7c
#define SEA_mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0x417c
#define SEA_mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0x447c
#define SEA_mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0x477c
#define SEA_mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0x4a7c
#define SEA_mmCRTC_H_BLANK_EARLY_NUM 0x1b7d
#define SEA_mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d
#define SEA_mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1e7d
#define SEA_mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x417d
#define SEA_mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x447d
#define SEA_mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x477d
#define SEA_mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x4a7d
#define SEA_mmDCFE_DBG_SEL 0x1b7e
#define SEA_mmCRTC0_DCFE_DBG_SEL 0x1b7e
#define SEA_mmCRTC1_DCFE_DBG_SEL 0x1e7e
#define SEA_mmCRTC2_DCFE_DBG_SEL 0x417e
#define SEA_mmCRTC3_DCFE_DBG_SEL 0x447e
#define SEA_mmCRTC4_DCFE_DBG_SEL 0x477e
#define SEA_mmCRTC5_DCFE_DBG_SEL 0x4a7e
#define SEA_mmDCFE_MEM_LIGHT_SLEEP_CNTL 0x1b7f
#define SEA_mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1b7f
#define SEA_mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1e7f
#define SEA_mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL 0x417f
#define SEA_mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL 0x447f
#define SEA_mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL 0x477f
#define SEA_mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL 0x4a7f
#define SEA_mmCRTC_H_TOTAL 0x1b80
#define SEA_mmCRTC0_CRTC_H_TOTAL 0x1b80
#define SEA_mmCRTC1_CRTC_H_TOTAL 0x1e80
#define SEA_mmCRTC2_CRTC_H_TOTAL 0x4180
#define SEA_mmCRTC3_CRTC_H_TOTAL 0x4480
#define SEA_mmCRTC4_CRTC_H_TOTAL 0x4780
#define SEA_mmCRTC5_CRTC_H_TOTAL 0x4a80
#define SEA_mmCRTC_H_BLANK_START_END 0x1b81
#define SEA_mmCRTC0_CRTC_H_BLANK_START_END 0x1b81
#define SEA_mmCRTC1_CRTC_H_BLANK_START_END 0x1e81
#define SEA_mmCRTC2_CRTC_H_BLANK_START_END 0x4181
#define SEA_mmCRTC3_CRTC_H_BLANK_START_END 0x4481
#define SEA_mmCRTC4_CRTC_H_BLANK_START_END 0x4781
#define SEA_mmCRTC5_CRTC_H_BLANK_START_END 0x4a81
#define SEA_mmCRTC_H_SYNC_A 0x1b82
#define SEA_mmCRTC0_CRTC_H_SYNC_A 0x1b82
#define SEA_mmCRTC1_CRTC_H_SYNC_A 0x1e82
#define SEA_mmCRTC2_CRTC_H_SYNC_A 0x4182
#define SEA_mmCRTC3_CRTC_H_SYNC_A 0x4482
#define SEA_mmCRTC4_CRTC_H_SYNC_A 0x4782
#define SEA_mmCRTC5_CRTC_H_SYNC_A 0x4a82
#define SEA_mmCRTC_H_SYNC_A_CNTL 0x1b83
#define SEA_mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83
#define SEA_mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1e83
#define SEA_mmCRTC2_CRTC_H_SYNC_A_CNTL 0x4183
#define SEA_mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4483
#define SEA_mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4783
#define SEA_mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4a83
#define SEA_mmCRTC_H_SYNC_B 0x1b84
#define SEA_mmCRTC0_CRTC_H_SYNC_B 0x1b84
#define SEA_mmCRTC1_CRTC_H_SYNC_B 0x1e84
#define SEA_mmCRTC2_CRTC_H_SYNC_B 0x4184
#define SEA_mmCRTC3_CRTC_H_SYNC_B 0x4484
#define SEA_mmCRTC4_CRTC_H_SYNC_B 0x4784
#define SEA_mmCRTC5_CRTC_H_SYNC_B 0x4a84
#define SEA_mmCRTC_H_SYNC_B_CNTL 0x1b85
#define SEA_mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85
#define SEA_mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1e85
#define SEA_mmCRTC2_CRTC_H_SYNC_B_CNTL 0x4185
#define SEA_mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4485
#define SEA_mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4785
#define SEA_mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4a85
#define SEA_mmCRTC_VBI_END 0x1b86
#define SEA_mmCRTC0_CRTC_VBI_END 0x1b86
#define SEA_mmCRTC1_CRTC_VBI_END 0x1e86
#define SEA_mmCRTC2_CRTC_VBI_END 0x4186
#define SEA_mmCRTC3_CRTC_VBI_END 0x4486
#define SEA_mmCRTC4_CRTC_VBI_END 0x4786
#define SEA_mmCRTC5_CRTC_VBI_END 0x4a86
#define SEA_mmCRTC_V_TOTAL 0x1b87
#define SEA_mmCRTC0_CRTC_V_TOTAL 0x1b87
#define SEA_mmCRTC1_CRTC_V_TOTAL 0x1e87
#define SEA_mmCRTC2_CRTC_V_TOTAL 0x4187
#define SEA_mmCRTC3_CRTC_V_TOTAL 0x4487
#define SEA_mmCRTC4_CRTC_V_TOTAL 0x4787
#define SEA_mmCRTC5_CRTC_V_TOTAL 0x4a87
#define SEA_mmCRTC_V_TOTAL_MIN 0x1b88
#define SEA_mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88
#define SEA_mmCRTC1_CRTC_V_TOTAL_MIN 0x1e88
#define SEA_mmCRTC2_CRTC_V_TOTAL_MIN 0x4188
#define SEA_mmCRTC3_CRTC_V_TOTAL_MIN 0x4488
#define SEA_mmCRTC4_CRTC_V_TOTAL_MIN 0x4788
#define SEA_mmCRTC5_CRTC_V_TOTAL_MIN 0x4a88
#define SEA_mmCRTC_V_TOTAL_MAX 0x1b89
#define SEA_mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89
#define SEA_mmCRTC1_CRTC_V_TOTAL_MAX 0x1e89
#define SEA_mmCRTC2_CRTC_V_TOTAL_MAX 0x4189
#define SEA_mmCRTC3_CRTC_V_TOTAL_MAX 0x4489
#define SEA_mmCRTC4_CRTC_V_TOTAL_MAX 0x4789
#define SEA_mmCRTC5_CRTC_V_TOTAL_MAX 0x4a89
#define SEA_mmCRTC_V_TOTAL_CONTROL 0x1b8a
#define SEA_mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a
#define SEA_mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1e8a
#define SEA_mmCRTC2_CRTC_V_TOTAL_CONTROL 0x418a
#define SEA_mmCRTC3_CRTC_V_TOTAL_CONTROL 0x448a
#define SEA_mmCRTC4_CRTC_V_TOTAL_CONTROL 0x478a
#define SEA_mmCRTC5_CRTC_V_TOTAL_CONTROL 0x4a8a
#define SEA_mmCRTC_V_TOTAL_INT_STATUS 0x1b8b
#define SEA_mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b
#define SEA_mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1e8b
#define SEA_mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x418b
#define SEA_mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x448b
#define SEA_mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x478b
#define SEA_mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x4a8b
#define SEA_mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c
#define SEA_mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c
#define SEA_mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1e8c
#define SEA_mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x418c
#define SEA_mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x448c
#define SEA_mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x478c
#define SEA_mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x4a8c
#define SEA_mmCRTC_V_BLANK_START_END 0x1b8d
#define SEA_mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d
#define SEA_mmCRTC1_CRTC_V_BLANK_START_END 0x1e8d
#define SEA_mmCRTC2_CRTC_V_BLANK_START_END 0x418d
#define SEA_mmCRTC3_CRTC_V_BLANK_START_END 0x448d
#define SEA_mmCRTC4_CRTC_V_BLANK_START_END 0x478d
#define SEA_mmCRTC5_CRTC_V_BLANK_START_END 0x4a8d
#define SEA_mmCRTC_V_SYNC_A 0x1b8e
#define SEA_mmCRTC0_CRTC_V_SYNC_A 0x1b8e
#define SEA_mmCRTC1_CRTC_V_SYNC_A 0x1e8e
#define SEA_mmCRTC2_CRTC_V_SYNC_A 0x418e
#define SEA_mmCRTC3_CRTC_V_SYNC_A 0x448e
#define SEA_mmCRTC4_CRTC_V_SYNC_A 0x478e
#define SEA_mmCRTC5_CRTC_V_SYNC_A 0x4a8e
#define SEA_mmCRTC_V_SYNC_A_CNTL 0x1b8f
#define SEA_mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f
#define SEA_mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1e8f
#define SEA_mmCRTC2_CRTC_V_SYNC_A_CNTL 0x418f
#define SEA_mmCRTC3_CRTC_V_SYNC_A_CNTL 0x448f
#define SEA_mmCRTC4_CRTC_V_SYNC_A_CNTL 0x478f
#define SEA_mmCRTC5_CRTC_V_SYNC_A_CNTL 0x4a8f
#define SEA_mmCRTC_V_SYNC_B 0x1b90
#define SEA_mmCRTC0_CRTC_V_SYNC_B 0x1b90
#define SEA_mmCRTC1_CRTC_V_SYNC_B 0x1e90
#define SEA_mmCRTC2_CRTC_V_SYNC_B 0x4190
#define SEA_mmCRTC3_CRTC_V_SYNC_B 0x4490
#define SEA_mmCRTC4_CRTC_V_SYNC_B 0x4790
#define SEA_mmCRTC5_CRTC_V_SYNC_B 0x4a90
#define SEA_mmCRTC_V_SYNC_B_CNTL 0x1b91
#define SEA_mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91
#define SEA_mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1e91
#define SEA_mmCRTC2_CRTC_V_SYNC_B_CNTL 0x4191
#define SEA_mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4491
#define SEA_mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4791
#define SEA_mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4a91
#define SEA_mmCRTC_DTMTEST_CNTL 0x1b92
#define SEA_mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92
#define SEA_mmCRTC1_CRTC_DTMTEST_CNTL 0x1e92
#define SEA_mmCRTC2_CRTC_DTMTEST_CNTL 0x4192
#define SEA_mmCRTC3_CRTC_DTMTEST_CNTL 0x4492
#define SEA_mmCRTC4_CRTC_DTMTEST_CNTL 0x4792
#define SEA_mmCRTC5_CRTC_DTMTEST_CNTL 0x4a92
#define SEA_mmCRTC_DTMTEST_STATUS_POSITION 0x1b93
#define SEA_mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93
#define SEA_mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1e93
#define SEA_mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x4193
#define SEA_mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4493
#define SEA_mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4793
#define SEA_mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4a93
#define SEA_mmCRTC_TRIGA_CNTL 0x1b94
#define SEA_mmCRTC0_CRTC_TRIGA_CNTL 0x1b94
#define SEA_mmCRTC1_CRTC_TRIGA_CNTL 0x1e94
#define SEA_mmCRTC2_CRTC_TRIGA_CNTL 0x4194
#define SEA_mmCRTC3_CRTC_TRIGA_CNTL 0x4494
#define SEA_mmCRTC4_CRTC_TRIGA_CNTL 0x4794
#define SEA_mmCRTC5_CRTC_TRIGA_CNTL 0x4a94
#define SEA_mmCRTC_TRIGA_MANUAL_TRIG 0x1b95
#define SEA_mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95
#define SEA_mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1e95
#define SEA_mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x4195
#define SEA_mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4495
#define SEA_mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4795
#define SEA_mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4a95
#define SEA_mmCRTC_TRIGB_CNTL 0x1b96
#define SEA_mmCRTC0_CRTC_TRIGB_CNTL 0x1b96
#define SEA_mmCRTC1_CRTC_TRIGB_CNTL 0x1e96
#define SEA_mmCRTC2_CRTC_TRIGB_CNTL 0x4196
#define SEA_mmCRTC3_CRTC_TRIGB_CNTL 0x4496
#define SEA_mmCRTC4_CRTC_TRIGB_CNTL 0x4796
#define SEA_mmCRTC5_CRTC_TRIGB_CNTL 0x4a96
#define SEA_mmCRTC_TRIGB_MANUAL_TRIG 0x1b97
#define SEA_mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97
#define SEA_mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1e97
#define SEA_mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x4197
#define SEA_mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4497
#define SEA_mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4797
#define SEA_mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4a97
#define SEA_mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98
#define SEA_mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98
#define SEA_mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1e98
#define SEA_mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x4198
#define SEA_mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4498
#define SEA_mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4798
#define SEA_mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4a98
#define SEA_mmCRTC_FLOW_CONTROL 0x1b99
#define SEA_mmCRTC0_CRTC_FLOW_CONTROL 0x1b99
#define SEA_mmCRTC1_CRTC_FLOW_CONTROL 0x1e99
#define SEA_mmCRTC2_CRTC_FLOW_CONTROL 0x4199
#define SEA_mmCRTC3_CRTC_FLOW_CONTROL 0x4499
#define SEA_mmCRTC4_CRTC_FLOW_CONTROL 0x4799
#define SEA_mmCRTC5_CRTC_FLOW_CONTROL 0x4a99
#define SEA_mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9b
#define SEA_mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9b
#define SEA_mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1e9b
#define SEA_mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x419b
#define SEA_mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x449b
#define SEA_mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x479b
#define SEA_mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x4a9b
#define SEA_mmCRTC_CONTROL 0x1b9c
#define SEA_mmCRTC0_CRTC_CONTROL 0x1b9c
#define SEA_mmCRTC1_CRTC_CONTROL 0x1e9c
#define SEA_mmCRTC2_CRTC_CONTROL 0x419c
#define SEA_mmCRTC3_CRTC_CONTROL 0x449c
#define SEA_mmCRTC4_CRTC_CONTROL 0x479c
#define SEA_mmCRTC5_CRTC_CONTROL 0x4a9c
#define SEA_mmCRTC_BLANK_CONTROL 0x1b9d
#define SEA_mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d
#define SEA_mmCRTC1_CRTC_BLANK_CONTROL 0x1e9d
#define SEA_mmCRTC2_CRTC_BLANK_CONTROL 0x419d
#define SEA_mmCRTC3_CRTC_BLANK_CONTROL 0x449d
#define SEA_mmCRTC4_CRTC_BLANK_CONTROL 0x479d
#define SEA_mmCRTC5_CRTC_BLANK_CONTROL 0x4a9d
#define SEA_mmCRTC_INTERLACE_CONTROL 0x1b9e
#define SEA_mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e
#define SEA_mmCRTC1_CRTC_INTERLACE_CONTROL 0x1e9e
#define SEA_mmCRTC2_CRTC_INTERLACE_CONTROL 0x419e
#define SEA_mmCRTC3_CRTC_INTERLACE_CONTROL 0x449e
#define SEA_mmCRTC4_CRTC_INTERLACE_CONTROL 0x479e
#define SEA_mmCRTC5_CRTC_INTERLACE_CONTROL 0x4a9e
#define SEA_mmCRTC_INTERLACE_STATUS 0x1b9f
#define SEA_mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f
#define SEA_mmCRTC1_CRTC_INTERLACE_STATUS 0x1e9f
#define SEA_mmCRTC2_CRTC_INTERLACE_STATUS 0x419f
#define SEA_mmCRTC3_CRTC_INTERLACE_STATUS 0x449f
#define SEA_mmCRTC4_CRTC_INTERLACE_STATUS 0x479f
#define SEA_mmCRTC5_CRTC_INTERLACE_STATUS 0x4a9f
#define SEA_mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0
#define SEA_mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0
#define SEA_mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1ea0
#define SEA_mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x41a0
#define SEA_mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x44a0
#define SEA_mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x47a0
#define SEA_mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x4aa0
#define SEA_mmCRTC_PIXEL_DATA_READBACK0 0x1ba1
#define SEA_mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1
#define SEA_mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1ea1
#define SEA_mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x41a1
#define SEA_mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x44a1
#define SEA_mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x47a1
#define SEA_mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x4aa1
#define SEA_mmCRTC_PIXEL_DATA_READBACK1 0x1ba2
#define SEA_mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2
#define SEA_mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1ea2
#define SEA_mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x41a2
#define SEA_mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x44a2
#define SEA_mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x47a2
#define SEA_mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x4aa2
#define SEA_mmCRTC_STATUS 0x1ba3
#define SEA_mmCRTC0_CRTC_STATUS 0x1ba3
#define SEA_mmCRTC1_CRTC_STATUS 0x1ea3
#define SEA_mmCRTC2_CRTC_STATUS 0x41a3
#define SEA_mmCRTC3_CRTC_STATUS 0x44a3
#define SEA_mmCRTC4_CRTC_STATUS 0x47a3
#define SEA_mmCRTC5_CRTC_STATUS 0x4aa3
#define SEA_mmCRTC_STATUS_POSITION 0x1ba4
#define SEA_mmCRTC0_CRTC_STATUS_POSITION 0x1ba4
#define SEA_mmCRTC1_CRTC_STATUS_POSITION 0x1ea4
#define SEA_mmCRTC2_CRTC_STATUS_POSITION 0x41a4
#define SEA_mmCRTC3_CRTC_STATUS_POSITION 0x44a4
#define SEA_mmCRTC4_CRTC_STATUS_POSITION 0x47a4
#define SEA_mmCRTC5_CRTC_STATUS_POSITION 0x4aa4
#define SEA_mmCRTC_NOM_VERT_POSITION 0x1ba5
#define SEA_mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5
#define SEA_mmCRTC1_CRTC_NOM_VERT_POSITION 0x1ea5
#define SEA_mmCRTC2_CRTC_NOM_VERT_POSITION 0x41a5
#define SEA_mmCRTC3_CRTC_NOM_VERT_POSITION 0x44a5
#define SEA_mmCRTC4_CRTC_NOM_VERT_POSITION 0x47a5
#define SEA_mmCRTC5_CRTC_NOM_VERT_POSITION 0x4aa5
#define SEA_mmCRTC_STATUS_FRAME_COUNT 0x1ba6
#define SEA_mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6
#define SEA_mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1ea6
#define SEA_mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x41a6
#define SEA_mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x44a6
#define SEA_mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x47a6
#define SEA_mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x4aa6
#define SEA_mmCRTC_STATUS_VF_COUNT 0x1ba7
#define SEA_mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7
#define SEA_mmCRTC1_CRTC_STATUS_VF_COUNT 0x1ea7
#define SEA_mmCRTC2_CRTC_STATUS_VF_COUNT 0x41a7
#define SEA_mmCRTC3_CRTC_STATUS_VF_COUNT 0x44a7
#define SEA_mmCRTC4_CRTC_STATUS_VF_COUNT 0x47a7
#define SEA_mmCRTC5_CRTC_STATUS_VF_COUNT 0x4aa7
#define SEA_mmCRTC_STATUS_HV_COUNT 0x1ba8
#define SEA_mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8
#define SEA_mmCRTC1_CRTC_STATUS_HV_COUNT 0x1ea8
#define SEA_mmCRTC2_CRTC_STATUS_HV_COUNT 0x41a8
#define SEA_mmCRTC3_CRTC_STATUS_HV_COUNT 0x44a8
#define SEA_mmCRTC4_CRTC_STATUS_HV_COUNT 0x47a8
#define SEA_mmCRTC5_CRTC_STATUS_HV_COUNT 0x4aa8
#define SEA_mmCRTC_COUNT_CONTROL 0x1ba9
#define SEA_mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9
#define SEA_mmCRTC1_CRTC_COUNT_CONTROL 0x1ea9
#define SEA_mmCRTC2_CRTC_COUNT_CONTROL 0x41a9
#define SEA_mmCRTC3_CRTC_COUNT_CONTROL 0x44a9
#define SEA_mmCRTC4_CRTC_COUNT_CONTROL 0x47a9
#define SEA_mmCRTC5_CRTC_COUNT_CONTROL 0x4aa9
#define SEA_mmCRTC_COUNT_RESET 0x1baa
#define SEA_mmCRTC0_CRTC_COUNT_RESET 0x1baa
#define SEA_mmCRTC1_CRTC_COUNT_RESET 0x1eaa
#define SEA_mmCRTC2_CRTC_COUNT_RESET 0x41aa
#define SEA_mmCRTC3_CRTC_COUNT_RESET 0x44aa
#define SEA_mmCRTC4_CRTC_COUNT_RESET 0x47aa
#define SEA_mmCRTC5_CRTC_COUNT_RESET 0x4aaa
#define SEA_mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab
#define SEA_mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab
#define SEA_mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1eab
#define SEA_mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab
#define SEA_mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x44ab
#define SEA_mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47ab
#define SEA_mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x4aab
#define SEA_mmCRTC_VERT_SYNC_CONTROL 0x1bac
#define SEA_mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac
#define SEA_mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1eac
#define SEA_mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x41ac
#define SEA_mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x44ac
#define SEA_mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x47ac
#define SEA_mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x4aac
#define SEA_mmCRTC_STEREO_STATUS 0x1bad
#define SEA_mmCRTC0_CRTC_STEREO_STATUS 0x1bad
#define SEA_mmCRTC1_CRTC_STEREO_STATUS 0x1ead
#define SEA_mmCRTC2_CRTC_STEREO_STATUS 0x41ad
#define SEA_mmCRTC3_CRTC_STEREO_STATUS 0x44ad
#define SEA_mmCRTC4_CRTC_STEREO_STATUS 0x47ad
#define SEA_mmCRTC5_CRTC_STEREO_STATUS 0x4aad
#define SEA_mmCRTC_STEREO_CONTROL 0x1bae
#define SEA_mmCRTC0_CRTC_STEREO_CONTROL 0x1bae
#define SEA_mmCRTC1_CRTC_STEREO_CONTROL 0x1eae
#define SEA_mmCRTC2_CRTC_STEREO_CONTROL 0x41ae
#define SEA_mmCRTC3_CRTC_STEREO_CONTROL 0x44ae
#define SEA_mmCRTC4_CRTC_STEREO_CONTROL 0x47ae
#define SEA_mmCRTC5_CRTC_STEREO_CONTROL 0x4aae
#define SEA_mmCRTC_SNAPSHOT_STATUS 0x1baf
#define SEA_mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf
#define SEA_mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1eaf
#define SEA_mmCRTC2_CRTC_SNAPSHOT_STATUS 0x41af
#define SEA_mmCRTC3_CRTC_SNAPSHOT_STATUS 0x44af
#define SEA_mmCRTC4_CRTC_SNAPSHOT_STATUS 0x47af
#define SEA_mmCRTC5_CRTC_SNAPSHOT_STATUS 0x4aaf
#define SEA_mmCRTC_SNAPSHOT_CONTROL 0x1bb0
#define SEA_mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0
#define SEA_mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1eb0
#define SEA_mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x41b0
#define SEA_mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x44b0
#define SEA_mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x47b0
#define SEA_mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x4ab0
#define SEA_mmCRTC_SNAPSHOT_POSITION 0x1bb1
#define SEA_mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1
#define SEA_mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1eb1
#define SEA_mmCRTC2_CRTC_SNAPSHOT_POSITION 0x41b1
#define SEA_mmCRTC3_CRTC_SNAPSHOT_POSITION 0x44b1
#define SEA_mmCRTC4_CRTC_SNAPSHOT_POSITION 0x47b1
#define SEA_mmCRTC5_CRTC_SNAPSHOT_POSITION 0x4ab1
#define SEA_mmCRTC_SNAPSHOT_FRAME 0x1bb2
#define SEA_mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2
#define SEA_mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1eb2
#define SEA_mmCRTC2_CRTC_SNAPSHOT_FRAME 0x41b2
#define SEA_mmCRTC3_CRTC_SNAPSHOT_FRAME 0x44b2
#define SEA_mmCRTC4_CRTC_SNAPSHOT_FRAME 0x47b2
#define SEA_mmCRTC5_CRTC_SNAPSHOT_FRAME 0x4ab2
#define SEA_mmCRTC_START_LINE_CONTROL 0x1bb3
#define SEA_mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3
#define SEA_mmCRTC1_CRTC_START_LINE_CONTROL 0x1eb3
#define SEA_mmCRTC2_CRTC_START_LINE_CONTROL 0x41b3
#define SEA_mmCRTC3_CRTC_START_LINE_CONTROL 0x44b3
#define SEA_mmCRTC4_CRTC_START_LINE_CONTROL 0x47b3
#define SEA_mmCRTC5_CRTC_START_LINE_CONTROL 0x4ab3
#define SEA_mmCRTC_INTERRUPT_CONTROL 0x1bb4
#define SEA_mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4
#define SEA_mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1eb4
#define SEA_mmCRTC2_CRTC_INTERRUPT_CONTROL 0x41b4
#define SEA_mmCRTC3_CRTC_INTERRUPT_CONTROL 0x44b4
#define SEA_mmCRTC4_CRTC_INTERRUPT_CONTROL 0x47b4
#define SEA_mmCRTC5_CRTC_INTERRUPT_CONTROL 0x4ab4
#define SEA_mmCRTC_UPDATE_LOCK 0x1bb5
#define SEA_mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5
#define SEA_mmCRTC1_CRTC_UPDATE_LOCK 0x1eb5
#define SEA_mmCRTC2_CRTC_UPDATE_LOCK 0x41b5
#define SEA_mmCRTC3_CRTC_UPDATE_LOCK 0x44b5
#define SEA_mmCRTC4_CRTC_UPDATE_LOCK 0x47b5
#define SEA_mmCRTC5_CRTC_UPDATE_LOCK 0x4ab5
#define SEA_mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6
#define SEA_mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6
#define SEA_mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1eb6
#define SEA_mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6
#define SEA_mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x44b6
#define SEA_mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x47b6
#define SEA_mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x4ab6
#define SEA_mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7
#define SEA_mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7
#define SEA_mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1eb7
#define SEA_mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7
#define SEA_mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x44b7
#define SEA_mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x47b7
#define SEA_mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x4ab7
#define SEA_mmCRTC_TEST_PATTERN_CONTROL 0x1bba
#define SEA_mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba
#define SEA_mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1eba
#define SEA_mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x41ba
#define SEA_mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x44ba
#define SEA_mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x47ba
#define SEA_mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x4aba
#define SEA_mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb
#define SEA_mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb
#define SEA_mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1ebb
#define SEA_mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x41bb
#define SEA_mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x44bb
#define SEA_mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x47bb
#define SEA_mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x4abb
#define SEA_mmCRTC_TEST_PATTERN_COLOR 0x1bbc
#define SEA_mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc
#define SEA_mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1ebc
#define SEA_mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x41bc
#define SEA_mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x44bc
#define SEA_mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x47bc
#define SEA_mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x4abc
#define SEA_mmMASTER_UPDATE_LOCK 0x1bbd
#define SEA_mmCRTC0_MASTER_UPDATE_LOCK 0x1bbd
#define SEA_mmCRTC1_MASTER_UPDATE_LOCK 0x1ebd
#define SEA_mmCRTC2_MASTER_UPDATE_LOCK 0x41bd
#define SEA_mmCRTC3_MASTER_UPDATE_LOCK 0x44bd
#define SEA_mmCRTC4_MASTER_UPDATE_LOCK 0x47bd
#define SEA_mmCRTC5_MASTER_UPDATE_LOCK 0x4abd
#define SEA_mmMASTER_UPDATE_MODE 0x1bbe
#define SEA_mmCRTC0_MASTER_UPDATE_MODE 0x1bbe
#define SEA_mmCRTC1_MASTER_UPDATE_MODE 0x1ebe
#define SEA_mmCRTC2_MASTER_UPDATE_MODE 0x41be
#define SEA_mmCRTC3_MASTER_UPDATE_MODE 0x44be
#define SEA_mmCRTC4_MASTER_UPDATE_MODE 0x47be
#define SEA_mmCRTC5_MASTER_UPDATE_MODE 0x4abe
#define SEA_mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf
#define SEA_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf
#define SEA_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1ebf
#define SEA_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf
#define SEA_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x44bf
#define SEA_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x47bf
#define SEA_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x4abf
#define SEA_mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0
#define SEA_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0
#define SEA_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1ec0
#define SEA_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0
#define SEA_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x44c0
#define SEA_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x47c0
#define SEA_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x4ac0
#define SEA_mmCRTC_MVP_STATUS 0x1bc1
#define SEA_mmCRTC0_CRTC_MVP_STATUS 0x1bc1
#define SEA_mmCRTC1_CRTC_MVP_STATUS 0x1ec1
#define SEA_mmCRTC2_CRTC_MVP_STATUS 0x41c1
#define SEA_mmCRTC3_CRTC_MVP_STATUS 0x44c1
#define SEA_mmCRTC4_CRTC_MVP_STATUS 0x47c1
#define SEA_mmCRTC5_CRTC_MVP_STATUS 0x4ac1
#define SEA_mmCRTC_MASTER_EN 0x1bc2
#define SEA_mmCRTC0_CRTC_MASTER_EN 0x1bc2
#define SEA_mmCRTC1_CRTC_MASTER_EN 0x1ec2
#define SEA_mmCRTC2_CRTC_MASTER_EN 0x41c2
#define SEA_mmCRTC3_CRTC_MASTER_EN 0x44c2
#define SEA_mmCRTC4_CRTC_MASTER_EN 0x47c2
#define SEA_mmCRTC5_CRTC_MASTER_EN 0x4ac2
#define SEA_mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3
#define SEA_mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3
#define SEA_mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1ec3
#define SEA_mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3
#define SEA_mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x44c3
#define SEA_mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x47c3
#define SEA_mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x4ac3
#define SEA_mmCRTC_V_UPDATE_INT_STATUS 0x1bc4
#define SEA_mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4
#define SEA_mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1ec4
#define SEA_mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x41c4
#define SEA_mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x44c4
#define SEA_mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x47c4
#define SEA_mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x4ac4
#define SEA_mmCRTC_OVERSCAN_COLOR 0x1bc8
#define SEA_mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8
#define SEA_mmCRTC1_CRTC_OVERSCAN_COLOR 0x1ec8
#define SEA_mmCRTC2_CRTC_OVERSCAN_COLOR 0x41c8
#define SEA_mmCRTC3_CRTC_OVERSCAN_COLOR 0x44c8
#define SEA_mmCRTC4_CRTC_OVERSCAN_COLOR 0x47c8
#define SEA_mmCRTC5_CRTC_OVERSCAN_COLOR 0x4ac8
#define SEA_mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9
#define SEA_mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9
#define SEA_mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1ec9
#define SEA_mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x41c9
#define SEA_mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x44c9
#define SEA_mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x47c9
#define SEA_mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x4ac9
#define SEA_mmCRTC_BLANK_DATA_COLOR 0x1bca
#define SEA_mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca
#define SEA_mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1eca
#define SEA_mmCRTC2_CRTC_BLANK_DATA_COLOR 0x41ca
#define SEA_mmCRTC3_CRTC_BLANK_DATA_COLOR 0x44ca
#define SEA_mmCRTC4_CRTC_BLANK_DATA_COLOR 0x47ca
#define SEA_mmCRTC5_CRTC_BLANK_DATA_COLOR 0x4aca
#define SEA_mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb
#define SEA_mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb
#define SEA_mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1ecb
#define SEA_mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x41cb
#define SEA_mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x44cb
#define SEA_mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x47cb
#define SEA_mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x4acb
#define SEA_mmCRTC_BLACK_COLOR 0x1bcc
#define SEA_mmCRTC0_CRTC_BLACK_COLOR 0x1bcc
#define SEA_mmCRTC1_CRTC_BLACK_COLOR 0x1ecc
#define SEA_mmCRTC2_CRTC_BLACK_COLOR 0x41cc
#define SEA_mmCRTC3_CRTC_BLACK_COLOR 0x44cc
#define SEA_mmCRTC4_CRTC_BLACK_COLOR 0x47cc
#define SEA_mmCRTC5_CRTC_BLACK_COLOR 0x4acc
#define SEA_mmCRTC_BLACK_COLOR_EXT 0x1bcd
#define SEA_mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd
#define SEA_mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1ecd
#define SEA_mmCRTC2_CRTC_BLACK_COLOR_EXT 0x41cd
#define SEA_mmCRTC3_CRTC_BLACK_COLOR_EXT 0x44cd
#define SEA_mmCRTC4_CRTC_BLACK_COLOR_EXT 0x47cd
#define SEA_mmCRTC5_CRTC_BLACK_COLOR_EXT 0x4acd
#define SEA_mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce
#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce
#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1ece
#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce
#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x44ce
#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x47ce
#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x4ace
#define SEA_mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf
#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf
#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1ecf
#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf
#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x44cf
#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x47cf
#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x4acf
#define SEA_mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0
#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0
#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1ed0
#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0
#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x44d0
#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x47d0
#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x4ad0
#define SEA_mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1
#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1
#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1ed1
#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1
#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x44d1
#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x47d1
#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x4ad1
#define SEA_mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2
#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2
#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1ed2
#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2
#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x44d2
#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x47d2
#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x4ad2
#define SEA_mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3
#define SEA_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3
#define SEA_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1ed3
#define SEA_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3
#define SEA_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x44d3
#define SEA_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x47d3
#define SEA_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x4ad3
#define SEA_mmCRTC_CRC_CNTL 0x1bd4
#define SEA_mmCRTC0_CRTC_CRC_CNTL 0x1bd4
#define SEA_mmCRTC1_CRTC_CRC_CNTL 0x1ed4
#define SEA_mmCRTC2_CRTC_CRC_CNTL 0x41d4
#define SEA_mmCRTC3_CRTC_CRC_CNTL 0x44d4
#define SEA_mmCRTC4_CRTC_CRC_CNTL 0x47d4
#define SEA_mmCRTC5_CRTC_CRC_CNTL 0x4ad4
#define SEA_mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5
#define SEA_mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5
#define SEA_mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1ed5
#define SEA_mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5
#define SEA_mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x44d5
#define SEA_mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x47d5
#define SEA_mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x4ad5
#define SEA_mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6
#define SEA_mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6
#define SEA_mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1ed6
#define SEA_mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6
#define SEA_mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x44d6
#define SEA_mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x47d6
#define SEA_mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x4ad6
#define SEA_mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7
#define SEA_mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7
#define SEA_mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1ed7
#define SEA_mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7
#define SEA_mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x44d7
#define SEA_mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x47d7
#define SEA_mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x4ad7
#define SEA_mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8
#define SEA_mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8
#define SEA_mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1ed8
#define SEA_mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8
#define SEA_mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x44d8
#define SEA_mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x47d8
#define SEA_mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x4ad8
#define SEA_mmCRTC_CRC0_DATA_RG 0x1bd9
#define SEA_mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9
#define SEA_mmCRTC1_CRTC_CRC0_DATA_RG 0x1ed9
#define SEA_mmCRTC2_CRTC_CRC0_DATA_RG 0x41d9
#define SEA_mmCRTC3_CRTC_CRC0_DATA_RG 0x44d9
#define SEA_mmCRTC4_CRTC_CRC0_DATA_RG 0x47d9
#define SEA_mmCRTC5_CRTC_CRC0_DATA_RG 0x4ad9
#define SEA_mmCRTC_CRC0_DATA_B 0x1bda
#define SEA_mmCRTC0_CRTC_CRC0_DATA_B 0x1bda
#define SEA_mmCRTC1_CRTC_CRC0_DATA_B 0x1eda
#define SEA_mmCRTC2_CRTC_CRC0_DATA_B 0x41da
#define SEA_mmCRTC3_CRTC_CRC0_DATA_B 0x44da
#define SEA_mmCRTC4_CRTC_CRC0_DATA_B 0x47da
#define SEA_mmCRTC5_CRTC_CRC0_DATA_B 0x4ada
#define SEA_mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb
#define SEA_mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb
#define SEA_mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1edb
#define SEA_mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db
#define SEA_mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x44db
#define SEA_mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x47db
#define SEA_mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x4adb
#define SEA_mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc
#define SEA_mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc
#define SEA_mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1edc
#define SEA_mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc
#define SEA_mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x44dc
#define SEA_mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x47dc
#define SEA_mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x4adc
#define SEA_mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd
#define SEA_mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd
#define SEA_mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1edd
#define SEA_mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd
#define SEA_mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x44dd
#define SEA_mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x47dd
#define SEA_mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x4add
#define SEA_mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde
#define SEA_mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde
#define SEA_mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1ede
#define SEA_mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de
#define SEA_mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x44de
#define SEA_mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x47de
#define SEA_mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x4ade
#define SEA_mmCRTC_CRC1_DATA_RG 0x1bdf
#define SEA_mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf
#define SEA_mmCRTC1_CRTC_CRC1_DATA_RG 0x1edf
#define SEA_mmCRTC2_CRTC_CRC1_DATA_RG 0x41df
#define SEA_mmCRTC3_CRTC_CRC1_DATA_RG 0x44df
#define SEA_mmCRTC4_CRTC_CRC1_DATA_RG 0x47df
#define SEA_mmCRTC5_CRTC_CRC1_DATA_RG 0x4adf
#define SEA_mmCRTC_CRC1_DATA_B 0x1be0
#define SEA_mmCRTC0_CRTC_CRC1_DATA_B 0x1be0
#define SEA_mmCRTC1_CRTC_CRC1_DATA_B 0x1ee0
#define SEA_mmCRTC2_CRTC_CRC1_DATA_B 0x41e0
#define SEA_mmCRTC3_CRTC_CRC1_DATA_B 0x44e0
#define SEA_mmCRTC4_CRTC_CRC1_DATA_B 0x47e0
#define SEA_mmCRTC5_CRTC_CRC1_DATA_B 0x4ae0
#define SEA_mmCRTC_EXT_TIMING_SYNC_CONTROL 0x1be1
#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x1be1
#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x1ee1
#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x41e1
#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x44e1
#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x47e1
#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x4ae1
#define SEA_mmCRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2
#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2
#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1ee2
#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x41e2
#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x44e2
#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x47e2
#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x4ae2
#define SEA_mmCRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3
#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3
#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1ee3
#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x41e3
#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x44e3
#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x47e3
#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x4ae3
#define SEA_mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4
#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4
#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1ee4
#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x41e4
#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x44e4
#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x47e4
#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x4ae4
#define SEA_mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5
#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5
#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1ee5
#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x41e5
#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x44e5
#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x47e5
#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x4ae5
#define SEA_mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6
#define SEA_mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6
#define SEA_mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1ee6
#define SEA_mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x41e6
#define SEA_mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x44e6
#define SEA_mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x47e6
#define SEA_mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x4ae6
#define SEA_mmCRTC_STATIC_SCREEN_CONTROL 0x1be7
#define SEA_mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7
#define SEA_mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1ee7
#define SEA_mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x41e7
#define SEA_mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x44e7
#define SEA_mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x47e7
#define SEA_mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x4ae7
#define SEA_mmCRTC_3D_STRUCTURE_CONTROL 0x1b78
#define SEA_mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78
#define SEA_mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1e78
#define SEA_mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x4178
#define SEA_mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4478
#define SEA_mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4778
#define SEA_mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4a78
#define SEA_mmCRTC_GSL_VSYNC_GAP 0x1b79
#define SEA_mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79
#define SEA_mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1e79
#define SEA_mmCRTC2_CRTC_GSL_VSYNC_GAP 0x4179
#define SEA_mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4479
#define SEA_mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4779
#define SEA_mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4a79
#define SEA_mmCRTC_GSL_WINDOW 0x1b7a
#define SEA_mmCRTC0_CRTC_GSL_WINDOW 0x1b7a
#define SEA_mmCRTC1_CRTC_GSL_WINDOW 0x1e7a
#define SEA_mmCRTC2_CRTC_GSL_WINDOW 0x417a
#define SEA_mmCRTC3_CRTC_GSL_WINDOW 0x447a
#define SEA_mmCRTC4_CRTC_GSL_WINDOW 0x477a
#define SEA_mmCRTC5_CRTC_GSL_WINDOW 0x4a7a
#define SEA_mmCRTC_GSL_CONTROL 0x1b7b
#define SEA_mmCRTC0_CRTC_GSL_CONTROL 0x1b7b
#define SEA_mmCRTC1_CRTC_GSL_CONTROL 0x1e7b
#define SEA_mmCRTC2_CRTC_GSL_CONTROL 0x417b
#define SEA_mmCRTC3_CRTC_GSL_CONTROL 0x447b
#define SEA_mmCRTC4_CRTC_GSL_CONTROL 0x477b
#define SEA_mmCRTC5_CRTC_GSL_CONTROL 0x4a7b
#define SEA_mmCRTC_TEST_DEBUG_INDEX 0x1bc6
#define SEA_mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6
#define SEA_mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1ec6
#define SEA_mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x41c6
#define SEA_mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x44c6
#define SEA_mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x47c6
#define SEA_mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x4ac6
#define SEA_mmCRTC_TEST_DEBUG_DATA 0x1bc7
#define SEA_mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7
#define SEA_mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1ec7
#define SEA_mmCRTC2_CRTC_TEST_DEBUG_DATA 0x41c7
#define SEA_mmCRTC3_CRTC_TEST_DEBUG_DATA 0x44c7
#define SEA_mmCRTC4_CRTC_TEST_DEBUG_DATA 0x47c7
#define SEA_mmCRTC5_CRTC_TEST_DEBUG_DATA 0x4ac7
#define SEA_mmDAC_ENABLE 0x19e4
#define SEA_mmDAC_SOURCE_SELECT 0x19e5
#define SEA_mmDAC_CRC_EN 0x19e6
#define SEA_mmDAC_CRC_CONTROL 0x19e7
#define SEA_mmDAC_CRC_SIG_RGB_MASK 0x19e8
#define SEA_mmDAC_CRC_SIG_CONTROL_MASK 0x19e9
#define SEA_mmDAC_CRC_SIG_RGB 0x19ea
#define SEA_mmDAC_CRC_SIG_CONTROL 0x19eb
#define SEA_mmDAC_SYNC_TRISTATE_CONTROL 0x19ec
#define SEA_mmDAC_STEREOSYNC_SELECT 0x19ed
#define SEA_mmDAC_AUTODETECT_CONTROL 0x19ee
#define SEA_mmDAC_AUTODETECT_CONTROL2 0x19ef
#define SEA_mmDAC_AUTODETECT_CONTROL3 0x19f0
#define SEA_mmDAC_AUTODETECT_STATUS 0x19f1
#define SEA_mmDAC_AUTODETECT_INT_CONTROL 0x19f2
#define SEA_mmDAC_FORCE_OUTPUT_CNTL 0x19f3
#define SEA_mmDAC_FORCE_DATA 0x19f4
#define SEA_mmDAC_POWERDOWN 0x19f5
#define SEA_mmDAC_CONTROL 0x19f6
#define SEA_mmDAC_COMPARATOR_ENABLE 0x19f7
#define SEA_mmDAC_COMPARATOR_OUTPUT 0x19f8
#define SEA_mmDAC_PWR_CNTL 0x19f9
#define SEA_mmDAC_DFT_CONFIG 0x19fa
#define SEA_mmDAC_FIFO_STATUS 0x19fb
#define SEA_mmPERFCOUNTER_CNTL 0x170
#define SEA_mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170
#define SEA_mmDC_PERFMON1_PERFCOUNTER_CNTL 0x1870
#define SEA_mmDC_PERFMON2_PERFCOUNTER_CNTL 0x1b24
#define SEA_mmDC_PERFMON3_PERFCOUNTER_CNTL 0x1e24
#define SEA_mmDC_PERFMON4_PERFCOUNTER_CNTL 0x4124
#define SEA_mmDC_PERFMON5_PERFCOUNTER_CNTL 0x4424
#define SEA_mmDC_PERFMON6_PERFCOUNTER_CNTL 0x4724
#define SEA_mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4a24
#define SEA_mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4c40
#define SEA_mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4d14
#define SEA_mmPERFCOUNTER_STATE 0x171
#define SEA_mmDC_PERFMON0_PERFCOUNTER_STATE 0x171
#define SEA_mmDC_PERFMON1_PERFCOUNTER_STATE 0x1871
#define SEA_mmDC_PERFMON2_PERFCOUNTER_STATE 0x1b25
#define SEA_mmDC_PERFMON3_PERFCOUNTER_STATE 0x1e25
#define SEA_mmDC_PERFMON4_PERFCOUNTER_STATE 0x4125
#define SEA_mmDC_PERFMON5_PERFCOUNTER_STATE 0x4425
#define SEA_mmDC_PERFMON6_PERFCOUNTER_STATE 0x4725
#define SEA_mmDC_PERFMON7_PERFCOUNTER_STATE 0x4a25
#define SEA_mmDC_PERFMON8_PERFCOUNTER_STATE 0x4c41
#define SEA_mmDC_PERFMON9_PERFCOUNTER_STATE 0x4d15
#define SEA_mmPERFMON_CNTL 0x173
#define SEA_mmDC_PERFMON0_PERFMON_CNTL 0x173
#define SEA_mmDC_PERFMON1_PERFMON_CNTL 0x1873
#define SEA_mmDC_PERFMON2_PERFMON_CNTL 0x1b27
#define SEA_mmDC_PERFMON3_PERFMON_CNTL 0x1e27
#define SEA_mmDC_PERFMON4_PERFMON_CNTL 0x4127
#define SEA_mmDC_PERFMON5_PERFMON_CNTL 0x4427
#define SEA_mmDC_PERFMON6_PERFMON_CNTL 0x4727
#define SEA_mmDC_PERFMON7_PERFMON_CNTL 0x4a27
#define SEA_mmDC_PERFMON8_PERFMON_CNTL 0x4c43
#define SEA_mmDC_PERFMON9_PERFMON_CNTL 0x4d17
#define SEA_mmPERFMON_CVALUE_INT_MISC 0x172
#define SEA_mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172
#define SEA_mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x1872
#define SEA_mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x1b26
#define SEA_mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x1e26
#define SEA_mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x4126
#define SEA_mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x4426
#define SEA_mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x4726
#define SEA_mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4a26
#define SEA_mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4c42
#define SEA_mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4d16
#define SEA_mmPERFMON_CVALUE_LOW 0x174
#define SEA_mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174
#define SEA_mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x1874
#define SEA_mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x1b28
#define SEA_mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x1e28
#define SEA_mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x4128
#define SEA_mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x4428
#define SEA_mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x4728
#define SEA_mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4a28
#define SEA_mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4c44
#define SEA_mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4d18
#define SEA_mmPERFMON_HI 0x175
#define SEA_mmDC_PERFMON0_PERFMON_HI 0x175
#define SEA_mmDC_PERFMON1_PERFMON_HI 0x1875
#define SEA_mmDC_PERFMON2_PERFMON_HI 0x1b29
#define SEA_mmDC_PERFMON3_PERFMON_HI 0x1e29
#define SEA_mmDC_PERFMON4_PERFMON_HI 0x4129
#define SEA_mmDC_PERFMON5_PERFMON_HI 0x4429
#define SEA_mmDC_PERFMON6_PERFMON_HI 0x4729
#define SEA_mmDC_PERFMON7_PERFMON_HI 0x4a29
#define SEA_mmDC_PERFMON8_PERFMON_HI 0x4c45
#define SEA_mmDC_PERFMON9_PERFMON_HI 0x4d19
#define SEA_mmPERFMON_LOW 0x176
#define SEA_mmDC_PERFMON0_PERFMON_LOW 0x176
#define SEA_mmDC_PERFMON1_PERFMON_LOW 0x1876
#define SEA_mmDC_PERFMON2_PERFMON_LOW 0x1b2a
#define SEA_mmDC_PERFMON3_PERFMON_LOW 0x1e2a
#define SEA_mmDC_PERFMON4_PERFMON_LOW 0x412a
#define SEA_mmDC_PERFMON5_PERFMON_LOW 0x442a
#define SEA_mmDC_PERFMON6_PERFMON_LOW 0x472a
#define SEA_mmDC_PERFMON7_PERFMON_LOW 0x4a2a
#define SEA_mmDC_PERFMON8_PERFMON_LOW 0x4c46
#define SEA_mmDC_PERFMON9_PERFMON_LOW 0x4d1a
#define SEA_mmPERFMON_TEST_DEBUG_INDEX 0x177
#define SEA_mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177
#define SEA_mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x1877
#define SEA_mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x1b2b
#define SEA_mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x1e2b
#define SEA_mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x412b
#define SEA_mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x442b
#define SEA_mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x472b
#define SEA_mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x4a2b
#define SEA_mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x4c47
#define SEA_mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x4d1b
#define SEA_mmPERFMON_TEST_DEBUG_DATA 0x178
#define SEA_mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178
#define SEA_mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x1878
#define SEA_mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x1b2c
#define SEA_mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x1e2c
#define SEA_mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x412c
#define SEA_mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x442c
#define SEA_mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x472c
#define SEA_mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x4a2c
#define SEA_mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x4c48
#define SEA_mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x4d1c
#define SEA_mmVGA25_PPLL_REF_DIV 0xd8
#define SEA_mmVGA28_PPLL_REF_DIV 0xd9
#define SEA_mmVGA41_PPLL_REF_DIV 0xda
#define SEA_mmVGA25_PPLL_FB_DIV 0xdc
#define SEA_mmVGA28_PPLL_FB_DIV 0xdd
#define SEA_mmVGA41_PPLL_FB_DIV 0xde
#define SEA_mmVGA25_PPLL_POST_DIV 0xe0
#define SEA_mmVGA28_PPLL_POST_DIV 0xe1
#define SEA_mmVGA41_PPLL_POST_DIV 0xe2
#define SEA_mmVGA25_PPLL_ANALOG 0xe4
#define SEA_mmVGA28_PPLL_ANALOG 0xe5
#define SEA_mmVGA41_PPLL_ANALOG 0xe6
#define SEA_mmDPREFCLK_CNTL 0x118
#define SEA_mmSCANIN_SOFT_RESET 0x11e
#define SEA_mmDCCG_GTC_CNTL 0x120
#define SEA_mmDCCG_GTC_DTO_INCR 0x121
#define SEA_mmDCCG_GTC_DTO_MODULO 0x122
#define SEA_mmDCCG_GTC_CURRENT 0x123
#define SEA_mmDCCG_DS_DTO_INCR 0x113
#define SEA_mmDCCG_DS_DTO_MODULO 0x114
#define SEA_mmDCCG_DS_CNTL 0x115
#define SEA_mmDCCG_DS_HW_CAL_INTERVAL 0x116
#define SEA_mmDCCG_DS_DEBUG_CNTL 0x112
#define SEA_mmDMCU_SMU_INTERRUPT_CNTL 0x12c
#define SEA_mmSMU_CONTROL 0x12d
#define SEA_mmSMU_INTERRUPT_CONTROL 0x12e
#define SEA_mmDAC_CLK_ENABLE 0x128
#define SEA_mmDVO_CLK_ENABLE 0x129
#define SEA_mmDCCG_GATE_DISABLE_CNTL 0x134
#define SEA_mmDISPCLK_CGTT_BLK_CTRL_REG 0x135
#define SEA_mmSCLK_CGTT_BLK_CTRL_REG 0x136
#define SEA_mmDCCG_CAC_STATUS 0x137
#define SEA_mmPIXCLK1_RESYNC_CNTL 0x138
#define SEA_mmPIXCLK2_RESYNC_CNTL 0x139
#define SEA_mmPIXCLK0_RESYNC_CNTL 0x13a
#define SEA_mmMICROSECOND_TIME_BASE_DIV 0x13b
#define SEA_mmDCCG_DISP_CNTL_REG 0x13f
#define SEA_mmDISPPLL_BG_CNTL 0x13c
#define SEA_mmDIG_SOFT_RESET 0x13d
#define SEA_mmMILLISECOND_TIME_BASE_DIV 0x130
#define SEA_mmDISPCLK_FREQ_CHANGE_CNTL 0x131
#define SEA_mmLIGHT_SLEEP_CNTL 0x132
#define SEA_mmDCCG_PERFMON_CNTL 0x133
#define SEA_mmCRTC0_PIXEL_RATE_CNTL 0x140
#define SEA_mmDP_DTO0_PHASE 0x141
#define SEA_mmDP_DTO0_MODULO 0x142
#define SEA_mmCRTC1_PIXEL_RATE_CNTL 0x144
#define SEA_mmDP_DTO1_PHASE 0x145
#define SEA_mmDP_DTO1_MODULO 0x146
#define SEA_mmCRTC2_PIXEL_RATE_CNTL 0x148
#define SEA_mmDP_DTO2_PHASE 0x149
#define SEA_mmDP_DTO2_MODULO 0x14a
#define SEA_mmCRTC3_PIXEL_RATE_CNTL 0x14c
#define SEA_mmDP_DTO3_PHASE 0x14d
#define SEA_mmDP_DTO3_MODULO 0x14e
#define SEA_mmCRTC4_PIXEL_RATE_CNTL 0x150
#define SEA_mmDP_DTO4_PHASE 0x151
#define SEA_mmDP_DTO4_MODULO 0x152
#define SEA_mmCRTC5_PIXEL_RATE_CNTL 0x154
#define SEA_mmDP_DTO5_PHASE 0x155
#define SEA_mmDP_DTO5_MODULO 0x156
#define SEA_mmDCFE0_SOFT_RESET 0x158
#define SEA_mmDCFE1_SOFT_RESET 0x159
#define SEA_mmDCFE2_SOFT_RESET 0x15a
#define SEA_mmDCFE3_SOFT_RESET 0x15b
#define SEA_mmDCFE4_SOFT_RESET 0x15c
#define SEA_mmDCFE5_SOFT_RESET 0x15d
#define SEA_mmDCI_SOFT_RESET 0x15e
#define SEA_mmDCCG_SOFT_RESET 0x15f
#define SEA_mmSYMCLKA_CLOCK_ENABLE 0x160
#define SEA_mmSYMCLKB_CLOCK_ENABLE 0x161
#define SEA_mmSYMCLKC_CLOCK_ENABLE 0x162
#define SEA_mmSYMCLKD_CLOCK_ENABLE 0x163
#define SEA_mmSYMCLKE_CLOCK_ENABLE 0x164
#define SEA_mmSYMCLKF_CLOCK_ENABLE 0x165
#define SEA_mmSYMCLKG_CLOCK_ENABLE 0x117
#define SEA_mmUNIPHY_SOFT_RESET 0x166
#define SEA_mmDCO_SOFT_RESET 0x167
#define SEA_mmDVOACLKD_CNTL 0x168
#define SEA_mmDVOACLKC_MVP_CNTL 0x169
#define SEA_mmDVOACLKC_CNTL 0x16a
#define SEA_mmDCCG_AUDIO_DTO_SOURCE 0x16b
#define SEA_mmDCCG_AUDIO_DTO0_PHASE 0x16c
#define SEA_mmDCCG_AUDIO_DTO0_MODULE 0x16d
#define SEA_mmDCCG_AUDIO_DTO1_PHASE 0x16e
#define SEA_mmDCCG_AUDIO_DTO1_MODULE 0x16f
#define SEA_mmDCCG_TEST_DEBUG_INDEX 0x17c
#define SEA_mmDCCG_TEST_DEBUG_DATA 0x17d
#define SEA_mmDCCG_TEST_CLK_SEL 0x17e
#define SEA_mmPLL_REF_DIV 0x1700
#define SEA_mmDCCG_PLL0_PLL_REF_DIV 0x1700
#define SEA_mmDCCG_PLL1_PLL_REF_DIV 0x1714
#define SEA_mmDCCG_PLL2_PLL_REF_DIV 0x1728
#define SEA_mmDCCG_PLL3_PLL_REF_DIV 0x173c
#define SEA_mmPLL_FB_DIV 0x1701
#define SEA_mmDCCG_PLL0_PLL_FB_DIV 0x1701
#define SEA_mmDCCG_PLL1_PLL_FB_DIV 0x1715
#define SEA_mmDCCG_PLL2_PLL_FB_DIV 0x1729
#define SEA_mmDCCG_PLL3_PLL_FB_DIV 0x173d
#define SEA_mmPLL_POST_DIV 0x1702
#define SEA_mmDCCG_PLL0_PLL_POST_DIV 0x1702
#define SEA_mmDCCG_PLL1_PLL_POST_DIV 0x1716
#define SEA_mmDCCG_PLL2_PLL_POST_DIV 0x172a
#define SEA_mmDCCG_PLL3_PLL_POST_DIV 0x173e
#define SEA_mmPLL_SS_AMOUNT_DSFRAC 0x1703
#define SEA_mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703
#define SEA_mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC 0x1717
#define SEA_mmDCCG_PLL2_PLL_SS_AMOUNT_DSFRAC 0x172b
#define SEA_mmDCCG_PLL3_PLL_SS_AMOUNT_DSFRAC 0x173f
#define SEA_mmPLL_SS_CNTL 0x1704
#define SEA_mmDCCG_PLL0_PLL_SS_CNTL 0x1704
#define SEA_mmDCCG_PLL1_PLL_SS_CNTL 0x1718
#define SEA_mmDCCG_PLL2_PLL_SS_CNTL 0x172c
#define SEA_mmDCCG_PLL3_PLL_SS_CNTL 0x1740
#define SEA_mmPLL_DS_CNTL 0x1705
#define SEA_mmDCCG_PLL0_PLL_DS_CNTL 0x1705
#define SEA_mmDCCG_PLL1_PLL_DS_CNTL 0x1719
#define SEA_mmDCCG_PLL2_PLL_DS_CNTL 0x172d
#define SEA_mmDCCG_PLL3_PLL_DS_CNTL 0x1741
#define SEA_mmPLL_IDCLK_CNTL 0x1706
#define SEA_mmDCCG_PLL0_PLL_IDCLK_CNTL 0x1706
#define SEA_mmDCCG_PLL1_PLL_IDCLK_CNTL 0x171a
#define SEA_mmDCCG_PLL2_PLL_IDCLK_CNTL 0x172e
#define SEA_mmDCCG_PLL3_PLL_IDCLK_CNTL 0x1742
#define SEA_mmPLL_CNTL 0x1707
#define SEA_mmDCCG_PLL0_PLL_CNTL 0x1707
#define SEA_mmDCCG_PLL1_PLL_CNTL 0x171b
#define SEA_mmDCCG_PLL2_PLL_CNTL 0x172f
#define SEA_mmDCCG_PLL3_PLL_CNTL 0x1743
#define SEA_mmPLL_ANALOG 0x1708
#define SEA_mmDCCG_PLL0_PLL_ANALOG 0x1708
#define SEA_mmDCCG_PLL1_PLL_ANALOG 0x171c
#define SEA_mmDCCG_PLL2_PLL_ANALOG 0x1730
#define SEA_mmDCCG_PLL3_PLL_ANALOG 0x1744
#define SEA_mmPLL_ANALOG_CNTL 0x1711
#define SEA_mmDCCG_PLL0_PLL_ANALOG_CNTL 0x1711
#define SEA_mmDCCG_PLL1_PLL_ANALOG_CNTL 0x1725
#define SEA_mmDCCG_PLL2_PLL_ANALOG_CNTL 0x1739
#define SEA_mmDCCG_PLL3_PLL_ANALOG_CNTL 0x174d
#define SEA_mmPLL_VREG_CNTL 0x1709
#define SEA_mmDCCG_PLL0_PLL_VREG_CNTL 0x1709
#define SEA_mmDCCG_PLL1_PLL_VREG_CNTL 0x171d
#define SEA_mmDCCG_PLL2_PLL_VREG_CNTL 0x1731
#define SEA_mmDCCG_PLL3_PLL_VREG_CNTL 0x1745
#define SEA_mmPLL_XOR_LOCK 0x1710
#define SEA_mmDCCG_PLL0_PLL_XOR_LOCK 0x1710
#define SEA_mmDCCG_PLL1_PLL_XOR_LOCK 0x1724
#define SEA_mmDCCG_PLL2_PLL_XOR_LOCK 0x1738
#define SEA_mmDCCG_PLL3_PLL_XOR_LOCK 0x174c
#define SEA_mmPLL_UNLOCK_DETECT_CNTL 0x170a
#define SEA_mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170a
#define SEA_mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL 0x171e
#define SEA_mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL 0x1732
#define SEA_mmDCCG_PLL3_PLL_UNLOCK_DETECT_CNTL 0x1746
#define SEA_mmPLL_DEBUG_CNTL 0x170b
#define SEA_mmDCCG_PLL0_PLL_DEBUG_CNTL 0x170b
#define SEA_mmDCCG_PLL1_PLL_DEBUG_CNTL 0x171f
#define SEA_mmDCCG_PLL2_PLL_DEBUG_CNTL 0x1733
#define SEA_mmDCCG_PLL3_PLL_DEBUG_CNTL 0x1747
#define SEA_mmPLL_UPDATE_LOCK 0x170c
#define SEA_mmDCCG_PLL0_PLL_UPDATE_LOCK 0x170c
#define SEA_mmDCCG_PLL1_PLL_UPDATE_LOCK 0x1720
#define SEA_mmDCCG_PLL2_PLL_UPDATE_LOCK 0x1734
#define SEA_mmDCCG_PLL3_PLL_UPDATE_LOCK 0x1748
#define SEA_mmPLL_UPDATE_CNTL 0x170d
#define SEA_mmDCCG_PLL0_PLL_UPDATE_CNTL 0x170d
#define SEA_mmDCCG_PLL1_PLL_UPDATE_CNTL 0x1721
#define SEA_mmDCCG_PLL2_PLL_UPDATE_CNTL 0x1735
#define SEA_mmDCCG_PLL3_PLL_UPDATE_CNTL 0x1749
#define SEA_mmPLL_DISPCLK_DTO_CNTL 0x170e
#define SEA_mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL 0x170e
#define SEA_mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL 0x1722
#define SEA_mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL 0x1736
#define SEA_mmDCCG_PLL3_PLL_DISPCLK_DTO_CNTL 0x174a
#define SEA_mmPLL_DISPCLK_CURRENT_DTO_PHASE 0x170f
#define SEA_mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE 0x170f
#define SEA_mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE 0x1723
#define SEA_mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE 0x1737
#define SEA_mmDCCG_PLL3_PLL_DISPCLK_CURRENT_DTO_PHASE 0x174b
#define SEA_mmDENTIST_DISPCLK_CNTL 0x124
#define SEA_mmDCDEBUG_BUS_CLK1_SEL 0x1860
#define SEA_mmDCDEBUG_BUS_CLK2_SEL 0x1861
#define SEA_mmDCDEBUG_BUS_CLK3_SEL 0x1862
#define SEA_mmDCDEBUG_BUS_CLK4_SEL 0x1863
#define SEA_mmDCDEBUG_OUT_PIN_OVERRIDE 0x186a
#define SEA_mmDCDEBUG_OUT_CNTL 0x186b
#define SEA_mmDCDEBUG_OUT_DATA 0x186e
#define SEA_mmDMIF_ADDR_CONFIG 0x2f5
#define SEA_mmDMIF_CONTROL 0x2f6
#define SEA_mmDMIF_STATUS 0x2f7
#define SEA_mmDMIF_HW_DEBUG 0x2f8
#define SEA_mmDMIF_ARBITRATION_CONTROL 0x2f9
#define SEA_mmPIPE0_ARBITRATION_CONTROL3 0x2fa
#define SEA_mmPIPE1_ARBITRATION_CONTROL3 0x2fb
#define SEA_mmPIPE2_ARBITRATION_CONTROL3 0x2fc
#define SEA_mmPIPE3_ARBITRATION_CONTROL3 0x2fd
#define SEA_mmPIPE4_ARBITRATION_CONTROL3 0x2fe
#define SEA_mmPIPE5_ARBITRATION_CONTROL3 0x2ff
#define SEA_mmDMIF_TEST_DEBUG_INDEX 0x312
#define SEA_mmDMIF_TEST_DEBUG_DATA 0x313
#define SEA_ixDMIF_DEBUG02_CORE0 0x2
#define SEA_ixDMIF_DEBUG02_CORE1 0xa
#define SEA_mmDMIF_ADDR_CALC 0x300
#define SEA_mmDMIF_STATUS2 0x301
#define SEA_mmPIPE0_MAX_REQUESTS 0x302
#define SEA_mmPIPE1_MAX_REQUESTS 0x303
#define SEA_mmPIPE2_MAX_REQUESTS 0x304
#define SEA_mmPIPE3_MAX_REQUESTS 0x305
#define SEA_mmPIPE4_MAX_REQUESTS 0x306
#define SEA_mmPIPE5_MAX_REQUESTS 0x307
#define SEA_mmLOW_POWER_TILING_CONTROL 0x325
#define SEA_mmMCIF_CONTROL 0x314
#define SEA_mmMCIF_WRITE_COMBINE_CONTROL 0x315
#define SEA_mmMCIF_TEST_DEBUG_INDEX 0x316
#define SEA_mmMCIF_TEST_DEBUG_DATA 0x317
#define SEA_ixIDDCCIF02_DBG_DCCIF_C 0x9
#define SEA_ixIDDCCIF04_DBG_DCCIF_E 0xb
#define SEA_ixIDDCCIF05_DBG_DCCIF_F 0xc
#define SEA_mmMCIF_VMID 0x318
#define SEA_mmMCIF_MEM_CONTROL 0x319
#define SEA_mmCC_DC_PIPE_DIS 0x177f
#define SEA_mmMC_DC_INTERFACE_NACK_STATUS 0x31c
#define SEA_mmDC_RBBMIF_RDWR_CNTL1 0x31a
#define SEA_mmDC_RBBMIF_RDWR_CNTL2 0x31d
#define SEA_mmDC_RBBMIF_RDWR_CNTL3 0x311
#define SEA_mmDCI_MEM_PWR_STATE 0x31b
#define SEA_mmDCI_MEM_PWR_STATE2 0x322
#define SEA_mmDCI_CLK_CNTL 0x31e
#define SEA_mmDCCG_VPCLK_CNTL 0x31f
#define SEA_mmDCI_MEM_PWR_CNTL 0x326
#define SEA_mmDC_XDMA_INTERFACE_CNTL 0x327
#define SEA_mmDCI_TEST_DEBUG_INDEX 0x320
#define SEA_mmDCI_TEST_DEBUG_DATA 0x321
#define SEA_mmDCI_DEBUG_CONFIG 0x323
#define SEA_mmPIPE0_DMIF_BUFFER_CONTROL 0x328
#define SEA_mmPIPE1_DMIF_BUFFER_CONTROL 0x330
#define SEA_mmPIPE2_DMIF_BUFFER_CONTROL 0x338
#define SEA_mmPIPE3_DMIF_BUFFER_CONTROL 0x340
#define SEA_mmPIPE4_DMIF_BUFFER_CONTROL 0x348
#define SEA_mmPIPE5_DMIF_BUFFER_CONTROL 0x350
#define SEA_mmMCIF_BUFMGR_SW_CONTROL 0x358
#define SEA_mmMCIF_BUFMGR_STATUS 0x35a
#define SEA_mmMCIF_BUF_PITCH 0x35b
#define SEA_mmMCIF_BUF_1_ADDR_Y_LOW 0x35c
#define SEA_mmMCIF_BUF_2_ADDR_Y_LOW 0x360
#define SEA_mmMCIF_BUF_3_ADDR_Y_LOW 0x364
#define SEA_mmMCIF_BUF_4_ADDR_Y_LOW 0x368
#define SEA_mmMCIF_BUF_1_ADDR_UP 0x35d
#define SEA_mmMCIF_BUF_2_ADDR_UP 0x361
#define SEA_mmMCIF_BUF_3_ADDR_UP 0x365
#define SEA_mmMCIF_BUF_4_ADDR_UP 0x369
#define SEA_mmMCIF_BUF_1_ADDR_C_LOW 0x35e
#define SEA_mmMCIF_BUF_2_ADDR_C_LOW 0x362
#define SEA_mmMCIF_BUF_3_ADDR_C_LOW 0x366
#define SEA_mmMCIF_BUF_4_ADDR_C_LOW 0x36a
#define SEA_mmMCIF_BUF_1_STATUS 0x35f
#define SEA_mmMCIF_BUF_2_STATUS 0x363
#define SEA_mmMCIF_BUF_3_STATUS 0x367
#define SEA_mmMCIF_BUF_4_STATUS 0x36b
#define SEA_mmMCIF_SI_ARBITRATION_CONTROL 0x36c
#define SEA_mmMCIF_URGENCY_WATERMARK 0x36d
#define SEA_mmDC_GENERICA 0x1900
#define SEA_mmDC_GENERICB 0x1901
#define SEA_mmDC_PAD_EXTERN_SIG 0x1902
#define SEA_mmDC_REF_CLK_CNTL 0x1903
#define SEA_mmDC_GPIO_DEBUG 0x1904
#define SEA_mmDCO_MEM_POWER_STATE 0x1906
#define SEA_mmDCO_MEM_POWER_STATE_2 0x193a
#define SEA_mmDCO_LIGHT_SLEEP_DIS 0x1907
#define SEA_mmUNIPHY_IMPCAL_LINKA 0x1908
#define SEA_mmUNIPHY_IMPCAL_LINKB 0x1909
#define SEA_mmUNIPHY_IMPCAL_PERIOD 0x190a
#define SEA_mmAUXP_IMPCAL 0x190b
#define SEA_mmAUXN_IMPCAL 0x190c
#define SEA_mmDCIO_IMPCAL_CNTL_AB 0x190d
#define SEA_mmUNIPHY_IMPCAL_PSW_AB 0x190e
#define SEA_mmUNIPHY_IMPCAL_LINKC 0x190f
#define SEA_mmUNIPHY_IMPCAL_LINKD 0x1910
#define SEA_mmDCIO_IMPCAL_CNTL_CD 0x1911
#define SEA_mmUNIPHY_IMPCAL_PSW_CD 0x1912
#define SEA_mmUNIPHY_IMPCAL_LINKE 0x1913
#define SEA_mmUNIPHY_IMPCAL_LINKF 0x1914
#define SEA_mmDCIO_IMPCAL_CNTL_EF 0x1915
#define SEA_mmUNIPHY_IMPCAL_PSW_EF 0x1916
#define SEA_mmDC_PINSTRAPS 0x1917
#define SEA_mmDC_DVODATA_CONFIG 0x1905
#define SEA_mmLVTMA_PWRSEQ_CNTL 0x1919
#define SEA_mmLVTMA_PWRSEQ_STATE 0x191a
#define SEA_mmLVTMA_PWRSEQ_REF_DIV 0x191b
#define SEA_mmLVTMA_PWRSEQ_DELAY1 0x191c
#define SEA_mmLVTMA_PWRSEQ_DELAY2 0x191d
#define SEA_mmBL_PWM_CNTL 0x191e
#define SEA_mmBL_PWM_CNTL2 0x191f
#define SEA_mmBL_PWM_PERIOD_CNTL 0x1920
#define SEA_mmBL_PWM_GRP1_REG_LOCK 0x1921
#define SEA_mmDCIO_GSL_GENLK_PAD_CNTL 0x1922
#define SEA_mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x1923
#define SEA_mmDCIO_GSL0_CNTL 0x1924
#define SEA_mmDCIO_GSL1_CNTL 0x1925
#define SEA_mmDCIO_GSL2_CNTL 0x1926
#define SEA_mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x1927
#define SEA_mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x1928
#define SEA_mmDC_GPU_TIMER_READ 0x1929
#define SEA_mmDC_GPU_TIMER_READ_CNTL 0x192a
#define SEA_mmDCO_CLK_CNTL 0x192b
#define SEA_mmDCO_CLK_RAMP_CNTL 0x192c
#define SEA_mmDCIO_DEBUG 0x192e
#define SEA_mmDCO_DCFE_EXT_VSYNC_CNTL 0x1937
#define SEA_mmDCIO_TEST_DEBUG_INDEX 0x192f
#define SEA_mmDCIO_TEST_DEBUG_DATA 0x1930
#define SEA_ixDCIO_DEBUG1 0x1
#define SEA_ixDCIO_DEBUG2 0x2
#define SEA_ixDCIO_DEBUG3 0x3
#define SEA_ixDCIO_DEBUG4 0x4
#define SEA_ixDCIO_DEBUG5 0x5
#define SEA_ixDCIO_DEBUG6 0x6
#define SEA_ixDCIO_DEBUG7 0x7
#define SEA_ixDCIO_DEBUG8 0x8
#define SEA_ixDCIO_DEBUG9 0x9
#define SEA_ixDCIO_DEBUGA 0xa
#define SEA_ixDCIO_DEBUGB 0xb
#define SEA_ixDCIO_DEBUGC 0xc
#define SEA_ixDCIO_DEBUGD 0xd
#define SEA_ixDCIO_DEBUGE 0xe
#define SEA_ixDCIO_DEBUGF 0xf
#define SEA_ixDCIO_DEBUG10 0x10
#define SEA_ixDCIO_DEBUG11 0x11
#define SEA_ixDCIO_DEBUG12 0x12
#define SEA_ixDCIO_DEBUG13 0x13
#define SEA_ixDCIO_DEBUG14 0x14
#define SEA_ixDCIO_DEBUG15 0x15
#define SEA_ixDCIO_DEBUG_ID 0x0
#define SEA_mmDC_GPIO_GENERIC_MASK 0x1944
#define SEA_mmDC_GPIO_GENERIC_A 0x1945
#define SEA_mmDC_GPIO_GENERIC_EN 0x1946
#define SEA_mmDC_GPIO_GENERIC_Y 0x1947
#define SEA_mmDC_GPIO_DVODATA_MASK 0x1948
#define SEA_mmDC_GPIO_DVODATA_A 0x1949
#define SEA_mmDC_GPIO_DVODATA_EN 0x194a
#define SEA_mmDC_GPIO_DVODATA_Y 0x194b
#define SEA_mmDC_GPIO_DDC1_MASK 0x194c
#define SEA_mmDC_GPIO_DDC1_A 0x194d
#define SEA_mmDC_GPIO_DDC1_EN 0x194e
#define SEA_mmDC_GPIO_DDC1_Y 0x194f
#define SEA_mmDC_GPIO_DDC2_MASK 0x1950
#define SEA_mmDC_GPIO_DDC2_A 0x1951
#define SEA_mmDC_GPIO_DDC2_EN 0x1952
#define SEA_mmDC_GPIO_DDC2_Y 0x1953
#define SEA_mmDC_GPIO_DDC3_MASK 0x1954
#define SEA_mmDC_GPIO_DDC3_A 0x1955
#define SEA_mmDC_GPIO_DDC3_EN 0x1956
#define SEA_mmDC_GPIO_DDC3_Y 0x1957
#define SEA_mmDC_GPIO_DDC4_MASK 0x1958
#define SEA_mmDC_GPIO_DDC4_A 0x1959
#define SEA_mmDC_GPIO_DDC4_EN 0x195a
#define SEA_mmDC_GPIO_DDC4_Y 0x195b
#define SEA_mmDC_GPIO_DDC5_MASK 0x195c
#define SEA_mmDC_GPIO_DDC5_A 0x195d
#define SEA_mmDC_GPIO_DDC5_EN 0x195e
#define SEA_mmDC_GPIO_DDC5_Y 0x195f
#define SEA_mmDC_GPIO_DDC6_MASK 0x1960
#define SEA_mmDC_GPIO_DDC6_A 0x1961
#define SEA_mmDC_GPIO_DDC6_EN 0x1962
#define SEA_mmDC_GPIO_DDC6_Y 0x1963
#define SEA_mmDC_GPIO_DDCVGA_MASK 0x1970
#define SEA_mmDC_GPIO_DDCVGA_A 0x1971
#define SEA_mmDC_GPIO_DDCVGA_EN 0x1972
#define SEA_mmDC_GPIO_DDCVGA_Y 0x1973
#define SEA_mmDC_GPIO_SYNCA_MASK 0x1964
#define SEA_mmDC_GPIO_SYNCA_A 0x1965
#define SEA_mmDC_GPIO_SYNCA_EN 0x1966
#define SEA_mmDC_GPIO_SYNCA_Y 0x1967
#define SEA_mmDC_GPIO_GENLK_MASK 0x1968
#define SEA_mmDC_GPIO_GENLK_A 0x1969
#define SEA_mmDC_GPIO_GENLK_EN 0x196a
#define SEA_mmDC_GPIO_GENLK_Y 0x196b
#define SEA_mmDC_GPIO_HPD_MASK 0x196c
#define SEA_mmDC_GPIO_HPD_A 0x196d
#define SEA_mmDC_GPIO_HPD_EN 0x196e
#define SEA_mmDC_GPIO_HPD_Y 0x196f
#define SEA_mmDC_GPIO_PWRSEQ_MASK 0x1940
#define SEA_mmDC_GPIO_PWRSEQ_A 0x1941
#define SEA_mmDC_GPIO_PWRSEQ_EN 0x1942
#define SEA_mmDC_GPIO_PWRSEQ_Y 0x1943
#define SEA_mmDC_GPIO_PAD_STRENGTH_1 0x1978
#define SEA_mmDC_GPIO_PAD_STRENGTH_2 0x1979
#define SEA_mmPHY_AUX_CNTL 0x197f
#define SEA_mmDC_GPIO_I2CPAD_A 0x1975
#define SEA_mmDC_GPIO_I2CPAD_EN 0x1976
#define SEA_mmDC_GPIO_I2CPAD_Y 0x1977
#define SEA_mmDC_GPIO_I2CPAD_STRENGTH 0x197a
#define SEA_mmDVO_STRENGTH_CONTROL 0x197b
#define SEA_mmDVO_VREF_CONTROL 0x197c
#define SEA_mmDVO_SKEW_ADJUST 0x197d
#define SEA_mmUNIPHYAB_TPG_CONTROL 0x1931
#define SEA_mmUNIPHYAB_TPG_SEED 0x1932
#define SEA_mmUNIPHYCD_TPG_CONTROL 0x1933
#define SEA_mmUNIPHYCD_TPG_SEED 0x1934
#define SEA_mmUNIPHYEF_TPG_CONTROL 0x1935
#define SEA_mmUNIPHYEF_TPG_SEED 0x1936
#define SEA_mmUNIPHYGH_TPG_CONTROL 0x1938
#define SEA_mmUNIPHYGH_TPG_SEED 0x1939
#define SEA_mmDC_GPIO_I2S_SPDIF_MASK 0x193c
#define SEA_mmDC_GPIO_I2S_SPDIF_A 0x193d
#define SEA_mmDC_GPIO_I2S_SPDIF_EN 0x193e
#define SEA_mmDC_GPIO_I2S_SPDIF_Y 0x193f
#define SEA_mmDC_GPIO_I2S_SPDIF_STRENGTH 0x193b
#define SEA_mmDAC_MACRO_CNTL_RESERVED0 0x19fc
#define SEA_mmDAC_MACRO_CNTL_RESERVED1 0x19fd
#define SEA_mmDAC_MACRO_CNTL_RESERVED2 0x19fe
#define SEA_mmDAC_MACRO_CNTL_RESERVED3 0x19ff
#define SEA_mmUNIPHY_TX_CONTROL1 0x1980
#define SEA_mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1 0x1980
#define SEA_mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1 0x1990
#define SEA_mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1 0x19a0
#define SEA_mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1 0x19b0
#define SEA_mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1 0x19c0
#define SEA_mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1 0x19d0
#define SEA_mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL1 0x4df0
#define SEA_mmUNIPHY_TX_CONTROL2 0x1981
#define SEA_mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2 0x1981
#define SEA_mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2 0x1991
#define SEA_mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2 0x19a1
#define SEA_mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2 0x19b1
#define SEA_mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2 0x19c1
#define SEA_mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2 0x19d1
#define SEA_mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL2 0x4df1
#define SEA_mmUNIPHY_TX_CONTROL3 0x1982
#define SEA_mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3 0x1982
#define SEA_mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3 0x1992
#define SEA_mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3 0x19a2
#define SEA_mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3 0x19b2
#define SEA_mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3 0x19c2
#define SEA_mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3 0x19d2
#define SEA_mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL3 0x4df2
#define SEA_mmUNIPHY_TX_CONTROL4 0x1983
#define SEA_mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4 0x1983
#define SEA_mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4 0x1993
#define SEA_mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4 0x19a3
#define SEA_mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4 0x19b3
#define SEA_mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4 0x19c3
#define SEA_mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4 0x19d3
#define SEA_mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL4 0x4df3
#define SEA_mmUNIPHY_POWER_CONTROL 0x1984
#define SEA_mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL 0x1984
#define SEA_mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL 0x1994
#define SEA_mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL 0x19a4
#define SEA_mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL 0x19b4
#define SEA_mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL 0x19c4
#define SEA_mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL 0x19d4
#define SEA_mmDCIO_UNIPHY6_UNIPHY_POWER_CONTROL 0x4df4
#define SEA_mmUNIPHY_PLL_FBDIV 0x1985
#define SEA_mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV 0x1985
#define SEA_mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV 0x1995
#define SEA_mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV 0x19a5
#define SEA_mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV 0x19b5
#define SEA_mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV 0x19c5
#define SEA_mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV 0x19d5
#define SEA_mmDCIO_UNIPHY6_UNIPHY_PLL_FBDIV 0x4df5
#define SEA_mmUNIPHY_PLL_CONTROL1 0x1986
#define SEA_mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1 0x1986
#define SEA_mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1 0x1996
#define SEA_mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1 0x19a6
#define SEA_mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1 0x19b6
#define SEA_mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1 0x19c6
#define SEA_mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1 0x19d6
#define SEA_mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL1 0x4df6
#define SEA_mmUNIPHY_PLL_CONTROL2 0x1987
#define SEA_mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2 0x1987
#define SEA_mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2 0x1997
#define SEA_mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2 0x19a7
#define SEA_mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2 0x19b7
#define SEA_mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2 0x19c7
#define SEA_mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2 0x19d7
#define SEA_mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL2 0x4df7
#define SEA_mmUNIPHY_PLL_SS_STEP_SIZE 0x1988
#define SEA_mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x1988
#define SEA_mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x1998
#define SEA_mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x19a8
#define SEA_mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x19b8
#define SEA_mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x19c8
#define SEA_mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x19d8
#define SEA_mmDCIO_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE 0x4df8
#define SEA_mmUNIPHY_PLL_SS_CNTL 0x1989
#define SEA_mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x1989
#define SEA_mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x1999
#define SEA_mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x19a9
#define SEA_mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x19b9
#define SEA_mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x19c9
#define SEA_mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x19d9
#define SEA_mmDCIO_UNIPHY6_UNIPHY_PLL_SS_CNTL 0x4df9
#define SEA_mmUNIPHY_DATA_SYNCHRONIZATION 0x198a
#define SEA_mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x198a
#define SEA_mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x199a
#define SEA_mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x19aa
#define SEA_mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x19ba
#define SEA_mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x19ca
#define SEA_mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x19da
#define SEA_mmDCIO_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION 0x4dfa
#define SEA_mmUNIPHY_REG_TEST_OUTPUT 0x198b
#define SEA_mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x198b
#define SEA_mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x199b
#define SEA_mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x19ab
#define SEA_mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x19bb
#define SEA_mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x19cb
#define SEA_mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x19db
#define SEA_mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT 0x4dfb
#define SEA_mmUNIPHY_ANG_BIST_CNTL 0x198c
#define SEA_mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x198c
#define SEA_mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x199c
#define SEA_mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x19ac
#define SEA_mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x19bc
#define SEA_mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x19cc
#define SEA_mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x19dc
#define SEA_mmDCIO_UNIPHY6_UNIPHY_ANG_BIST_CNTL 0x4dfc
#define SEA_mmUNIPHY_LINK_CNTL 0x198d
#define SEA_mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL 0x198d
#define SEA_mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL 0x199d
#define SEA_mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL 0x19ad
#define SEA_mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL 0x19bd
#define SEA_mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL 0x19cd
#define SEA_mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL 0x19dd
#define SEA_mmDCIO_UNIPHY6_UNIPHY_LINK_CNTL 0x4dfd
#define SEA_mmUNIPHY_CHANNEL_XBAR_CNTL 0x198e
#define SEA_mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL 0x198e
#define SEA_mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL 0x199e
#define SEA_mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL 0x19ae
#define SEA_mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL 0x19be
#define SEA_mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL 0x19ce
#define SEA_mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL 0x19de
#define SEA_mmDCIO_UNIPHY6_UNIPHY_CHANNEL_XBAR_CNTL 0x4dfe
#define SEA_mmUNIPHY_REG_TEST_OUTPUT2 0x198f
#define SEA_mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 0x198f
#define SEA_mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 0x199f
#define SEA_mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 0x19af
#define SEA_mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 0x19bf
#define SEA_mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 0x19cf
#define SEA_mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 0x19df
#define SEA_mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 0x4dff
#define SEA_mmGRPH_ENABLE 0x1a00
#define SEA_mmDCP0_GRPH_ENABLE 0x1a00
#define SEA_mmDCP1_GRPH_ENABLE 0x1d00
#define SEA_mmDCP2_GRPH_ENABLE 0x4000
#define SEA_mmDCP3_GRPH_ENABLE 0x4300
#define SEA_mmDCP4_GRPH_ENABLE 0x4600
#define SEA_mmDCP5_GRPH_ENABLE 0x4900
#define SEA_mmGRPH_CONTROL 0x1a01
#define SEA_mmDCP0_GRPH_CONTROL 0x1a01
#define SEA_mmDCP1_GRPH_CONTROL 0x1d01
#define SEA_mmDCP2_GRPH_CONTROL 0x4001
#define SEA_mmDCP3_GRPH_CONTROL 0x4301
#define SEA_mmDCP4_GRPH_CONTROL 0x4601
#define SEA_mmDCP5_GRPH_CONTROL 0x4901
#define SEA_mmGRPH_LUT_10BIT_BYPASS 0x1a02
#define SEA_mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02
#define SEA_mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1d02
#define SEA_mmDCP2_GRPH_LUT_10BIT_BYPASS 0x4002
#define SEA_mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4302
#define SEA_mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4602
#define SEA_mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4902
#define SEA_mmGRPH_SWAP_CNTL 0x1a03
#define SEA_mmDCP0_GRPH_SWAP_CNTL 0x1a03
#define SEA_mmDCP1_GRPH_SWAP_CNTL 0x1d03
#define SEA_mmDCP2_GRPH_SWAP_CNTL 0x4003
#define SEA_mmDCP3_GRPH_SWAP_CNTL 0x4303
#define SEA_mmDCP4_GRPH_SWAP_CNTL 0x4603
#define SEA_mmDCP5_GRPH_SWAP_CNTL 0x4903
#define SEA_mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04
#define SEA_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04
#define SEA_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1d04
#define SEA_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004
#define SEA_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4304
#define SEA_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4604
#define SEA_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4904
#define SEA_mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05
#define SEA_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05
#define SEA_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1d05
#define SEA_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005
#define SEA_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4305
#define SEA_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4605
#define SEA_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4905
#define SEA_mmGRPH_PITCH 0x1a06
#define SEA_mmDCP0_GRPH_PITCH 0x1a06
#define SEA_mmDCP1_GRPH_PITCH 0x1d06
#define SEA_mmDCP2_GRPH_PITCH 0x4006
#define SEA_mmDCP3_GRPH_PITCH 0x4306
#define SEA_mmDCP4_GRPH_PITCH 0x4606
#define SEA_mmDCP5_GRPH_PITCH 0x4906
#define SEA_mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07
#define SEA_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07
#define SEA_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1d07
#define SEA_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007
#define SEA_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4307
#define SEA_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4607
#define SEA_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4907
#define SEA_mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08
#define SEA_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08
#define SEA_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1d08
#define SEA_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008
#define SEA_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4308
#define SEA_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4608
#define SEA_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4908
#define SEA_mmGRPH_SURFACE_OFFSET_X 0x1a09
#define SEA_mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09
#define SEA_mmDCP1_GRPH_SURFACE_OFFSET_X 0x1d09
#define SEA_mmDCP2_GRPH_SURFACE_OFFSET_X 0x4009
#define SEA_mmDCP3_GRPH_SURFACE_OFFSET_X 0x4309
#define SEA_mmDCP4_GRPH_SURFACE_OFFSET_X 0x4609
#define SEA_mmDCP5_GRPH_SURFACE_OFFSET_X 0x4909
#define SEA_mmGRPH_SURFACE_OFFSET_Y 0x1a0a
#define SEA_mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a
#define SEA_mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1d0a
#define SEA_mmDCP2_GRPH_SURFACE_OFFSET_Y 0x400a
#define SEA_mmDCP3_GRPH_SURFACE_OFFSET_Y 0x430a
#define SEA_mmDCP4_GRPH_SURFACE_OFFSET_Y 0x460a
#define SEA_mmDCP5_GRPH_SURFACE_OFFSET_Y 0x490a
#define SEA_mmGRPH_X_START 0x1a0b
#define SEA_mmDCP0_GRPH_X_START 0x1a0b
#define SEA_mmDCP1_GRPH_X_START 0x1d0b
#define SEA_mmDCP2_GRPH_X_START 0x400b
#define SEA_mmDCP3_GRPH_X_START 0x430b
#define SEA_mmDCP4_GRPH_X_START 0x460b
#define SEA_mmDCP5_GRPH_X_START 0x490b
#define SEA_mmGRPH_Y_START 0x1a0c
#define SEA_mmDCP0_GRPH_Y_START 0x1a0c
#define SEA_mmDCP1_GRPH_Y_START 0x1d0c
#define SEA_mmDCP2_GRPH_Y_START 0x400c
#define SEA_mmDCP3_GRPH_Y_START 0x430c
#define SEA_mmDCP4_GRPH_Y_START 0x460c
#define SEA_mmDCP5_GRPH_Y_START 0x490c
#define SEA_mmGRPH_X_END 0x1a0d
#define SEA_mmDCP0_GRPH_X_END 0x1a0d
#define SEA_mmDCP1_GRPH_X_END 0x1d0d
#define SEA_mmDCP2_GRPH_X_END 0x400d
#define SEA_mmDCP3_GRPH_X_END 0x430d
#define SEA_mmDCP4_GRPH_X_END 0x460d
#define SEA_mmDCP5_GRPH_X_END 0x490d
#define SEA_mmGRPH_Y_END 0x1a0e
#define SEA_mmDCP0_GRPH_Y_END 0x1a0e
#define SEA_mmDCP1_GRPH_Y_END 0x1d0e
#define SEA_mmDCP2_GRPH_Y_END 0x400e
#define SEA_mmDCP3_GRPH_Y_END 0x430e
#define SEA_mmDCP4_GRPH_Y_END 0x460e
#define SEA_mmDCP5_GRPH_Y_END 0x490e
#define SEA_mmINPUT_GAMMA_CONTROL 0x1a10
#define SEA_mmDCP0_INPUT_GAMMA_CONTROL 0x1a10
#define SEA_mmDCP1_INPUT_GAMMA_CONTROL 0x1d10
#define SEA_mmDCP2_INPUT_GAMMA_CONTROL 0x4010
#define SEA_mmDCP3_INPUT_GAMMA_CONTROL 0x4310
#define SEA_mmDCP4_INPUT_GAMMA_CONTROL 0x4610
#define SEA_mmDCP5_INPUT_GAMMA_CONTROL 0x4910
#define SEA_mmGRPH_UPDATE 0x1a11
#define SEA_mmDCP0_GRPH_UPDATE 0x1a11
#define SEA_mmDCP1_GRPH_UPDATE 0x1d11
#define SEA_mmDCP2_GRPH_UPDATE 0x4011
#define SEA_mmDCP3_GRPH_UPDATE 0x4311
#define SEA_mmDCP4_GRPH_UPDATE 0x4611
#define SEA_mmDCP5_GRPH_UPDATE 0x4911
#define SEA_mmGRPH_FLIP_CONTROL 0x1a12
#define SEA_mmDCP0_GRPH_FLIP_CONTROL 0x1a12
#define SEA_mmDCP1_GRPH_FLIP_CONTROL 0x1d12
#define SEA_mmDCP2_GRPH_FLIP_CONTROL 0x4012
#define SEA_mmDCP3_GRPH_FLIP_CONTROL 0x4312
#define SEA_mmDCP4_GRPH_FLIP_CONTROL 0x4612
#define SEA_mmDCP5_GRPH_FLIP_CONTROL 0x4912
#define SEA_mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13
#define SEA_mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13
#define SEA_mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1d13
#define SEA_mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x4013
#define SEA_mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4313
#define SEA_mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4613
#define SEA_mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4913
#define SEA_mmGRPH_DFQ_CONTROL 0x1a14
#define SEA_mmDCP0_GRPH_DFQ_CONTROL 0x1a14
#define SEA_mmDCP1_GRPH_DFQ_CONTROL 0x1d14
#define SEA_mmDCP2_GRPH_DFQ_CONTROL 0x4014
#define SEA_mmDCP3_GRPH_DFQ_CONTROL 0x4314
#define SEA_mmDCP4_GRPH_DFQ_CONTROL 0x4614
#define SEA_mmDCP5_GRPH_DFQ_CONTROL 0x4914
#define SEA_mmGRPH_DFQ_STATUS 0x1a15
#define SEA_mmDCP0_GRPH_DFQ_STATUS 0x1a15
#define SEA_mmDCP1_GRPH_DFQ_STATUS 0x1d15
#define SEA_mmDCP2_GRPH_DFQ_STATUS 0x4015
#define SEA_mmDCP3_GRPH_DFQ_STATUS 0x4315
#define SEA_mmDCP4_GRPH_DFQ_STATUS 0x4615
#define SEA_mmDCP5_GRPH_DFQ_STATUS 0x4915
#define SEA_mmGRPH_INTERRUPT_STATUS 0x1a16
#define SEA_mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16
#define SEA_mmDCP1_GRPH_INTERRUPT_STATUS 0x1d16
#define SEA_mmDCP2_GRPH_INTERRUPT_STATUS 0x4016
#define SEA_mmDCP3_GRPH_INTERRUPT_STATUS 0x4316
#define SEA_mmDCP4_GRPH_INTERRUPT_STATUS 0x4616
#define SEA_mmDCP5_GRPH_INTERRUPT_STATUS 0x4916
#define SEA_mmGRPH_INTERRUPT_CONTROL 0x1a17
#define SEA_mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17
#define SEA_mmDCP1_GRPH_INTERRUPT_CONTROL 0x1d17
#define SEA_mmDCP2_GRPH_INTERRUPT_CONTROL 0x4017
#define SEA_mmDCP3_GRPH_INTERRUPT_CONTROL 0x4317
#define SEA_mmDCP4_GRPH_INTERRUPT_CONTROL 0x4617
#define SEA_mmDCP5_GRPH_INTERRUPT_CONTROL 0x4917
#define SEA_mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18
#define SEA_mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18
#define SEA_mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1d18
#define SEA_mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018
#define SEA_mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4318
#define SEA_mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4618
#define SEA_mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4918
#define SEA_mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19
#define SEA_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19
#define SEA_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1d19
#define SEA_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019
#define SEA_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4319
#define SEA_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4619
#define SEA_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4919
#define SEA_mmGRPH_COMPRESS_PITCH 0x1a1a
#define SEA_mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a
#define SEA_mmDCP1_GRPH_COMPRESS_PITCH 0x1d1a
#define SEA_mmDCP2_GRPH_COMPRESS_PITCH 0x401a
#define SEA_mmDCP3_GRPH_COMPRESS_PITCH 0x431a
#define SEA_mmDCP4_GRPH_COMPRESS_PITCH 0x461a
#define SEA_mmDCP5_GRPH_COMPRESS_PITCH 0x491a
#define SEA_mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b
#define SEA_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b
#define SEA_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1d1b
#define SEA_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b
#define SEA_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x431b
#define SEA_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x461b
#define SEA_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x491b
#define SEA_mmOVL_ENABLE 0x1a1c
#define SEA_mmDCP0_OVL_ENABLE 0x1a1c
#define SEA_mmDCP1_OVL_ENABLE 0x1d1c
#define SEA_mmDCP2_OVL_ENABLE 0x401c
#define SEA_mmDCP3_OVL_ENABLE 0x431c
#define SEA_mmDCP4_OVL_ENABLE 0x461c
#define SEA_mmDCP5_OVL_ENABLE 0x491c
#define SEA_mmOVL_CONTROL1 0x1a1d
#define SEA_mmDCP0_OVL_CONTROL1 0x1a1d
#define SEA_mmDCP1_OVL_CONTROL1 0x1d1d
#define SEA_mmDCP2_OVL_CONTROL1 0x401d
#define SEA_mmDCP3_OVL_CONTROL1 0x431d
#define SEA_mmDCP4_OVL_CONTROL1 0x461d
#define SEA_mmDCP5_OVL_CONTROL1 0x491d
#define SEA_mmOVL_CONTROL2 0x1a1e
#define SEA_mmDCP0_OVL_CONTROL2 0x1a1e
#define SEA_mmDCP1_OVL_CONTROL2 0x1d1e
#define SEA_mmDCP2_OVL_CONTROL2 0x401e
#define SEA_mmDCP3_OVL_CONTROL2 0x431e
#define SEA_mmDCP4_OVL_CONTROL2 0x461e
#define SEA_mmDCP5_OVL_CONTROL2 0x491e
#define SEA_mmOVL_SWAP_CNTL 0x1a1f
#define SEA_mmDCP0_OVL_SWAP_CNTL 0x1a1f
#define SEA_mmDCP1_OVL_SWAP_CNTL 0x1d1f
#define SEA_mmDCP2_OVL_SWAP_CNTL 0x401f
#define SEA_mmDCP3_OVL_SWAP_CNTL 0x431f
#define SEA_mmDCP4_OVL_SWAP_CNTL 0x461f
#define SEA_mmDCP5_OVL_SWAP_CNTL 0x491f
#define SEA_mmOVL_SURFACE_ADDRESS 0x1a20
#define SEA_mmDCP0_OVL_SURFACE_ADDRESS 0x1a20
#define SEA_mmDCP1_OVL_SURFACE_ADDRESS 0x1d20
#define SEA_mmDCP2_OVL_SURFACE_ADDRESS 0x4020
#define SEA_mmDCP3_OVL_SURFACE_ADDRESS 0x4320
#define SEA_mmDCP4_OVL_SURFACE_ADDRESS 0x4620
#define SEA_mmDCP5_OVL_SURFACE_ADDRESS 0x4920
#define SEA_mmOVL_PITCH 0x1a21
#define SEA_mmDCP0_OVL_PITCH 0x1a21
#define SEA_mmDCP1_OVL_PITCH 0x1d21
#define SEA_mmDCP2_OVL_PITCH 0x4021
#define SEA_mmDCP3_OVL_PITCH 0x4321
#define SEA_mmDCP4_OVL_PITCH 0x4621
#define SEA_mmDCP5_OVL_PITCH 0x4921
#define SEA_mmOVL_SURFACE_ADDRESS_HIGH 0x1a22
#define SEA_mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0x1a22
#define SEA_mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0x1d22
#define SEA_mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0x4022
#define SEA_mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0x4322
#define SEA_mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0x4622
#define SEA_mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0x4922
#define SEA_mmOVL_SURFACE_OFFSET_X 0x1a23
#define SEA_mmDCP0_OVL_SURFACE_OFFSET_X 0x1a23
#define SEA_mmDCP1_OVL_SURFACE_OFFSET_X 0x1d23
#define SEA_mmDCP2_OVL_SURFACE_OFFSET_X 0x4023
#define SEA_mmDCP3_OVL_SURFACE_OFFSET_X 0x4323
#define SEA_mmDCP4_OVL_SURFACE_OFFSET_X 0x4623
#define SEA_mmDCP5_OVL_SURFACE_OFFSET_X 0x4923
#define SEA_mmOVL_SURFACE_OFFSET_Y 0x1a24
#define SEA_mmDCP0_OVL_SURFACE_OFFSET_Y 0x1a24
#define SEA_mmDCP1_OVL_SURFACE_OFFSET_Y 0x1d24
#define SEA_mmDCP2_OVL_SURFACE_OFFSET_Y 0x4024
#define SEA_mmDCP3_OVL_SURFACE_OFFSET_Y 0x4324
#define SEA_mmDCP4_OVL_SURFACE_OFFSET_Y 0x4624
#define SEA_mmDCP5_OVL_SURFACE_OFFSET_Y 0x4924
#define SEA_mmOVL_START 0x1a25
#define SEA_mmDCP0_OVL_START 0x1a25
#define SEA_mmDCP1_OVL_START 0x1d25
#define SEA_mmDCP2_OVL_START 0x4025
#define SEA_mmDCP3_OVL_START 0x4325
#define SEA_mmDCP4_OVL_START 0x4625
#define SEA_mmDCP5_OVL_START 0x4925
#define SEA_mmOVL_END 0x1a26
#define SEA_mmDCP0_OVL_END 0x1a26
#define SEA_mmDCP1_OVL_END 0x1d26
#define SEA_mmDCP2_OVL_END 0x4026
#define SEA_mmDCP3_OVL_END 0x4326
#define SEA_mmDCP4_OVL_END 0x4626
#define SEA_mmDCP5_OVL_END 0x4926
#define SEA_mmOVL_UPDATE 0x1a27
#define SEA_mmDCP0_OVL_UPDATE 0x1a27
#define SEA_mmDCP1_OVL_UPDATE 0x1d27
#define SEA_mmDCP2_OVL_UPDATE 0x4027
#define SEA_mmDCP3_OVL_UPDATE 0x4327
#define SEA_mmDCP4_OVL_UPDATE 0x4627
#define SEA_mmDCP5_OVL_UPDATE 0x4927
#define SEA_mmOVL_SURFACE_ADDRESS_INUSE 0x1a28
#define SEA_mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0x1a28
#define SEA_mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0x1d28
#define SEA_mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0x4028
#define SEA_mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0x4328
#define SEA_mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0x4628
#define SEA_mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0x4928
#define SEA_mmOVL_DFQ_CONTROL 0x1a29
#define SEA_mmDCP0_OVL_DFQ_CONTROL 0x1a29
#define SEA_mmDCP1_OVL_DFQ_CONTROL 0x1d29
#define SEA_mmDCP2_OVL_DFQ_CONTROL 0x4029
#define SEA_mmDCP3_OVL_DFQ_CONTROL 0x4329
#define SEA_mmDCP4_OVL_DFQ_CONTROL 0x4629
#define SEA_mmDCP5_OVL_DFQ_CONTROL 0x4929
#define SEA_mmOVL_DFQ_STATUS 0x1a2a
#define SEA_mmDCP0_OVL_DFQ_STATUS 0x1a2a
#define SEA_mmDCP1_OVL_DFQ_STATUS 0x1d2a
#define SEA_mmDCP2_OVL_DFQ_STATUS 0x402a
#define SEA_mmDCP3_OVL_DFQ_STATUS 0x432a
#define SEA_mmDCP4_OVL_DFQ_STATUS 0x462a
#define SEA_mmDCP5_OVL_DFQ_STATUS 0x492a
#define SEA_mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b
#define SEA_mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b
#define SEA_mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1d2b
#define SEA_mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x402b
#define SEA_mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x432b
#define SEA_mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x462b
#define SEA_mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x492b
#define SEA_mmOVLSCL_EDGE_PIXEL_CNTL 0x1a2c
#define SEA_mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0x1a2c
#define SEA_mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0x1d2c
#define SEA_mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0x402c
#define SEA_mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0x432c
#define SEA_mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0x462c
#define SEA_mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0x492c
#define SEA_mmPRESCALE_GRPH_CONTROL 0x1a2d
#define SEA_mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d
#define SEA_mmDCP1_PRESCALE_GRPH_CONTROL 0x1d2d
#define SEA_mmDCP2_PRESCALE_GRPH_CONTROL 0x402d
#define SEA_mmDCP3_PRESCALE_GRPH_CONTROL 0x432d
#define SEA_mmDCP4_PRESCALE_GRPH_CONTROL 0x462d
#define SEA_mmDCP5_PRESCALE_GRPH_CONTROL 0x492d
#define SEA_mmPRESCALE_VALUES_GRPH_R 0x1a2e
#define SEA_mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e
#define SEA_mmDCP1_PRESCALE_VALUES_GRPH_R 0x1d2e
#define SEA_mmDCP2_PRESCALE_VALUES_GRPH_R 0x402e
#define SEA_mmDCP3_PRESCALE_VALUES_GRPH_R 0x432e
#define SEA_mmDCP4_PRESCALE_VALUES_GRPH_R 0x462e
#define SEA_mmDCP5_PRESCALE_VALUES_GRPH_R 0x492e
#define SEA_mmPRESCALE_VALUES_GRPH_G 0x1a2f
#define SEA_mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f
#define SEA_mmDCP1_PRESCALE_VALUES_GRPH_G 0x1d2f
#define SEA_mmDCP2_PRESCALE_VALUES_GRPH_G 0x402f
#define SEA_mmDCP3_PRESCALE_VALUES_GRPH_G 0x432f
#define SEA_mmDCP4_PRESCALE_VALUES_GRPH_G 0x462f
#define SEA_mmDCP5_PRESCALE_VALUES_GRPH_G 0x492f
#define SEA_mmPRESCALE_VALUES_GRPH_B 0x1a30
#define SEA_mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30
#define SEA_mmDCP1_PRESCALE_VALUES_GRPH_B 0x1d30
#define SEA_mmDCP2_PRESCALE_VALUES_GRPH_B 0x4030
#define SEA_mmDCP3_PRESCALE_VALUES_GRPH_B 0x4330
#define SEA_mmDCP4_PRESCALE_VALUES_GRPH_B 0x4630
#define SEA_mmDCP5_PRESCALE_VALUES_GRPH_B 0x4930
#define SEA_mmPRESCALE_OVL_CONTROL 0x1a31
#define SEA_mmDCP0_PRESCALE_OVL_CONTROL 0x1a31
#define SEA_mmDCP1_PRESCALE_OVL_CONTROL 0x1d31
#define SEA_mmDCP2_PRESCALE_OVL_CONTROL 0x4031
#define SEA_mmDCP3_PRESCALE_OVL_CONTROL 0x4331
#define SEA_mmDCP4_PRESCALE_OVL_CONTROL 0x4631
#define SEA_mmDCP5_PRESCALE_OVL_CONTROL 0x4931
#define SEA_mmPRESCALE_VALUES_OVL_CB 0x1a32
#define SEA_mmDCP0_PRESCALE_VALUES_OVL_CB 0x1a32
#define SEA_mmDCP1_PRESCALE_VALUES_OVL_CB 0x1d32
#define SEA_mmDCP2_PRESCALE_VALUES_OVL_CB 0x4032
#define SEA_mmDCP3_PRESCALE_VALUES_OVL_CB 0x4332
#define SEA_mmDCP4_PRESCALE_VALUES_OVL_CB 0x4632
#define SEA_mmDCP5_PRESCALE_VALUES_OVL_CB 0x4932
#define SEA_mmPRESCALE_VALUES_OVL_Y 0x1a33
#define SEA_mmDCP0_PRESCALE_VALUES_OVL_Y 0x1a33
#define SEA_mmDCP1_PRESCALE_VALUES_OVL_Y 0x1d33
#define SEA_mmDCP2_PRESCALE_VALUES_OVL_Y 0x4033
#define SEA_mmDCP3_PRESCALE_VALUES_OVL_Y 0x4333
#define SEA_mmDCP4_PRESCALE_VALUES_OVL_Y 0x4633
#define SEA_mmDCP5_PRESCALE_VALUES_OVL_Y 0x4933
#define SEA_mmPRESCALE_VALUES_OVL_CR 0x1a34
#define SEA_mmDCP0_PRESCALE_VALUES_OVL_CR 0x1a34
#define SEA_mmDCP1_PRESCALE_VALUES_OVL_CR 0x1d34
#define SEA_mmDCP2_PRESCALE_VALUES_OVL_CR 0x4034
#define SEA_mmDCP3_PRESCALE_VALUES_OVL_CR 0x4334
#define SEA_mmDCP4_PRESCALE_VALUES_OVL_CR 0x4634
#define SEA_mmDCP5_PRESCALE_VALUES_OVL_CR 0x4934
#define SEA_mmINPUT_CSC_CONTROL 0x1a35
#define SEA_mmDCP0_INPUT_CSC_CONTROL 0x1a35
#define SEA_mmDCP1_INPUT_CSC_CONTROL 0x1d35
#define SEA_mmDCP2_INPUT_CSC_CONTROL 0x4035
#define SEA_mmDCP3_INPUT_CSC_CONTROL 0x4335
#define SEA_mmDCP4_INPUT_CSC_CONTROL 0x4635
#define SEA_mmDCP5_INPUT_CSC_CONTROL 0x4935
#define SEA_mmINPUT_CSC_C11_C12 0x1a36
#define SEA_mmDCP0_INPUT_CSC_C11_C12 0x1a36
#define SEA_mmDCP1_INPUT_CSC_C11_C12 0x1d36
#define SEA_mmDCP2_INPUT_CSC_C11_C12 0x4036
#define SEA_mmDCP3_INPUT_CSC_C11_C12 0x4336
#define SEA_mmDCP4_INPUT_CSC_C11_C12 0x4636
#define SEA_mmDCP5_INPUT_CSC_C11_C12 0x4936
#define SEA_mmINPUT_CSC_C13_C14 0x1a37
#define SEA_mmDCP0_INPUT_CSC_C13_C14 0x1a37
#define SEA_mmDCP1_INPUT_CSC_C13_C14 0x1d37
#define SEA_mmDCP2_INPUT_CSC_C13_C14 0x4037
#define SEA_mmDCP3_INPUT_CSC_C13_C14 0x4337
#define SEA_mmDCP4_INPUT_CSC_C13_C14 0x4637
#define SEA_mmDCP5_INPUT_CSC_C13_C14 0x4937
#define SEA_mmINPUT_CSC_C21_C22 0x1a38
#define SEA_mmDCP0_INPUT_CSC_C21_C22 0x1a38
#define SEA_mmDCP1_INPUT_CSC_C21_C22 0x1d38
#define SEA_mmDCP2_INPUT_CSC_C21_C22 0x4038
#define SEA_mmDCP3_INPUT_CSC_C21_C22 0x4338
#define SEA_mmDCP4_INPUT_CSC_C21_C22 0x4638
#define SEA_mmDCP5_INPUT_CSC_C21_C22 0x4938
#define SEA_mmINPUT_CSC_C23_C24 0x1a39
#define SEA_mmDCP0_INPUT_CSC_C23_C24 0x1a39
#define SEA_mmDCP1_INPUT_CSC_C23_C24 0x1d39
#define SEA_mmDCP2_INPUT_CSC_C23_C24 0x4039
#define SEA_mmDCP3_INPUT_CSC_C23_C24 0x4339
#define SEA_mmDCP4_INPUT_CSC_C23_C24 0x4639
#define SEA_mmDCP5_INPUT_CSC_C23_C24 0x4939
#define SEA_mmINPUT_CSC_C31_C32 0x1a3a
#define SEA_mmDCP0_INPUT_CSC_C31_C32 0x1a3a
#define SEA_mmDCP1_INPUT_CSC_C31_C32 0x1d3a
#define SEA_mmDCP2_INPUT_CSC_C31_C32 0x403a
#define SEA_mmDCP3_INPUT_CSC_C31_C32 0x433a
#define SEA_mmDCP4_INPUT_CSC_C31_C32 0x463a
#define SEA_mmDCP5_INPUT_CSC_C31_C32 0x493a
#define SEA_mmINPUT_CSC_C33_C34 0x1a3b
#define SEA_mmDCP0_INPUT_CSC_C33_C34 0x1a3b
#define SEA_mmDCP1_INPUT_CSC_C33_C34 0x1d3b
#define SEA_mmDCP2_INPUT_CSC_C33_C34 0x403b
#define SEA_mmDCP3_INPUT_CSC_C33_C34 0x433b
#define SEA_mmDCP4_INPUT_CSC_C33_C34 0x463b
#define SEA_mmDCP5_INPUT_CSC_C33_C34 0x493b
#define SEA_mmOUTPUT_CSC_CONTROL 0x1a3c
#define SEA_mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c
#define SEA_mmDCP1_OUTPUT_CSC_CONTROL 0x1d3c
#define SEA_mmDCP2_OUTPUT_CSC_CONTROL 0x403c
#define SEA_mmDCP3_OUTPUT_CSC_CONTROL 0x433c
#define SEA_mmDCP4_OUTPUT_CSC_CONTROL 0x463c
#define SEA_mmDCP5_OUTPUT_CSC_CONTROL 0x493c
#define SEA_mmOUTPUT_CSC_C11_C12 0x1a3d
#define SEA_mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d
#define SEA_mmDCP1_OUTPUT_CSC_C11_C12 0x1d3d
#define SEA_mmDCP2_OUTPUT_CSC_C11_C12 0x403d
#define SEA_mmDCP3_OUTPUT_CSC_C11_C12 0x433d
#define SEA_mmDCP4_OUTPUT_CSC_C11_C12 0x463d
#define SEA_mmDCP5_OUTPUT_CSC_C11_C12 0x493d
#define SEA_mmOUTPUT_CSC_C13_C14 0x1a3e
#define SEA_mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e
#define SEA_mmDCP1_OUTPUT_CSC_C13_C14 0x1d3e
#define SEA_mmDCP2_OUTPUT_CSC_C13_C14 0x403e
#define SEA_mmDCP3_OUTPUT_CSC_C13_C14 0x433e
#define SEA_mmDCP4_OUTPUT_CSC_C13_C14 0x463e
#define SEA_mmDCP5_OUTPUT_CSC_C13_C14 0x493e
#define SEA_mmOUTPUT_CSC_C21_C22 0x1a3f
#define SEA_mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f
#define SEA_mmDCP1_OUTPUT_CSC_C21_C22 0x1d3f
#define SEA_mmDCP2_OUTPUT_CSC_C21_C22 0x403f
#define SEA_mmDCP3_OUTPUT_CSC_C21_C22 0x433f
#define SEA_mmDCP4_OUTPUT_CSC_C21_C22 0x463f
#define SEA_mmDCP5_OUTPUT_CSC_C21_C22 0x493f
#define SEA_mmOUTPUT_CSC_C23_C24 0x1a40
#define SEA_mmDCP0_OUTPUT_CSC_C23_C24 0x1a40
#define SEA_mmDCP1_OUTPUT_CSC_C23_C24 0x1d40
#define SEA_mmDCP2_OUTPUT_CSC_C23_C24 0x4040
#define SEA_mmDCP3_OUTPUT_CSC_C23_C24 0x4340
#define SEA_mmDCP4_OUTPUT_CSC_C23_C24 0x4640
#define SEA_mmDCP5_OUTPUT_CSC_C23_C24 0x4940
#define SEA_mmOUTPUT_CSC_C31_C32 0x1a41
#define SEA_mmDCP0_OUTPUT_CSC_C31_C32 0x1a41
#define SEA_mmDCP1_OUTPUT_CSC_C31_C32 0x1d41
#define SEA_mmDCP2_OUTPUT_CSC_C31_C32 0x4041
#define SEA_mmDCP3_OUTPUT_CSC_C31_C32 0x4341
#define SEA_mmDCP4_OUTPUT_CSC_C31_C32 0x4641
#define SEA_mmDCP5_OUTPUT_CSC_C31_C32 0x4941
#define SEA_mmOUTPUT_CSC_C33_C34 0x1a42
#define SEA_mmDCP0_OUTPUT_CSC_C33_C34 0x1a42
#define SEA_mmDCP1_OUTPUT_CSC_C33_C34 0x1d42
#define SEA_mmDCP2_OUTPUT_CSC_C33_C34 0x4042
#define SEA_mmDCP3_OUTPUT_CSC_C33_C34 0x4342
#define SEA_mmDCP4_OUTPUT_CSC_C33_C34 0x4642
#define SEA_mmDCP5_OUTPUT_CSC_C33_C34 0x4942
#define SEA_mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43
#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43
#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1d43
#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x4043
#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4343
#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4643
#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4943
#define SEA_mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44
#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44
#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1d44
#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x4044
#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4344
#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4644
#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4944
#define SEA_mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45
#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45
#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1d45
#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x4045
#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4345
#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4645
#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4945
#define SEA_mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46
#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46
#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1d46
#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x4046
#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4346
#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4646
#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4946
#define SEA_mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47
#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47
#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1d47
#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x4047
#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4347
#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4647
#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4947
#define SEA_mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48
#define SEA_mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48
#define SEA_mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1d48
#define SEA_mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x4048
#define SEA_mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4348
#define SEA_mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4648
#define SEA_mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4948
#define SEA_mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49
#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49
#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1d49
#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x4049
#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4349
#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4649
#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4949
#define SEA_mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a
#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a
#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1d4a
#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x404a
#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x434a
#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x464a
#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x494a
#define SEA_mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b
#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b
#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1d4b
#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x404b
#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x434b
#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x464b
#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x494b
#define SEA_mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c
#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c
#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1d4c
#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x404c
#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x434c
#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x464c
#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x494c
#define SEA_mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d
#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d
#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1d4d
#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x404d
#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x434d
#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x464d
#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x494d
#define SEA_mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e
#define SEA_mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e
#define SEA_mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1d4e
#define SEA_mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x404e
#define SEA_mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x434e
#define SEA_mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x464e
#define SEA_mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x494e
#define SEA_mmDENORM_CONTROL 0x1a50
#define SEA_mmDCP0_DENORM_CONTROL 0x1a50
#define SEA_mmDCP1_DENORM_CONTROL 0x1d50
#define SEA_mmDCP2_DENORM_CONTROL 0x4050
#define SEA_mmDCP3_DENORM_CONTROL 0x4350
#define SEA_mmDCP4_DENORM_CONTROL 0x4650
#define SEA_mmDCP5_DENORM_CONTROL 0x4950
#define SEA_mmOUT_ROUND_CONTROL 0x1a51
#define SEA_mmDCP0_OUT_ROUND_CONTROL 0x1a51
#define SEA_mmDCP1_OUT_ROUND_CONTROL 0x1d51
#define SEA_mmDCP2_OUT_ROUND_CONTROL 0x4051
#define SEA_mmDCP3_OUT_ROUND_CONTROL 0x4351
#define SEA_mmDCP4_OUT_ROUND_CONTROL 0x4651
#define SEA_mmDCP5_OUT_ROUND_CONTROL 0x4951
#define SEA_mmOUT_CLAMP_CONTROL_R_CR 0x1a52
#define SEA_mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52
#define SEA_mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1d52
#define SEA_mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x4052
#define SEA_mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4352
#define SEA_mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4652
#define SEA_mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4952
#define SEA_mmOUT_CLAMP_CONTROL_G_Y 0x1a9c
#define SEA_mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c
#define SEA_mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1d9c
#define SEA_mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x409c
#define SEA_mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x439c
#define SEA_mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x469c
#define SEA_mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x499c
#define SEA_mmOUT_CLAMP_CONTROL_B_CB 0x1a9d
#define SEA_mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d
#define SEA_mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1d9d
#define SEA_mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x409d
#define SEA_mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x439d
#define SEA_mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x469d
#define SEA_mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x499d
#define SEA_mmKEY_CONTROL 0x1a53
#define SEA_mmDCP0_KEY_CONTROL 0x1a53
#define SEA_mmDCP1_KEY_CONTROL 0x1d53
#define SEA_mmDCP2_KEY_CONTROL 0x4053
#define SEA_mmDCP3_KEY_CONTROL 0x4353
#define SEA_mmDCP4_KEY_CONTROL 0x4653
#define SEA_mmDCP5_KEY_CONTROL 0x4953
#define SEA_mmKEY_RANGE_ALPHA 0x1a54
#define SEA_mmDCP0_KEY_RANGE_ALPHA 0x1a54
#define SEA_mmDCP1_KEY_RANGE_ALPHA 0x1d54
#define SEA_mmDCP2_KEY_RANGE_ALPHA 0x4054
#define SEA_mmDCP3_KEY_RANGE_ALPHA 0x4354
#define SEA_mmDCP4_KEY_RANGE_ALPHA 0x4654
#define SEA_mmDCP5_KEY_RANGE_ALPHA 0x4954
#define SEA_mmKEY_RANGE_RED 0x1a55
#define SEA_mmDCP0_KEY_RANGE_RED 0x1a55
#define SEA_mmDCP1_KEY_RANGE_RED 0x1d55
#define SEA_mmDCP2_KEY_RANGE_RED 0x4055
#define SEA_mmDCP3_KEY_RANGE_RED 0x4355
#define SEA_mmDCP4_KEY_RANGE_RED 0x4655
#define SEA_mmDCP5_KEY_RANGE_RED 0x4955
#define SEA_mmKEY_RANGE_GREEN 0x1a56
#define SEA_mmDCP0_KEY_RANGE_GREEN 0x1a56
#define SEA_mmDCP1_KEY_RANGE_GREEN 0x1d56
#define SEA_mmDCP2_KEY_RANGE_GREEN 0x4056
#define SEA_mmDCP3_KEY_RANGE_GREEN 0x4356
#define SEA_mmDCP4_KEY_RANGE_GREEN 0x4656
#define SEA_mmDCP5_KEY_RANGE_GREEN 0x4956
#define SEA_mmKEY_RANGE_BLUE 0x1a57
#define SEA_mmDCP0_KEY_RANGE_BLUE 0x1a57
#define SEA_mmDCP1_KEY_RANGE_BLUE 0x1d57
#define SEA_mmDCP2_KEY_RANGE_BLUE 0x4057
#define SEA_mmDCP3_KEY_RANGE_BLUE 0x4357
#define SEA_mmDCP4_KEY_RANGE_BLUE 0x4657
#define SEA_mmDCP5_KEY_RANGE_BLUE 0x4957
#define SEA_mmDEGAMMA_CONTROL 0x1a58
#define SEA_mmDCP0_DEGAMMA_CONTROL 0x1a58
#define SEA_mmDCP1_DEGAMMA_CONTROL 0x1d58
#define SEA_mmDCP2_DEGAMMA_CONTROL 0x4058
#define SEA_mmDCP3_DEGAMMA_CONTROL 0x4358
#define SEA_mmDCP4_DEGAMMA_CONTROL 0x4658
#define SEA_mmDCP5_DEGAMMA_CONTROL 0x4958
#define SEA_mmGAMUT_REMAP_CONTROL 0x1a59
#define SEA_mmDCP0_GAMUT_REMAP_CONTROL 0x1a59
#define SEA_mmDCP1_GAMUT_REMAP_CONTROL 0x1d59
#define SEA_mmDCP2_GAMUT_REMAP_CONTROL 0x4059
#define SEA_mmDCP3_GAMUT_REMAP_CONTROL 0x4359
#define SEA_mmDCP4_GAMUT_REMAP_CONTROL 0x4659
#define SEA_mmDCP5_GAMUT_REMAP_CONTROL 0x4959
#define SEA_mmGAMUT_REMAP_C11_C12 0x1a5a
#define SEA_mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a
#define SEA_mmDCP1_GAMUT_REMAP_C11_C12 0x1d5a
#define SEA_mmDCP2_GAMUT_REMAP_C11_C12 0x405a
#define SEA_mmDCP3_GAMUT_REMAP_C11_C12 0x435a
#define SEA_mmDCP4_GAMUT_REMAP_C11_C12 0x465a
#define SEA_mmDCP5_GAMUT_REMAP_C11_C12 0x495a
#define SEA_mmGAMUT_REMAP_C13_C14 0x1a5b
#define SEA_mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b
#define SEA_mmDCP1_GAMUT_REMAP_C13_C14 0x1d5b
#define SEA_mmDCP2_GAMUT_REMAP_C13_C14 0x405b
#define SEA_mmDCP3_GAMUT_REMAP_C13_C14 0x435b
#define SEA_mmDCP4_GAMUT_REMAP_C13_C14 0x465b
#define SEA_mmDCP5_GAMUT_REMAP_C13_C14 0x495b
#define SEA_mmGAMUT_REMAP_C21_C22 0x1a5c
#define SEA_mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c
#define SEA_mmDCP1_GAMUT_REMAP_C21_C22 0x1d5c
#define SEA_mmDCP2_GAMUT_REMAP_C21_C22 0x405c
#define SEA_mmDCP3_GAMUT_REMAP_C21_C22 0x435c
#define SEA_mmDCP4_GAMUT_REMAP_C21_C22 0x465c
#define SEA_mmDCP5_GAMUT_REMAP_C21_C22 0x495c
#define SEA_mmGAMUT_REMAP_C23_C24 0x1a5d
#define SEA_mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d
#define SEA_mmDCP1_GAMUT_REMAP_C23_C24 0x1d5d
#define SEA_mmDCP2_GAMUT_REMAP_C23_C24 0x405d
#define SEA_mmDCP3_GAMUT_REMAP_C23_C24 0x435d
#define SEA_mmDCP4_GAMUT_REMAP_C23_C24 0x465d
#define SEA_mmDCP5_GAMUT_REMAP_C23_C24 0x495d
#define SEA_mmGAMUT_REMAP_C31_C32 0x1a5e
#define SEA_mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e
#define SEA_mmDCP1_GAMUT_REMAP_C31_C32 0x1d5e
#define SEA_mmDCP2_GAMUT_REMAP_C31_C32 0x405e
#define SEA_mmDCP3_GAMUT_REMAP_C31_C32 0x435e
#define SEA_mmDCP4_GAMUT_REMAP_C31_C32 0x465e
#define SEA_mmDCP5_GAMUT_REMAP_C31_C32 0x495e
#define SEA_mmGAMUT_REMAP_C33_C34 0x1a5f
#define SEA_mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f
#define SEA_mmDCP1_GAMUT_REMAP_C33_C34 0x1d5f
#define SEA_mmDCP2_GAMUT_REMAP_C33_C34 0x405f
#define SEA_mmDCP3_GAMUT_REMAP_C33_C34 0x435f
#define SEA_mmDCP4_GAMUT_REMAP_C33_C34 0x465f
#define SEA_mmDCP5_GAMUT_REMAP_C33_C34 0x495f
#define SEA_mmDCP_SPATIAL_DITHER_CNTL 0x1a60
#define SEA_mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60
#define SEA_mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1d60
#define SEA_mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x4060
#define SEA_mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4360
#define SEA_mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4660
#define SEA_mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4960
#define SEA_mmDCP_RANDOM_SEEDS 0x1a61
#define SEA_mmDCP0_DCP_RANDOM_SEEDS 0x1a61
#define SEA_mmDCP1_DCP_RANDOM_SEEDS 0x1d61
#define SEA_mmDCP2_DCP_RANDOM_SEEDS 0x4061
#define SEA_mmDCP3_DCP_RANDOM_SEEDS 0x4361
#define SEA_mmDCP4_DCP_RANDOM_SEEDS 0x4661
#define SEA_mmDCP5_DCP_RANDOM_SEEDS 0x4961
#define SEA_mmDCP_FP_CONVERTED_FIELD 0x1a65
#define SEA_mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65
#define SEA_mmDCP1_DCP_FP_CONVERTED_FIELD 0x1d65
#define SEA_mmDCP2_DCP_FP_CONVERTED_FIELD 0x4065
#define SEA_mmDCP3_DCP_FP_CONVERTED_FIELD 0x4365
#define SEA_mmDCP4_DCP_FP_CONVERTED_FIELD 0x4665
#define SEA_mmDCP5_DCP_FP_CONVERTED_FIELD 0x4965
#define SEA_mmCUR_CONTROL 0x1a66
#define SEA_mmDCP0_CUR_CONTROL 0x1a66
#define SEA_mmDCP1_CUR_CONTROL 0x1d66
#define SEA_mmDCP2_CUR_CONTROL 0x4066
#define SEA_mmDCP3_CUR_CONTROL 0x4366
#define SEA_mmDCP4_CUR_CONTROL 0x4666
#define SEA_mmDCP5_CUR_CONTROL 0x4966
#define SEA_mmCUR_SURFACE_ADDRESS 0x1a67
#define SEA_mmDCP0_CUR_SURFACE_ADDRESS 0x1a67
#define SEA_mmDCP1_CUR_SURFACE_ADDRESS 0x1d67
#define SEA_mmDCP2_CUR_SURFACE_ADDRESS 0x4067
#define SEA_mmDCP3_CUR_SURFACE_ADDRESS 0x4367
#define SEA_mmDCP4_CUR_SURFACE_ADDRESS 0x4667
#define SEA_mmDCP5_CUR_SURFACE_ADDRESS 0x4967
#define SEA_mmCUR_SIZE 0x1a68
#define SEA_mmDCP0_CUR_SIZE 0x1a68
#define SEA_mmDCP1_CUR_SIZE 0x1d68
#define SEA_mmDCP2_CUR_SIZE 0x4068
#define SEA_mmDCP3_CUR_SIZE 0x4368
#define SEA_mmDCP4_CUR_SIZE 0x4668
#define SEA_mmDCP5_CUR_SIZE 0x4968
#define SEA_mmCUR_SURFACE_ADDRESS_HIGH 0x1a69
#define SEA_mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69
#define SEA_mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1d69
#define SEA_mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x4069
#define SEA_mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4369
#define SEA_mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4669
#define SEA_mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4969
#define SEA_mmCUR_POSITION 0x1a6a
#define SEA_mmDCP0_CUR_POSITION 0x1a6a
#define SEA_mmDCP1_CUR_POSITION 0x1d6a
#define SEA_mmDCP2_CUR_POSITION 0x406a
#define SEA_mmDCP3_CUR_POSITION 0x436a
#define SEA_mmDCP4_CUR_POSITION 0x466a
#define SEA_mmDCP5_CUR_POSITION 0x496a
#define SEA_mmCUR_HOT_SPOT 0x1a6b
#define SEA_mmDCP0_CUR_HOT_SPOT 0x1a6b
#define SEA_mmDCP1_CUR_HOT_SPOT 0x1d6b
#define SEA_mmDCP2_CUR_HOT_SPOT 0x406b
#define SEA_mmDCP3_CUR_HOT_SPOT 0x436b
#define SEA_mmDCP4_CUR_HOT_SPOT 0x466b
#define SEA_mmDCP5_CUR_HOT_SPOT 0x496b
#define SEA_mmCUR_COLOR1 0x1a6c
#define SEA_mmDCP0_CUR_COLOR1 0x1a6c
#define SEA_mmDCP1_CUR_COLOR1 0x1d6c
#define SEA_mmDCP2_CUR_COLOR1 0x406c
#define SEA_mmDCP3_CUR_COLOR1 0x436c
#define SEA_mmDCP4_CUR_COLOR1 0x466c
#define SEA_mmDCP5_CUR_COLOR1 0x496c
#define SEA_mmCUR_COLOR2 0x1a6d
#define SEA_mmDCP0_CUR_COLOR2 0x1a6d
#define SEA_mmDCP1_CUR_COLOR2 0x1d6d
#define SEA_mmDCP2_CUR_COLOR2 0x406d
#define SEA_mmDCP3_CUR_COLOR2 0x436d
#define SEA_mmDCP4_CUR_COLOR2 0x466d
#define SEA_mmDCP5_CUR_COLOR2 0x496d
#define SEA_mmCUR_UPDATE 0x1a6e
#define SEA_mmDCP0_CUR_UPDATE 0x1a6e
#define SEA_mmDCP1_CUR_UPDATE 0x1d6e
#define SEA_mmDCP2_CUR_UPDATE 0x406e
#define SEA_mmDCP3_CUR_UPDATE 0x436e
#define SEA_mmDCP4_CUR_UPDATE 0x466e
#define SEA_mmDCP5_CUR_UPDATE 0x496e
#define SEA_mmCUR2_CONTROL 0x1a6f
#define SEA_mmDCP0_CUR2_CONTROL 0x1a6f
#define SEA_mmDCP1_CUR2_CONTROL 0x1d6f
#define SEA_mmDCP2_CUR2_CONTROL 0x406f
#define SEA_mmDCP3_CUR2_CONTROL 0x436f
#define SEA_mmDCP4_CUR2_CONTROL 0x466f
#define SEA_mmDCP5_CUR2_CONTROL 0x496f
#define SEA_mmCUR2_SURFACE_ADDRESS 0x1a70
#define SEA_mmDCP0_CUR2_SURFACE_ADDRESS 0x1a70
#define SEA_mmDCP1_CUR2_SURFACE_ADDRESS 0x1d70
#define SEA_mmDCP2_CUR2_SURFACE_ADDRESS 0x4070
#define SEA_mmDCP3_CUR2_SURFACE_ADDRESS 0x4370
#define SEA_mmDCP4_CUR2_SURFACE_ADDRESS 0x4670
#define SEA_mmDCP5_CUR2_SURFACE_ADDRESS 0x4970
#define SEA_mmCUR2_SIZE 0x1a71
#define SEA_mmDCP0_CUR2_SIZE 0x1a71
#define SEA_mmDCP1_CUR2_SIZE 0x1d71
#define SEA_mmDCP2_CUR2_SIZE 0x4071
#define SEA_mmDCP3_CUR2_SIZE 0x4371
#define SEA_mmDCP4_CUR2_SIZE 0x4671
#define SEA_mmDCP5_CUR2_SIZE 0x4971
#define SEA_mmCUR2_SURFACE_ADDRESS_HIGH 0x1a72
#define SEA_mmDCP0_CUR2_SURFACE_ADDRESS_HIGH 0x1a72
#define SEA_mmDCP1_CUR2_SURFACE_ADDRESS_HIGH 0x1d72
#define SEA_mmDCP2_CUR2_SURFACE_ADDRESS_HIGH 0x4072
#define SEA_mmDCP3_CUR2_SURFACE_ADDRESS_HIGH 0x4372
#define SEA_mmDCP4_CUR2_SURFACE_ADDRESS_HIGH 0x4672
#define SEA_mmDCP5_CUR2_SURFACE_ADDRESS_HIGH 0x4972
#define SEA_mmCUR2_POSITION 0x1a73
#define SEA_mmDCP0_CUR2_POSITION 0x1a73
#define SEA_mmDCP1_CUR2_POSITION 0x1d73
#define SEA_mmDCP2_CUR2_POSITION 0x4073
#define SEA_mmDCP3_CUR2_POSITION 0x4373
#define SEA_mmDCP4_CUR2_POSITION 0x4673
#define SEA_mmDCP5_CUR2_POSITION 0x4973
#define SEA_mmCUR2_HOT_SPOT 0x1a74
#define SEA_mmDCP0_CUR2_HOT_SPOT 0x1a74
#define SEA_mmDCP1_CUR2_HOT_SPOT 0x1d74
#define SEA_mmDCP2_CUR2_HOT_SPOT 0x4074
#define SEA_mmDCP3_CUR2_HOT_SPOT 0x4374
#define SEA_mmDCP4_CUR2_HOT_SPOT 0x4674
#define SEA_mmDCP5_CUR2_HOT_SPOT 0x4974
#define SEA_mmCUR2_COLOR1 0x1a75
#define SEA_mmDCP0_CUR2_COLOR1 0x1a75
#define SEA_mmDCP1_CUR2_COLOR1 0x1d75
#define SEA_mmDCP2_CUR2_COLOR1 0x4075
#define SEA_mmDCP3_CUR2_COLOR1 0x4375
#define SEA_mmDCP4_CUR2_COLOR1 0x4675
#define SEA_mmDCP5_CUR2_COLOR1 0x4975
#define SEA_mmCUR2_COLOR2 0x1a76
#define SEA_mmDCP0_CUR2_COLOR2 0x1a76
#define SEA_mmDCP1_CUR2_COLOR2 0x1d76
#define SEA_mmDCP2_CUR2_COLOR2 0x4076
#define SEA_mmDCP3_CUR2_COLOR2 0x4376
#define SEA_mmDCP4_CUR2_COLOR2 0x4676
#define SEA_mmDCP5_CUR2_COLOR2 0x4976
#define SEA_mmCUR2_UPDATE 0x1a77
#define SEA_mmDCP0_CUR2_UPDATE 0x1a77
#define SEA_mmDCP1_CUR2_UPDATE 0x1d77
#define SEA_mmDCP2_CUR2_UPDATE 0x4077
#define SEA_mmDCP3_CUR2_UPDATE 0x4377
#define SEA_mmDCP4_CUR2_UPDATE 0x4677
#define SEA_mmDCP5_CUR2_UPDATE 0x4977
#define SEA_mmCUR_REQUEST_FILTER_CNTL 0x1a99
#define SEA_mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99
#define SEA_mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1d99
#define SEA_mmDCP2_CUR_REQUEST_FILTER_CNTL 0x4099
#define SEA_mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4399
#define SEA_mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4699
#define SEA_mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4999
#define SEA_mmCUR_STEREO_CONTROL 0x1a9a
#define SEA_mmDCP0_CUR_STEREO_CONTROL 0x1a9a
#define SEA_mmDCP1_CUR_STEREO_CONTROL 0x1d9a
#define SEA_mmDCP2_CUR_STEREO_CONTROL 0x409a
#define SEA_mmDCP3_CUR_STEREO_CONTROL 0x439a
#define SEA_mmDCP4_CUR_STEREO_CONTROL 0x469a
#define SEA_mmDCP5_CUR_STEREO_CONTROL 0x499a
#define SEA_mmCUR2_STEREO_CONTROL 0x1a9b
#define SEA_mmDCP0_CUR2_STEREO_CONTROL 0x1a9b
#define SEA_mmDCP1_CUR2_STEREO_CONTROL 0x1d9b
#define SEA_mmDCP2_CUR2_STEREO_CONTROL 0x409b
#define SEA_mmDCP3_CUR2_STEREO_CONTROL 0x439b
#define SEA_mmDCP4_CUR2_STEREO_CONTROL 0x469b
#define SEA_mmDCP5_CUR2_STEREO_CONTROL 0x499b
#define SEA_mmDC_LUT_RW_MODE 0x1a78
#define SEA_mmDCP0_DC_LUT_RW_MODE 0x1a78
#define SEA_mmDCP1_DC_LUT_RW_MODE 0x1d78
#define SEA_mmDCP2_DC_LUT_RW_MODE 0x4078
#define SEA_mmDCP3_DC_LUT_RW_MODE 0x4378
#define SEA_mmDCP4_DC_LUT_RW_MODE 0x4678
#define SEA_mmDCP5_DC_LUT_RW_MODE 0x4978
#define SEA_mmDC_LUT_RW_INDEX 0x1a79
#define SEA_mmDCP0_DC_LUT_RW_INDEX 0x1a79
#define SEA_mmDCP1_DC_LUT_RW_INDEX 0x1d79
#define SEA_mmDCP2_DC_LUT_RW_INDEX 0x4079
#define SEA_mmDCP3_DC_LUT_RW_INDEX 0x4379
#define SEA_mmDCP4_DC_LUT_RW_INDEX 0x4679
#define SEA_mmDCP5_DC_LUT_RW_INDEX 0x4979
#define SEA_mmDC_LUT_SEQ_COLOR 0x1a7a
#define SEA_mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a
#define SEA_mmDCP1_DC_LUT_SEQ_COLOR 0x1d7a
#define SEA_mmDCP2_DC_LUT_SEQ_COLOR 0x407a
#define SEA_mmDCP3_DC_LUT_SEQ_COLOR 0x437a
#define SEA_mmDCP4_DC_LUT_SEQ_COLOR 0x467a
#define SEA_mmDCP5_DC_LUT_SEQ_COLOR 0x497a
#define SEA_mmDC_LUT_PWL_DATA 0x1a7b
#define SEA_mmDCP0_DC_LUT_PWL_DATA 0x1a7b
#define SEA_mmDCP1_DC_LUT_PWL_DATA 0x1d7b
#define SEA_mmDCP2_DC_LUT_PWL_DATA 0x407b
#define SEA_mmDCP3_DC_LUT_PWL_DATA 0x437b
#define SEA_mmDCP4_DC_LUT_PWL_DATA 0x467b
#define SEA_mmDCP5_DC_LUT_PWL_DATA 0x497b
#define SEA_mmDC_LUT_30_COLOR 0x1a7c
#define SEA_mmDCP0_DC_LUT_30_COLOR 0x1a7c
#define SEA_mmDCP1_DC_LUT_30_COLOR 0x1d7c
#define SEA_mmDCP2_DC_LUT_30_COLOR 0x407c
#define SEA_mmDCP3_DC_LUT_30_COLOR 0x437c
#define SEA_mmDCP4_DC_LUT_30_COLOR 0x467c
#define SEA_mmDCP5_DC_LUT_30_COLOR 0x497c
#define SEA_mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d
#define SEA_mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d
#define SEA_mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1d7d
#define SEA_mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x407d
#define SEA_mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x437d
#define SEA_mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x467d
#define SEA_mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x497d
#define SEA_mmDC_LUT_WRITE_EN_MASK 0x1a7e
#define SEA_mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e
#define SEA_mmDCP1_DC_LUT_WRITE_EN_MASK 0x1d7e
#define SEA_mmDCP2_DC_LUT_WRITE_EN_MASK 0x407e
#define SEA_mmDCP3_DC_LUT_WRITE_EN_MASK 0x437e
#define SEA_mmDCP4_DC_LUT_WRITE_EN_MASK 0x467e
#define SEA_mmDCP5_DC_LUT_WRITE_EN_MASK 0x497e
#define SEA_mmDC_LUT_AUTOFILL 0x1a7f
#define SEA_mmDCP0_DC_LUT_AUTOFILL 0x1a7f
#define SEA_mmDCP1_DC_LUT_AUTOFILL 0x1d7f
#define SEA_mmDCP2_DC_LUT_AUTOFILL 0x407f
#define SEA_mmDCP3_DC_LUT_AUTOFILL 0x437f
#define SEA_mmDCP4_DC_LUT_AUTOFILL 0x467f
#define SEA_mmDCP5_DC_LUT_AUTOFILL 0x497f
#define SEA_mmDC_LUT_CONTROL 0x1a80
#define SEA_mmDCP0_DC_LUT_CONTROL 0x1a80
#define SEA_mmDCP1_DC_LUT_CONTROL 0x1d80
#define SEA_mmDCP2_DC_LUT_CONTROL 0x4080
#define SEA_mmDCP3_DC_LUT_CONTROL 0x4380
#define SEA_mmDCP4_DC_LUT_CONTROL 0x4680
#define SEA_mmDCP5_DC_LUT_CONTROL 0x4980
#define SEA_mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81
#define SEA_mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81
#define SEA_mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1d81
#define SEA_mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x4081
#define SEA_mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4381
#define SEA_mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4681
#define SEA_mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4981
#define SEA_mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82
#define SEA_mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82
#define SEA_mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1d82
#define SEA_mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x4082
#define SEA_mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4382
#define SEA_mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4682
#define SEA_mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4982
#define SEA_mmDC_LUT_BLACK_OFFSET_RED 0x1a83
#define SEA_mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83
#define SEA_mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1d83
#define SEA_mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x4083
#define SEA_mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4383
#define SEA_mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4683
#define SEA_mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4983
#define SEA_mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84
#define SEA_mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84
#define SEA_mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1d84
#define SEA_mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x4084
#define SEA_mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4384
#define SEA_mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4684
#define SEA_mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4984
#define SEA_mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85
#define SEA_mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85
#define SEA_mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1d85
#define SEA_mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x4085
#define SEA_mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4385
#define SEA_mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4685
#define SEA_mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4985
#define SEA_mmDC_LUT_WHITE_OFFSET_RED 0x1a86
#define SEA_mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86
#define SEA_mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1d86
#define SEA_mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x4086
#define SEA_mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4386
#define SEA_mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4686
#define SEA_mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4986
#define SEA_mmDCP_CRC_CONTROL 0x1a87
#define SEA_mmDCP0_DCP_CRC_CONTROL 0x1a87
#define SEA_mmDCP1_DCP_CRC_CONTROL 0x1d87
#define SEA_mmDCP2_DCP_CRC_CONTROL 0x4087
#define SEA_mmDCP3_DCP_CRC_CONTROL 0x4387
#define SEA_mmDCP4_DCP_CRC_CONTROL 0x4687
#define SEA_mmDCP5_DCP_CRC_CONTROL 0x4987
#define SEA_mmDCP_CRC_MASK 0x1a88
#define SEA_mmDCP0_DCP_CRC_MASK 0x1a88
#define SEA_mmDCP1_DCP_CRC_MASK 0x1d88
#define SEA_mmDCP2_DCP_CRC_MASK 0x4088
#define SEA_mmDCP3_DCP_CRC_MASK 0x4388
#define SEA_mmDCP4_DCP_CRC_MASK 0x4688
#define SEA_mmDCP5_DCP_CRC_MASK 0x4988
#define SEA_mmDCP_CRC_CURRENT 0x1a89
#define SEA_mmDCP0_DCP_CRC_CURRENT 0x1a89
#define SEA_mmDCP1_DCP_CRC_CURRENT 0x1d89
#define SEA_mmDCP2_DCP_CRC_CURRENT 0x4089
#define SEA_mmDCP3_DCP_CRC_CURRENT 0x4389
#define SEA_mmDCP4_DCP_CRC_CURRENT 0x4689
#define SEA_mmDCP5_DCP_CRC_CURRENT 0x4989
#define SEA_mmDCP_CRC_LAST 0x1a8b
#define SEA_mmDCP0_DCP_CRC_LAST 0x1a8b
#define SEA_mmDCP1_DCP_CRC_LAST 0x1d8b
#define SEA_mmDCP2_DCP_CRC_LAST 0x408b
#define SEA_mmDCP3_DCP_CRC_LAST 0x438b
#define SEA_mmDCP4_DCP_CRC_LAST 0x468b
#define SEA_mmDCP5_DCP_CRC_LAST 0x498b
#define SEA_mmDCP_DEBUG 0x1a8d
#define SEA_mmDCP0_DCP_DEBUG 0x1a8d
#define SEA_mmDCP1_DCP_DEBUG 0x1d8d
#define SEA_mmDCP2_DCP_DEBUG 0x408d
#define SEA_mmDCP3_DCP_DEBUG 0x438d
#define SEA_mmDCP4_DCP_DEBUG 0x468d
#define SEA_mmDCP5_DCP_DEBUG 0x498d
#define SEA_mmGRPH_FLIP_RATE_CNTL 0x1a8e
#define SEA_mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e
#define SEA_mmDCP1_GRPH_FLIP_RATE_CNTL 0x1d8e
#define SEA_mmDCP2_GRPH_FLIP_RATE_CNTL 0x408e
#define SEA_mmDCP3_GRPH_FLIP_RATE_CNTL 0x438e
#define SEA_mmDCP4_GRPH_FLIP_RATE_CNTL 0x468e
#define SEA_mmDCP5_GRPH_FLIP_RATE_CNTL 0x498e
#define SEA_mmDCP_GSL_CONTROL 0x1a90
#define SEA_mmDCP0_DCP_GSL_CONTROL 0x1a90
#define SEA_mmDCP1_DCP_GSL_CONTROL 0x1d90
#define SEA_mmDCP2_DCP_GSL_CONTROL 0x4090
#define SEA_mmDCP3_DCP_GSL_CONTROL 0x4390
#define SEA_mmDCP4_DCP_GSL_CONTROL 0x4690
#define SEA_mmDCP5_DCP_GSL_CONTROL 0x4990
#define SEA_mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91
#define SEA_mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91
#define SEA_mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1d91
#define SEA_mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091
#define SEA_mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4391
#define SEA_mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4691
#define SEA_mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4991
#define SEA_mmOVL_SECONDARY_SURFACE_ADDRESS 0x1a92
#define SEA_mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0x1a92
#define SEA_mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0x1d92
#define SEA_mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0x4092
#define SEA_mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0x4392
#define SEA_mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0x4692
#define SEA_mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0x4992
#define SEA_mmOVL_STEREOSYNC_FLIP 0x1a93
#define SEA_mmDCP0_OVL_STEREOSYNC_FLIP 0x1a93
#define SEA_mmDCP1_OVL_STEREOSYNC_FLIP 0x1d93
#define SEA_mmDCP2_OVL_STEREOSYNC_FLIP 0x4093
#define SEA_mmDCP3_OVL_STEREOSYNC_FLIP 0x4393
#define SEA_mmDCP4_OVL_STEREOSYNC_FLIP 0x4693
#define SEA_mmDCP5_OVL_STEREOSYNC_FLIP 0x4993
#define SEA_mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94
#define SEA_mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94
#define SEA_mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1d94
#define SEA_mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4094
#define SEA_mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4394
#define SEA_mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4694
#define SEA_mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4994
#define SEA_mmDCP_TEST_DEBUG_INDEX 0x1a95
#define SEA_mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95
#define SEA_mmDCP1_DCP_TEST_DEBUG_INDEX 0x1d95
#define SEA_mmDCP2_DCP_TEST_DEBUG_INDEX 0x4095
#define SEA_mmDCP3_DCP_TEST_DEBUG_INDEX 0x4395
#define SEA_mmDCP4_DCP_TEST_DEBUG_INDEX 0x4695
#define SEA_mmDCP5_DCP_TEST_DEBUG_INDEX 0x4995
#define SEA_mmDCP_TEST_DEBUG_DATA 0x1a96
#define SEA_mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96
#define SEA_mmDCP1_DCP_TEST_DEBUG_DATA 0x1d96
#define SEA_mmDCP2_DCP_TEST_DEBUG_DATA 0x4096
#define SEA_mmDCP3_DCP_TEST_DEBUG_DATA 0x4396
#define SEA_mmDCP4_DCP_TEST_DEBUG_DATA 0x4696
#define SEA_mmDCP5_DCP_TEST_DEBUG_DATA 0x4996
#define SEA_mmGRPH_STEREOSYNC_FLIP 0x1a97
#define SEA_mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97
#define SEA_mmDCP1_GRPH_STEREOSYNC_FLIP 0x1d97
#define SEA_mmDCP2_GRPH_STEREOSYNC_FLIP 0x4097
#define SEA_mmDCP3_GRPH_STEREOSYNC_FLIP 0x4397
#define SEA_mmDCP4_GRPH_STEREOSYNC_FLIP 0x4697
#define SEA_mmDCP5_GRPH_STEREOSYNC_FLIP 0x4997
#define SEA_mmDCP_DEBUG2 0x1a98
#define SEA_mmDCP0_DCP_DEBUG2 0x1a98
#define SEA_mmDCP1_DCP_DEBUG2 0x1d98
#define SEA_mmDCP2_DCP_DEBUG2 0x4098
#define SEA_mmDCP3_DCP_DEBUG2 0x4398
#define SEA_mmDCP4_DCP_DEBUG2 0x4698
#define SEA_mmDCP5_DCP_DEBUG2 0x4998
#define SEA_mmHW_ROTATION 0x1a9e
#define SEA_mmDCP0_HW_ROTATION 0x1a9e
#define SEA_mmDCP1_HW_ROTATION 0x1d9e
#define SEA_mmDCP2_HW_ROTATION 0x409e
#define SEA_mmDCP3_HW_ROTATION 0x439e
#define SEA_mmDCP4_HW_ROTATION 0x469e
#define SEA_mmDCP5_HW_ROTATION 0x499e
#define SEA_mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f
#define SEA_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f
#define SEA_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1d9f
#define SEA_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f
#define SEA_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x439f
#define SEA_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x469f
#define SEA_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x499f
#define SEA_mmREGAMMA_CONTROL 0x1aa0
#define SEA_mmDCP0_REGAMMA_CONTROL 0x1aa0
#define SEA_mmDCP1_REGAMMA_CONTROL 0x1da0
#define SEA_mmDCP2_REGAMMA_CONTROL 0x40a0
#define SEA_mmDCP3_REGAMMA_CONTROL 0x43a0
#define SEA_mmDCP4_REGAMMA_CONTROL 0x46a0
#define SEA_mmDCP5_REGAMMA_CONTROL 0x49a0
#define SEA_mmREGAMMA_LUT_INDEX 0x1aa1
#define SEA_mmDCP0_REGAMMA_LUT_INDEX 0x1aa1
#define SEA_mmDCP1_REGAMMA_LUT_INDEX 0x1da1
#define SEA_mmDCP2_REGAMMA_LUT_INDEX 0x40a1
#define SEA_mmDCP3_REGAMMA_LUT_INDEX 0x43a1
#define SEA_mmDCP4_REGAMMA_LUT_INDEX 0x46a1
#define SEA_mmDCP5_REGAMMA_LUT_INDEX 0x49a1
#define SEA_mmREGAMMA_LUT_DATA 0x1aa2
#define SEA_mmDCP0_REGAMMA_LUT_DATA 0x1aa2
#define SEA_mmDCP1_REGAMMA_LUT_DATA 0x1da2
#define SEA_mmDCP2_REGAMMA_LUT_DATA 0x40a2
#define SEA_mmDCP3_REGAMMA_LUT_DATA 0x43a2
#define SEA_mmDCP4_REGAMMA_LUT_DATA 0x46a2
#define SEA_mmDCP5_REGAMMA_LUT_DATA 0x49a2
#define SEA_mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3
#define SEA_mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3
#define SEA_mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1da3
#define SEA_mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x40a3
#define SEA_mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x43a3
#define SEA_mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x46a3
#define SEA_mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x49a3
#define SEA_mmREGAMMA_CNTLA_START_CNTL 0x1aa4
#define SEA_mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4
#define SEA_mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1da4
#define SEA_mmDCP2_REGAMMA_CNTLA_START_CNTL 0x40a4
#define SEA_mmDCP3_REGAMMA_CNTLA_START_CNTL 0x43a4
#define SEA_mmDCP4_REGAMMA_CNTLA_START_CNTL 0x46a4
#define SEA_mmDCP5_REGAMMA_CNTLA_START_CNTL 0x49a4
#define SEA_mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5
#define SEA_mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5
#define SEA_mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1da5
#define SEA_mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5
#define SEA_mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x43a5
#define SEA_mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x46a5
#define SEA_mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x49a5
#define SEA_mmREGAMMA_CNTLA_END_CNTL1 0x1aa6
#define SEA_mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6
#define SEA_mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1da6
#define SEA_mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x40a6
#define SEA_mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x43a6
#define SEA_mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x46a6
#define SEA_mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x49a6
#define SEA_mmREGAMMA_CNTLA_END_CNTL2 0x1aa7
#define SEA_mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7
#define SEA_mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1da7
#define SEA_mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x40a7
#define SEA_mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x43a7
#define SEA_mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x46a7
#define SEA_mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x49a7
#define SEA_mmREGAMMA_CNTLA_REGION_0_1 0x1aa8
#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8
#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1da8
#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x40a8
#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x43a8
#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x46a8
#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x49a8
#define SEA_mmREGAMMA_CNTLA_REGION_2_3 0x1aa9
#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9
#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1da9
#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x40a9
#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x43a9
#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x46a9
#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x49a9
#define SEA_mmREGAMMA_CNTLA_REGION_4_5 0x1aaa
#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa
#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1daa
#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x40aa
#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x43aa
#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x46aa
#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x49aa
#define SEA_mmREGAMMA_CNTLA_REGION_6_7 0x1aab
#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab
#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1dab
#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x40ab
#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x43ab
#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x46ab
#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x49ab
#define SEA_mmREGAMMA_CNTLA_REGION_8_9 0x1aac
#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac
#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1dac
#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x40ac
#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x43ac
#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x46ac
#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x49ac
#define SEA_mmREGAMMA_CNTLA_REGION_10_11 0x1aad
#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad
#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1dad
#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x40ad
#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x43ad
#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x46ad
#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x49ad
#define SEA_mmREGAMMA_CNTLA_REGION_12_13 0x1aae
#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae
#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1dae
#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x40ae
#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x43ae
#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x46ae
#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x49ae
#define SEA_mmREGAMMA_CNTLA_REGION_14_15 0x1aaf
#define SEA_mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf
#define SEA_mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1daf
#define SEA_mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x40af
#define SEA_mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x43af
#define SEA_mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x46af
#define SEA_mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x49af
#define SEA_mmREGAMMA_CNTLB_START_CNTL 0x1ab0
#define SEA_mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0
#define SEA_mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1db0
#define SEA_mmDCP2_REGAMMA_CNTLB_START_CNTL 0x40b0
#define SEA_mmDCP3_REGAMMA_CNTLB_START_CNTL 0x43b0
#define SEA_mmDCP4_REGAMMA_CNTLB_START_CNTL 0x46b0
#define SEA_mmDCP5_REGAMMA_CNTLB_START_CNTL 0x49b0
#define SEA_mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1
#define SEA_mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1
#define SEA_mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1db1
#define SEA_mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1
#define SEA_mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x43b1
#define SEA_mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x46b1
#define SEA_mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x49b1
#define SEA_mmREGAMMA_CNTLB_END_CNTL1 0x1ab2
#define SEA_mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2
#define SEA_mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1db2
#define SEA_mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x40b2
#define SEA_mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x43b2
#define SEA_mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x46b2
#define SEA_mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x49b2
#define SEA_mmREGAMMA_CNTLB_END_CNTL2 0x1ab3
#define SEA_mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3
#define SEA_mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1db3
#define SEA_mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x40b3
#define SEA_mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x43b3
#define SEA_mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x46b3
#define SEA_mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x49b3
#define SEA_mmREGAMMA_CNTLB_REGION_0_1 0x1ab4
#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4
#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1db4
#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x40b4
#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x43b4
#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x46b4
#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x49b4
#define SEA_mmREGAMMA_CNTLB_REGION_2_3 0x1ab5
#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5
#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1db5
#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x40b5
#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x43b5
#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x46b5
#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x49b5
#define SEA_mmREGAMMA_CNTLB_REGION_4_5 0x1ab6
#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6
#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1db6
#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x40b6
#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x43b6
#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x46b6
#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x49b6
#define SEA_mmREGAMMA_CNTLB_REGION_6_7 0x1ab7
#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7
#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1db7
#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x40b7
#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x43b7
#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x46b7
#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x49b7
#define SEA_mmREGAMMA_CNTLB_REGION_8_9 0x1ab8
#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8
#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1db8
#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x40b8
#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x43b8
#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x46b8
#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x49b8
#define SEA_mmREGAMMA_CNTLB_REGION_10_11 0x1ab9
#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9
#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1db9
#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x40b9
#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x43b9
#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x46b9
#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x49b9
#define SEA_mmREGAMMA_CNTLB_REGION_12_13 0x1aba
#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba
#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1dba
#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x40ba
#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x43ba
#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x46ba
#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x49ba
#define SEA_mmREGAMMA_CNTLB_REGION_14_15 0x1abb
#define SEA_mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb
#define SEA_mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1dbb
#define SEA_mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x40bb
#define SEA_mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x43bb
#define SEA_mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x46bb
#define SEA_mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x49bb
#define SEA_mmALPHA_CONTROL 0x1abc
#define SEA_mmDCP0_ALPHA_CONTROL 0x1abc
#define SEA_mmDCP1_ALPHA_CONTROL 0x1dbc
#define SEA_mmDCP2_ALPHA_CONTROL 0x40bc
#define SEA_mmDCP3_ALPHA_CONTROL 0x43bc
#define SEA_mmDCP4_ALPHA_CONTROL 0x46bc
#define SEA_mmDCP5_ALPHA_CONTROL 0x49bc
#define SEA_mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd
#define SEA_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd
#define SEA_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1dbd
#define SEA_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd
#define SEA_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x43bd
#define SEA_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x46bd
#define SEA_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x49bd
#define SEA_mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe
#define SEA_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe
#define SEA_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1dbe
#define SEA_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be
#define SEA_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x43be
#define SEA_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x46be
#define SEA_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x49be
#define SEA_mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf
#define SEA_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf
#define SEA_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1dbf
#define SEA_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf
#define SEA_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x43bf
#define SEA_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x46bf
#define SEA_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x49bf
#define SEA_mmDIG_FE_CNTL 0x1c00
#define SEA_mmDIG0_DIG_FE_CNTL 0x1c00
#define SEA_mmDIG1_DIG_FE_CNTL 0x1f00
#define SEA_mmDIG2_DIG_FE_CNTL 0x4200
#define SEA_mmDIG3_DIG_FE_CNTL 0x4500
#define SEA_mmDIG4_DIG_FE_CNTL 0x4800
#define SEA_mmDIG5_DIG_FE_CNTL 0x4b00
#define SEA_mmDIG6_DIG_FE_CNTL 0x4e00
#define SEA_mmDIG_OUTPUT_CRC_CNTL 0x1c01
#define SEA_mmDIG0_DIG_OUTPUT_CRC_CNTL 0x1c01
#define SEA_mmDIG1_DIG_OUTPUT_CRC_CNTL 0x1f01
#define SEA_mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4201
#define SEA_mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4501
#define SEA_mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4801
#define SEA_mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4b01
#define SEA_mmDIG6_DIG_OUTPUT_CRC_CNTL 0x4e01
#define SEA_mmDIG_OUTPUT_CRC_RESULT 0x1c02
#define SEA_mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1c02
#define SEA_mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1f02
#define SEA_mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4202
#define SEA_mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4502
#define SEA_mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4802
#define SEA_mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4b02
#define SEA_mmDIG6_DIG_OUTPUT_CRC_RESULT 0x4e02
#define SEA_mmDIG_CLOCK_PATTERN 0x1c03
#define SEA_mmDIG0_DIG_CLOCK_PATTERN 0x1c03
#define SEA_mmDIG1_DIG_CLOCK_PATTERN 0x1f03
#define SEA_mmDIG2_DIG_CLOCK_PATTERN 0x4203
#define SEA_mmDIG3_DIG_CLOCK_PATTERN 0x4503
#define SEA_mmDIG4_DIG_CLOCK_PATTERN 0x4803
#define SEA_mmDIG5_DIG_CLOCK_PATTERN 0x4b03
#define SEA_mmDIG6_DIG_CLOCK_PATTERN 0x4e03
#define SEA_mmDIG_TEST_PATTERN 0x1c04
#define SEA_mmDIG0_DIG_TEST_PATTERN 0x1c04
#define SEA_mmDIG1_DIG_TEST_PATTERN 0x1f04
#define SEA_mmDIG2_DIG_TEST_PATTERN 0x4204
#define SEA_mmDIG3_DIG_TEST_PATTERN 0x4504
#define SEA_mmDIG4_DIG_TEST_PATTERN 0x4804
#define SEA_mmDIG5_DIG_TEST_PATTERN 0x4b04
#define SEA_mmDIG6_DIG_TEST_PATTERN 0x4e04
#define SEA_mmDIG_RANDOM_PATTERN_SEED 0x1c05
#define SEA_mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1c05
#define SEA_mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1f05
#define SEA_mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4205
#define SEA_mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4505
#define SEA_mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4805
#define SEA_mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4b05
#define SEA_mmDIG6_DIG_RANDOM_PATTERN_SEED 0x4e05
#define SEA_mmDIG_FIFO_STATUS 0x1c0a
#define SEA_mmDIG0_DIG_FIFO_STATUS 0x1c0a
#define SEA_mmDIG1_DIG_FIFO_STATUS 0x1f0a
#define SEA_mmDIG2_DIG_FIFO_STATUS 0x420a
#define SEA_mmDIG3_DIG_FIFO_STATUS 0x450a
#define SEA_mmDIG4_DIG_FIFO_STATUS 0x480a
#define SEA_mmDIG5_DIG_FIFO_STATUS 0x4b0a
#define SEA_mmDIG6_DIG_FIFO_STATUS 0x4e0a
#define SEA_mmDIG_DISPCLK_SWITCH_CNTL 0x1c08
#define SEA_mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x1c08
#define SEA_mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x1f08
#define SEA_mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4208
#define SEA_mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4508
#define SEA_mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4808
#define SEA_mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4b08
#define SEA_mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x4e08
#define SEA_mmDIG_DISPCLK_SWITCH_STATUS 0x1c09
#define SEA_mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x1c09
#define SEA_mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x1f09
#define SEA_mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4209
#define SEA_mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4509
#define SEA_mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4809
#define SEA_mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4b09
#define SEA_mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x4e09
#define SEA_mmHDMI_CONTROL 0x1c0c
#define SEA_mmDIG0_HDMI_CONTROL 0x1c0c
#define SEA_mmDIG1_HDMI_CONTROL 0x1f0c
#define SEA_mmDIG2_HDMI_CONTROL 0x420c
#define SEA_mmDIG3_HDMI_CONTROL 0x450c
#define SEA_mmDIG4_HDMI_CONTROL 0x480c
#define SEA_mmDIG5_HDMI_CONTROL 0x4b0c
#define SEA_mmDIG6_HDMI_CONTROL 0x4e0c
#define SEA_mmHDMI_STATUS 0x1c0d
#define SEA_mmDIG0_HDMI_STATUS 0x1c0d
#define SEA_mmDIG1_HDMI_STATUS 0x1f0d
#define SEA_mmDIG2_HDMI_STATUS 0x420d
#define SEA_mmDIG3_HDMI_STATUS 0x450d
#define SEA_mmDIG4_HDMI_STATUS 0x480d
#define SEA_mmDIG5_HDMI_STATUS 0x4b0d
#define SEA_mmDIG6_HDMI_STATUS 0x4e0d
#define SEA_mmHDMI_AUDIO_PACKET_CONTROL 0x1c0e
#define SEA_mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1c0e
#define SEA_mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1f0e
#define SEA_mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x420e
#define SEA_mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x450e
#define SEA_mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x480e
#define SEA_mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4b0e
#define SEA_mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x4e0e
#define SEA_mmHDMI_ACR_PACKET_CONTROL 0x1c0f
#define SEA_mmDIG0_HDMI_ACR_PACKET_CONTROL 0x1c0f
#define SEA_mmDIG1_HDMI_ACR_PACKET_CONTROL 0x1f0f
#define SEA_mmDIG2_HDMI_ACR_PACKET_CONTROL 0x420f
#define SEA_mmDIG3_HDMI_ACR_PACKET_CONTROL 0x450f
#define SEA_mmDIG4_HDMI_ACR_PACKET_CONTROL 0x480f
#define SEA_mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4b0f
#define SEA_mmDIG6_HDMI_ACR_PACKET_CONTROL 0x4e0f
#define SEA_mmHDMI_VBI_PACKET_CONTROL 0x1c10
#define SEA_mmDIG0_HDMI_VBI_PACKET_CONTROL 0x1c10
#define SEA_mmDIG1_HDMI_VBI_PACKET_CONTROL 0x1f10
#define SEA_mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4210
#define SEA_mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4510
#define SEA_mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4810
#define SEA_mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4b10
#define SEA_mmDIG6_HDMI_VBI_PACKET_CONTROL 0x4e10
#define SEA_mmHDMI_INFOFRAME_CONTROL0 0x1c11
#define SEA_mmDIG0_HDMI_INFOFRAME_CONTROL0 0x1c11
#define SEA_mmDIG1_HDMI_INFOFRAME_CONTROL0 0x1f11
#define SEA_mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4211
#define SEA_mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4511
#define SEA_mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4811
#define SEA_mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4b11
#define SEA_mmDIG6_HDMI_INFOFRAME_CONTROL0 0x4e11
#define SEA_mmHDMI_INFOFRAME_CONTROL1 0x1c12
#define SEA_mmDIG0_HDMI_INFOFRAME_CONTROL1 0x1c12
#define SEA_mmDIG1_HDMI_INFOFRAME_CONTROL1 0x1f12
#define SEA_mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4212
#define SEA_mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4512
#define SEA_mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4812
#define SEA_mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4b12
#define SEA_mmDIG6_HDMI_INFOFRAME_CONTROL1 0x4e12
#define SEA_mmHDMI_GENERIC_PACKET_CONTROL0 0x1c13
#define SEA_mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x1c13
#define SEA_mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x1f13
#define SEA_mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4213
#define SEA_mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4513
#define SEA_mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4813
#define SEA_mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4b13
#define SEA_mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x4e13
#define SEA_mmAFMT_INTERRUPT_STATUS 0x1c14
#define SEA_mmDIG0_AFMT_INTERRUPT_STATUS 0x1c14
#define SEA_mmDIG1_AFMT_INTERRUPT_STATUS 0x1f14
#define SEA_mmDIG2_AFMT_INTERRUPT_STATUS 0x4214
#define SEA_mmDIG3_AFMT_INTERRUPT_STATUS 0x4514
#define SEA_mmDIG4_AFMT_INTERRUPT_STATUS 0x4814
#define SEA_mmDIG5_AFMT_INTERRUPT_STATUS 0x4b14
#define SEA_mmDIG6_AFMT_INTERRUPT_STATUS 0x4e14
#define SEA_mmHDMI_GC 0x1c16
#define SEA_mmDIG0_HDMI_GC 0x1c16
#define SEA_mmDIG1_HDMI_GC 0x1f16
#define SEA_mmDIG2_HDMI_GC 0x4216
#define SEA_mmDIG3_HDMI_GC 0x4516
#define SEA_mmDIG4_HDMI_GC 0x4816
#define SEA_mmDIG5_HDMI_GC 0x4b16
#define SEA_mmDIG6_HDMI_GC 0x4e16
#define SEA_mmAFMT_AUDIO_PACKET_CONTROL2 0x1c17
#define SEA_mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1c17
#define SEA_mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1f17
#define SEA_mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4217
#define SEA_mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4517
#define SEA_mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4817
#define SEA_mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4b17
#define SEA_mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x4e17
#define SEA_mmAFMT_ISRC1_0 0x1c18
#define SEA_mmDIG0_AFMT_ISRC1_0 0x1c18
#define SEA_mmDIG1_AFMT_ISRC1_0 0x1f18
#define SEA_mmDIG2_AFMT_ISRC1_0 0x4218
#define SEA_mmDIG3_AFMT_ISRC1_0 0x4518
#define SEA_mmDIG4_AFMT_ISRC1_0 0x4818
#define SEA_mmDIG5_AFMT_ISRC1_0 0x4b18
#define SEA_mmDIG6_AFMT_ISRC1_0 0x4e18
#define SEA_mmAFMT_ISRC1_1 0x1c19
#define SEA_mmDIG0_AFMT_ISRC1_1 0x1c19
#define SEA_mmDIG1_AFMT_ISRC1_1 0x1f19
#define SEA_mmDIG2_AFMT_ISRC1_1 0x4219
#define SEA_mmDIG3_AFMT_ISRC1_1 0x4519
#define SEA_mmDIG4_AFMT_ISRC1_1 0x4819
#define SEA_mmDIG5_AFMT_ISRC1_1 0x4b19
#define SEA_mmDIG6_AFMT_ISRC1_1 0x4e19
#define SEA_mmAFMT_ISRC1_2 0x1c1a
#define SEA_mmDIG0_AFMT_ISRC1_2 0x1c1a
#define SEA_mmDIG1_AFMT_ISRC1_2 0x1f1a
#define SEA_mmDIG2_AFMT_ISRC1_2 0x421a
#define SEA_mmDIG3_AFMT_ISRC1_2 0x451a
#define SEA_mmDIG4_AFMT_ISRC1_2 0x481a
#define SEA_mmDIG5_AFMT_ISRC1_2 0x4b1a
#define SEA_mmDIG6_AFMT_ISRC1_2 0x4e1a
#define SEA_mmAFMT_ISRC1_3 0x1c1b
#define SEA_mmDIG0_AFMT_ISRC1_3 0x1c1b
#define SEA_mmDIG1_AFMT_ISRC1_3 0x1f1b
#define SEA_mmDIG2_AFMT_ISRC1_3 0x421b
#define SEA_mmDIG3_AFMT_ISRC1_3 0x451b
#define SEA_mmDIG4_AFMT_ISRC1_3 0x481b
#define SEA_mmDIG5_AFMT_ISRC1_3 0x4b1b
#define SEA_mmDIG6_AFMT_ISRC1_3 0x4e1b
#define SEA_mmAFMT_ISRC1_4 0x1c1c
#define SEA_mmDIG0_AFMT_ISRC1_4 0x1c1c
#define SEA_mmDIG1_AFMT_ISRC1_4 0x1f1c
#define SEA_mmDIG2_AFMT_ISRC1_4 0x421c
#define SEA_mmDIG3_AFMT_ISRC1_4 0x451c
#define SEA_mmDIG4_AFMT_ISRC1_4 0x481c
#define SEA_mmDIG5_AFMT_ISRC1_4 0x4b1c
#define SEA_mmDIG6_AFMT_ISRC1_4 0x4e1c
#define SEA_mmAFMT_ISRC2_0 0x1c1d
#define SEA_mmDIG0_AFMT_ISRC2_0 0x1c1d
#define SEA_mmDIG1_AFMT_ISRC2_0 0x1f1d
#define SEA_mmDIG2_AFMT_ISRC2_0 0x421d
#define SEA_mmDIG3_AFMT_ISRC2_0 0x451d
#define SEA_mmDIG4_AFMT_ISRC2_0 0x481d
#define SEA_mmDIG5_AFMT_ISRC2_0 0x4b1d
#define SEA_mmDIG6_AFMT_ISRC2_0 0x4e1d
#define SEA_mmAFMT_ISRC2_1 0x1c1e
#define SEA_mmDIG0_AFMT_ISRC2_1 0x1c1e
#define SEA_mmDIG1_AFMT_ISRC2_1 0x1f1e
#define SEA_mmDIG2_AFMT_ISRC2_1 0x421e
#define SEA_mmDIG3_AFMT_ISRC2_1 0x451e
#define SEA_mmDIG4_AFMT_ISRC2_1 0x481e
#define SEA_mmDIG5_AFMT_ISRC2_1 0x4b1e
#define SEA_mmDIG6_AFMT_ISRC2_1 0x4e1e
#define SEA_mmAFMT_ISRC2_2 0x1c1f
#define SEA_mmDIG0_AFMT_ISRC2_2 0x1c1f
#define SEA_mmDIG1_AFMT_ISRC2_2 0x1f1f
#define SEA_mmDIG2_AFMT_ISRC2_2 0x421f
#define SEA_mmDIG3_AFMT_ISRC2_2 0x451f
#define SEA_mmDIG4_AFMT_ISRC2_2 0x481f
#define SEA_mmDIG5_AFMT_ISRC2_2 0x4b1f
#define SEA_mmDIG6_AFMT_ISRC2_2 0x4e1f
#define SEA_mmAFMT_ISRC2_3 0x1c20
#define SEA_mmDIG0_AFMT_ISRC2_3 0x1c20
#define SEA_mmDIG1_AFMT_ISRC2_3 0x1f20
#define SEA_mmDIG2_AFMT_ISRC2_3 0x4220
#define SEA_mmDIG3_AFMT_ISRC2_3 0x4520
#define SEA_mmDIG4_AFMT_ISRC2_3 0x4820
#define SEA_mmDIG5_AFMT_ISRC2_3 0x4b20
#define SEA_mmDIG6_AFMT_ISRC2_3 0x4e20
#define SEA_mmAFMT_AVI_INFO0 0x1c21
#define SEA_mmDIG0_AFMT_AVI_INFO0 0x1c21
#define SEA_mmDIG1_AFMT_AVI_INFO0 0x1f21
#define SEA_mmDIG2_AFMT_AVI_INFO0 0x4221
#define SEA_mmDIG3_AFMT_AVI_INFO0 0x4521
#define SEA_mmDIG4_AFMT_AVI_INFO0 0x4821
#define SEA_mmDIG5_AFMT_AVI_INFO0 0x4b21
#define SEA_mmDIG6_AFMT_AVI_INFO0 0x4e21
#define SEA_mmAFMT_AVI_INFO1 0x1c22
#define SEA_mmDIG0_AFMT_AVI_INFO1 0x1c22
#define SEA_mmDIG1_AFMT_AVI_INFO1 0x1f22
#define SEA_mmDIG2_AFMT_AVI_INFO1 0x4222
#define SEA_mmDIG3_AFMT_AVI_INFO1 0x4522
#define SEA_mmDIG4_AFMT_AVI_INFO1 0x4822
#define SEA_mmDIG5_AFMT_AVI_INFO1 0x4b22
#define SEA_mmDIG6_AFMT_AVI_INFO1 0x4e22
#define SEA_mmAFMT_AVI_INFO2 0x1c23
#define SEA_mmDIG0_AFMT_AVI_INFO2 0x1c23
#define SEA_mmDIG1_AFMT_AVI_INFO2 0x1f23
#define SEA_mmDIG2_AFMT_AVI_INFO2 0x4223
#define SEA_mmDIG3_AFMT_AVI_INFO2 0x4523
#define SEA_mmDIG4_AFMT_AVI_INFO2 0x4823
#define SEA_mmDIG5_AFMT_AVI_INFO2 0x4b23
#define SEA_mmDIG6_AFMT_AVI_INFO2 0x4e23
#define SEA_mmAFMT_AVI_INFO3 0x1c24
#define SEA_mmDIG0_AFMT_AVI_INFO3 0x1c24
#define SEA_mmDIG1_AFMT_AVI_INFO3 0x1f24
#define SEA_mmDIG2_AFMT_AVI_INFO3 0x4224
#define SEA_mmDIG3_AFMT_AVI_INFO3 0x4524
#define SEA_mmDIG4_AFMT_AVI_INFO3 0x4824
#define SEA_mmDIG5_AFMT_AVI_INFO3 0x4b24
#define SEA_mmDIG6_AFMT_AVI_INFO3 0x4e24
#define SEA_mmAFMT_MPEG_INFO0 0x1c25
#define SEA_mmDIG0_AFMT_MPEG_INFO0 0x1c25
#define SEA_mmDIG1_AFMT_MPEG_INFO0 0x1f25
#define SEA_mmDIG2_AFMT_MPEG_INFO0 0x4225
#define SEA_mmDIG3_AFMT_MPEG_INFO0 0x4525
#define SEA_mmDIG4_AFMT_MPEG_INFO0 0x4825
#define SEA_mmDIG5_AFMT_MPEG_INFO0 0x4b25
#define SEA_mmDIG6_AFMT_MPEG_INFO0 0x4e25
#define SEA_mmAFMT_MPEG_INFO1 0x1c26
#define SEA_mmDIG0_AFMT_MPEG_INFO1 0x1c26
#define SEA_mmDIG1_AFMT_MPEG_INFO1 0x1f26
#define SEA_mmDIG2_AFMT_MPEG_INFO1 0x4226
#define SEA_mmDIG3_AFMT_MPEG_INFO1 0x4526
#define SEA_mmDIG4_AFMT_MPEG_INFO1 0x4826
#define SEA_mmDIG5_AFMT_MPEG_INFO1 0x4b26
#define SEA_mmDIG6_AFMT_MPEG_INFO1 0x4e26
#define SEA_mmAFMT_GENERIC_HDR 0x1c27
#define SEA_mmDIG0_AFMT_GENERIC_HDR 0x1c27
#define SEA_mmDIG1_AFMT_GENERIC_HDR 0x1f27
#define SEA_mmDIG2_AFMT_GENERIC_HDR 0x4227
#define SEA_mmDIG3_AFMT_GENERIC_HDR 0x4527
#define SEA_mmDIG4_AFMT_GENERIC_HDR 0x4827
#define SEA_mmDIG5_AFMT_GENERIC_HDR 0x4b27
#define SEA_mmDIG6_AFMT_GENERIC_HDR 0x4e27
#define SEA_mmAFMT_GENERIC_0 0x1c28
#define SEA_mmDIG0_AFMT_GENERIC_0 0x1c28
#define SEA_mmDIG1_AFMT_GENERIC_0 0x1f28
#define SEA_mmDIG2_AFMT_GENERIC_0 0x4228
#define SEA_mmDIG3_AFMT_GENERIC_0 0x4528
#define SEA_mmDIG4_AFMT_GENERIC_0 0x4828
#define SEA_mmDIG5_AFMT_GENERIC_0 0x4b28
#define SEA_mmDIG6_AFMT_GENERIC_0 0x4e28
#define SEA_mmAFMT_GENERIC_1 0x1c29
#define SEA_mmDIG0_AFMT_GENERIC_1 0x1c29
#define SEA_mmDIG1_AFMT_GENERIC_1 0x1f29
#define SEA_mmDIG2_AFMT_GENERIC_1 0x4229
#define SEA_mmDIG3_AFMT_GENERIC_1 0x4529
#define SEA_mmDIG4_AFMT_GENERIC_1 0x4829
#define SEA_mmDIG5_AFMT_GENERIC_1 0x4b29
#define SEA_mmDIG6_AFMT_GENERIC_1 0x4e29
#define SEA_mmAFMT_GENERIC_2 0x1c2a
#define SEA_mmDIG0_AFMT_GENERIC_2 0x1c2a
#define SEA_mmDIG1_AFMT_GENERIC_2 0x1f2a
#define SEA_mmDIG2_AFMT_GENERIC_2 0x422a
#define SEA_mmDIG3_AFMT_GENERIC_2 0x452a
#define SEA_mmDIG4_AFMT_GENERIC_2 0x482a
#define SEA_mmDIG5_AFMT_GENERIC_2 0x4b2a
#define SEA_mmDIG6_AFMT_GENERIC_2 0x4e2a
#define SEA_mmAFMT_GENERIC_3 0x1c2b
#define SEA_mmDIG0_AFMT_GENERIC_3 0x1c2b
#define SEA_mmDIG1_AFMT_GENERIC_3 0x1f2b
#define SEA_mmDIG2_AFMT_GENERIC_3 0x422b
#define SEA_mmDIG3_AFMT_GENERIC_3 0x452b
#define SEA_mmDIG4_AFMT_GENERIC_3 0x482b
#define SEA_mmDIG5_AFMT_GENERIC_3 0x4b2b
#define SEA_mmDIG6_AFMT_GENERIC_3 0x4e2b
#define SEA_mmAFMT_GENERIC_4 0x1c2c
#define SEA_mmDIG0_AFMT_GENERIC_4 0x1c2c
#define SEA_mmDIG1_AFMT_GENERIC_4 0x1f2c
#define SEA_mmDIG2_AFMT_GENERIC_4 0x422c
#define SEA_mmDIG3_AFMT_GENERIC_4 0x452c
#define SEA_mmDIG4_AFMT_GENERIC_4 0x482c
#define SEA_mmDIG5_AFMT_GENERIC_4 0x4b2c
#define SEA_mmDIG6_AFMT_GENERIC_4 0x4e2c
#define SEA_mmAFMT_GENERIC_5 0x1c2d
#define SEA_mmDIG0_AFMT_GENERIC_5 0x1c2d
#define SEA_mmDIG1_AFMT_GENERIC_5 0x1f2d
#define SEA_mmDIG2_AFMT_GENERIC_5 0x422d
#define SEA_mmDIG3_AFMT_GENERIC_5 0x452d
#define SEA_mmDIG4_AFMT_GENERIC_5 0x482d
#define SEA_mmDIG5_AFMT_GENERIC_5 0x4b2d
#define SEA_mmDIG6_AFMT_GENERIC_5 0x4e2d
#define SEA_mmAFMT_GENERIC_6 0x1c2e
#define SEA_mmDIG0_AFMT_GENERIC_6 0x1c2e
#define SEA_mmDIG1_AFMT_GENERIC_6 0x1f2e
#define SEA_mmDIG2_AFMT_GENERIC_6 0x422e
#define SEA_mmDIG3_AFMT_GENERIC_6 0x452e
#define SEA_mmDIG4_AFMT_GENERIC_6 0x482e
#define SEA_mmDIG5_AFMT_GENERIC_6 0x4b2e
#define SEA_mmDIG6_AFMT_GENERIC_6 0x4e2e
#define SEA_mmAFMT_GENERIC_7 0x1c2f
#define SEA_mmDIG0_AFMT_GENERIC_7 0x1c2f
#define SEA_mmDIG1_AFMT_GENERIC_7 0x1f2f
#define SEA_mmDIG2_AFMT_GENERIC_7 0x422f
#define SEA_mmDIG3_AFMT_GENERIC_7 0x452f
#define SEA_mmDIG4_AFMT_GENERIC_7 0x482f
#define SEA_mmDIG5_AFMT_GENERIC_7 0x4b2f
#define SEA_mmDIG6_AFMT_GENERIC_7 0x4e2f
#define SEA_mmHDMI_GENERIC_PACKET_CONTROL1 0x1c30
#define SEA_mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x1c30
#define SEA_mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x1f30
#define SEA_mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4230
#define SEA_mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4530
#define SEA_mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4830
#define SEA_mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4b30
#define SEA_mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x4e30
#define SEA_mmHDMI_ACR_32_0 0x1c37
#define SEA_mmDIG0_HDMI_ACR_32_0 0x1c37
#define SEA_mmDIG1_HDMI_ACR_32_0 0x1f37
#define SEA_mmDIG2_HDMI_ACR_32_0 0x4237
#define SEA_mmDIG3_HDMI_ACR_32_0 0x4537
#define SEA_mmDIG4_HDMI_ACR_32_0 0x4837
#define SEA_mmDIG5_HDMI_ACR_32_0 0x4b37
#define SEA_mmDIG6_HDMI_ACR_32_0 0x4e37
#define SEA_mmHDMI_ACR_32_1 0x1c38
#define SEA_mmDIG0_HDMI_ACR_32_1 0x1c38
#define SEA_mmDIG1_HDMI_ACR_32_1 0x1f38
#define SEA_mmDIG2_HDMI_ACR_32_1 0x4238
#define SEA_mmDIG3_HDMI_ACR_32_1 0x4538
#define SEA_mmDIG4_HDMI_ACR_32_1 0x4838
#define SEA_mmDIG5_HDMI_ACR_32_1 0x4b38
#define SEA_mmDIG6_HDMI_ACR_32_1 0x4e38
#define SEA_mmHDMI_ACR_44_0 0x1c39
#define SEA_mmDIG0_HDMI_ACR_44_0 0x1c39
#define SEA_mmDIG1_HDMI_ACR_44_0 0x1f39
#define SEA_mmDIG2_HDMI_ACR_44_0 0x4239
#define SEA_mmDIG3_HDMI_ACR_44_0 0x4539
#define SEA_mmDIG4_HDMI_ACR_44_0 0x4839
#define SEA_mmDIG5_HDMI_ACR_44_0 0x4b39
#define SEA_mmDIG6_HDMI_ACR_44_0 0x4e39
#define SEA_mmHDMI_ACR_44_1 0x1c3a
#define SEA_mmDIG0_HDMI_ACR_44_1 0x1c3a
#define SEA_mmDIG1_HDMI_ACR_44_1 0x1f3a
#define SEA_mmDIG2_HDMI_ACR_44_1 0x423a
#define SEA_mmDIG3_HDMI_ACR_44_1 0x453a
#define SEA_mmDIG4_HDMI_ACR_44_1 0x483a
#define SEA_mmDIG5_HDMI_ACR_44_1 0x4b3a
#define SEA_mmDIG6_HDMI_ACR_44_1 0x4e3a
#define SEA_mmHDMI_ACR_48_0 0x1c3b
#define SEA_mmDIG0_HDMI_ACR_48_0 0x1c3b
#define SEA_mmDIG1_HDMI_ACR_48_0 0x1f3b
#define SEA_mmDIG2_HDMI_ACR_48_0 0x423b
#define SEA_mmDIG3_HDMI_ACR_48_0 0x453b
#define SEA_mmDIG4_HDMI_ACR_48_0 0x483b
#define SEA_mmDIG5_HDMI_ACR_48_0 0x4b3b
#define SEA_mmDIG6_HDMI_ACR_48_0 0x4e3b
#define SEA_mmHDMI_ACR_48_1 0x1c3c
#define SEA_mmDIG0_HDMI_ACR_48_1 0x1c3c
#define SEA_mmDIG1_HDMI_ACR_48_1 0x1f3c
#define SEA_mmDIG2_HDMI_ACR_48_1 0x423c
#define SEA_mmDIG3_HDMI_ACR_48_1 0x453c
#define SEA_mmDIG4_HDMI_ACR_48_1 0x483c
#define SEA_mmDIG5_HDMI_ACR_48_1 0x4b3c
#define SEA_mmDIG6_HDMI_ACR_48_1 0x4e3c
#define SEA_mmHDMI_ACR_STATUS_0 0x1c3d
#define SEA_mmDIG0_HDMI_ACR_STATUS_0 0x1c3d
#define SEA_mmDIG1_HDMI_ACR_STATUS_0 0x1f3d
#define SEA_mmDIG2_HDMI_ACR_STATUS_0 0x423d
#define SEA_mmDIG3_HDMI_ACR_STATUS_0 0x453d
#define SEA_mmDIG4_HDMI_ACR_STATUS_0 0x483d
#define SEA_mmDIG5_HDMI_ACR_STATUS_0 0x4b3d
#define SEA_mmDIG6_HDMI_ACR_STATUS_0 0x4e3d
#define SEA_mmHDMI_ACR_STATUS_1 0x1c3e
#define SEA_mmDIG0_HDMI_ACR_STATUS_1 0x1c3e
#define SEA_mmDIG1_HDMI_ACR_STATUS_1 0x1f3e
#define SEA_mmDIG2_HDMI_ACR_STATUS_1 0x423e
#define SEA_mmDIG3_HDMI_ACR_STATUS_1 0x453e
#define SEA_mmDIG4_HDMI_ACR_STATUS_1 0x483e
#define SEA_mmDIG5_HDMI_ACR_STATUS_1 0x4b3e
#define SEA_mmDIG6_HDMI_ACR_STATUS_1 0x4e3e
#define SEA_mmAFMT_AUDIO_INFO0 0x1c3f
#define SEA_mmDIG0_AFMT_AUDIO_INFO0 0x1c3f
#define SEA_mmDIG1_AFMT_AUDIO_INFO0 0x1f3f
#define SEA_mmDIG2_AFMT_AUDIO_INFO0 0x423f
#define SEA_mmDIG3_AFMT_AUDIO_INFO0 0x453f
#define SEA_mmDIG4_AFMT_AUDIO_INFO0 0x483f
#define SEA_mmDIG5_AFMT_AUDIO_INFO0 0x4b3f
#define SEA_mmDIG6_AFMT_AUDIO_INFO0 0x4e3f
#define SEA_mmAFMT_AUDIO_INFO1 0x1c40
#define SEA_mmDIG0_AFMT_AUDIO_INFO1 0x1c40
#define SEA_mmDIG1_AFMT_AUDIO_INFO1 0x1f40
#define SEA_mmDIG2_AFMT_AUDIO_INFO1 0x4240
#define SEA_mmDIG3_AFMT_AUDIO_INFO1 0x4540
#define SEA_mmDIG4_AFMT_AUDIO_INFO1 0x4840
#define SEA_mmDIG5_AFMT_AUDIO_INFO1 0x4b40
#define SEA_mmDIG6_AFMT_AUDIO_INFO1 0x4e40
#define SEA_mmAFMT_60958_0 0x1c41
#define SEA_mmDIG0_AFMT_60958_0 0x1c41
#define SEA_mmDIG1_AFMT_60958_0 0x1f41
#define SEA_mmDIG2_AFMT_60958_0 0x4241
#define SEA_mmDIG3_AFMT_60958_0 0x4541
#define SEA_mmDIG4_AFMT_60958_0 0x4841
#define SEA_mmDIG5_AFMT_60958_0 0x4b41
#define SEA_mmDIG6_AFMT_60958_0 0x4e41
#define SEA_mmAFMT_60958_1 0x1c42
#define SEA_mmDIG0_AFMT_60958_1 0x1c42
#define SEA_mmDIG1_AFMT_60958_1 0x1f42
#define SEA_mmDIG2_AFMT_60958_1 0x4242
#define SEA_mmDIG3_AFMT_60958_1 0x4542
#define SEA_mmDIG4_AFMT_60958_1 0x4842
#define SEA_mmDIG5_AFMT_60958_1 0x4b42
#define SEA_mmDIG6_AFMT_60958_1 0x4e42
#define SEA_mmAFMT_AUDIO_CRC_CONTROL 0x1c43
#define SEA_mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x1c43
#define SEA_mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x1f43
#define SEA_mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4243
#define SEA_mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4543
#define SEA_mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4843
#define SEA_mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4b43
#define SEA_mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x4e43
#define SEA_mmAFMT_RAMP_CONTROL0 0x1c44
#define SEA_mmDIG0_AFMT_RAMP_CONTROL0 0x1c44
#define SEA_mmDIG1_AFMT_RAMP_CONTROL0 0x1f44
#define SEA_mmDIG2_AFMT_RAMP_CONTROL0 0x4244
#define SEA_mmDIG3_AFMT_RAMP_CONTROL0 0x4544
#define SEA_mmDIG4_AFMT_RAMP_CONTROL0 0x4844
#define SEA_mmDIG5_AFMT_RAMP_CONTROL0 0x4b44
#define SEA_mmDIG6_AFMT_RAMP_CONTROL0 0x4e44
#define SEA_mmAFMT_RAMP_CONTROL1 0x1c45
#define SEA_mmDIG0_AFMT_RAMP_CONTROL1 0x1c45
#define SEA_mmDIG1_AFMT_RAMP_CONTROL1 0x1f45
#define SEA_mmDIG2_AFMT_RAMP_CONTROL1 0x4245
#define SEA_mmDIG3_AFMT_RAMP_CONTROL1 0x4545
#define SEA_mmDIG4_AFMT_RAMP_CONTROL1 0x4845
#define SEA_mmDIG5_AFMT_RAMP_CONTROL1 0x4b45
#define SEA_mmDIG6_AFMT_RAMP_CONTROL1 0x4e45
#define SEA_mmAFMT_RAMP_CONTROL2 0x1c46
#define SEA_mmDIG0_AFMT_RAMP_CONTROL2 0x1c46
#define SEA_mmDIG1_AFMT_RAMP_CONTROL2 0x1f46
#define SEA_mmDIG2_AFMT_RAMP_CONTROL2 0x4246
#define SEA_mmDIG3_AFMT_RAMP_CONTROL2 0x4546
#define SEA_mmDIG4_AFMT_RAMP_CONTROL2 0x4846
#define SEA_mmDIG5_AFMT_RAMP_CONTROL2 0x4b46
#define SEA_mmDIG6_AFMT_RAMP_CONTROL2 0x4e46
#define SEA_mmAFMT_RAMP_CONTROL3 0x1c47
#define SEA_mmDIG0_AFMT_RAMP_CONTROL3 0x1c47
#define SEA_mmDIG1_AFMT_RAMP_CONTROL3 0x1f47
#define SEA_mmDIG2_AFMT_RAMP_CONTROL3 0x4247
#define SEA_mmDIG3_AFMT_RAMP_CONTROL3 0x4547
#define SEA_mmDIG4_AFMT_RAMP_CONTROL3 0x4847
#define SEA_mmDIG5_AFMT_RAMP_CONTROL3 0x4b47
#define SEA_mmDIG6_AFMT_RAMP_CONTROL3 0x4e47
#define SEA_mmAFMT_60958_2 0x1c48
#define SEA_mmDIG0_AFMT_60958_2 0x1c48
#define SEA_mmDIG1_AFMT_60958_2 0x1f48
#define SEA_mmDIG2_AFMT_60958_2 0x4248
#define SEA_mmDIG3_AFMT_60958_2 0x4548
#define SEA_mmDIG4_AFMT_60958_2 0x4848
#define SEA_mmDIG5_AFMT_60958_2 0x4b48
#define SEA_mmDIG6_AFMT_60958_2 0x4e48
#define SEA_mmAFMT_AUDIO_CRC_RESULT 0x1c49
#define SEA_mmDIG0_AFMT_AUDIO_CRC_RESULT 0x1c49
#define SEA_mmDIG1_AFMT_AUDIO_CRC_RESULT 0x1f49
#define SEA_mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4249
#define SEA_mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4549
#define SEA_mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4849
#define SEA_mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4b49
#define SEA_mmDIG6_AFMT_AUDIO_CRC_RESULT 0x4e49
#define SEA_mmAFMT_STATUS 0x1c4a
#define SEA_mmDIG0_AFMT_STATUS 0x1c4a
#define SEA_mmDIG1_AFMT_STATUS 0x1f4a
#define SEA_mmDIG2_AFMT_STATUS 0x424a
#define SEA_mmDIG3_AFMT_STATUS 0x454a
#define SEA_mmDIG4_AFMT_STATUS 0x484a
#define SEA_mmDIG5_AFMT_STATUS 0x4b4a
#define SEA_mmDIG6_AFMT_STATUS 0x4e4a
#define SEA_mmAFMT_AUDIO_PACKET_CONTROL 0x1c4b
#define SEA_mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x1c4b
#define SEA_mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x1f4b
#define SEA_mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x424b
#define SEA_mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x454b
#define SEA_mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x484b
#define SEA_mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4b4b
#define SEA_mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x4e4b
#define SEA_mmAFMT_VBI_PACKET_CONTROL 0x1c4c
#define SEA_mmDIG0_AFMT_VBI_PACKET_CONTROL 0x1c4c
#define SEA_mmDIG1_AFMT_VBI_PACKET_CONTROL 0x1f4c
#define SEA_mmDIG2_AFMT_VBI_PACKET_CONTROL 0x424c
#define SEA_mmDIG3_AFMT_VBI_PACKET_CONTROL 0x454c
#define SEA_mmDIG4_AFMT_VBI_PACKET_CONTROL 0x484c
#define SEA_mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4b4c
#define SEA_mmDIG6_AFMT_VBI_PACKET_CONTROL 0x4e4c
#define SEA_mmAFMT_INFOFRAME_CONTROL0 0x1c4d
#define SEA_mmDIG0_AFMT_INFOFRAME_CONTROL0 0x1c4d
#define SEA_mmDIG1_AFMT_INFOFRAME_CONTROL0 0x1f4d
#define SEA_mmDIG2_AFMT_INFOFRAME_CONTROL0 0x424d
#define SEA_mmDIG3_AFMT_INFOFRAME_CONTROL0 0x454d
#define SEA_mmDIG4_AFMT_INFOFRAME_CONTROL0 0x484d
#define SEA_mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4b4d
#define SEA_mmDIG6_AFMT_INFOFRAME_CONTROL0 0x4e4d
#define SEA_mmAFMT_AUDIO_SRC_CONTROL 0x1c4f
#define SEA_mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x1c4f
#define SEA_mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x1f4f
#define SEA_mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x424f
#define SEA_mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x454f
#define SEA_mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x484f
#define SEA_mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4b4f
#define SEA_mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x4e4f
#define SEA_mmAFMT_AUDIO_DBG_DTO_CNTL 0x1c52
#define SEA_mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x1c52
#define SEA_mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x1f52
#define SEA_mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4252
#define SEA_mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4552
#define SEA_mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4852
#define SEA_mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4b52
#define SEA_mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x4e52
#define SEA_mmDIG_BE_CNTL 0x1c50
#define SEA_mmDIG0_DIG_BE_CNTL 0x1c50
#define SEA_mmDIG1_DIG_BE_CNTL 0x1f50
#define SEA_mmDIG2_DIG_BE_CNTL 0x4250
#define SEA_mmDIG3_DIG_BE_CNTL 0x4550
#define SEA_mmDIG4_DIG_BE_CNTL 0x4850
#define SEA_mmDIG5_DIG_BE_CNTL 0x4b50
#define SEA_mmDIG6_DIG_BE_CNTL 0x4e50
#define SEA_mmDIG_BE_EN_CNTL 0x1c51
#define SEA_mmDIG0_DIG_BE_EN_CNTL 0x1c51
#define SEA_mmDIG1_DIG_BE_EN_CNTL 0x1f51
#define SEA_mmDIG2_DIG_BE_EN_CNTL 0x4251
#define SEA_mmDIG3_DIG_BE_EN_CNTL 0x4551
#define SEA_mmDIG4_DIG_BE_EN_CNTL 0x4851
#define SEA_mmDIG5_DIG_BE_EN_CNTL 0x4b51
#define SEA_mmDIG6_DIG_BE_EN_CNTL 0x4e51
#define SEA_mmTMDS_CNTL 0x1c7c
#define SEA_mmDIG0_TMDS_CNTL 0x1c7c
#define SEA_mmDIG1_TMDS_CNTL 0x1f7c
#define SEA_mmDIG2_TMDS_CNTL 0x427c
#define SEA_mmDIG3_TMDS_CNTL 0x457c
#define SEA_mmDIG4_TMDS_CNTL 0x487c
#define SEA_mmDIG5_TMDS_CNTL 0x4b7c
#define SEA_mmDIG6_TMDS_CNTL 0x4e7c
#define SEA_mmTMDS_CONTROL_CHAR 0x1c7d
#define SEA_mmDIG0_TMDS_CONTROL_CHAR 0x1c7d
#define SEA_mmDIG1_TMDS_CONTROL_CHAR 0x1f7d
#define SEA_mmDIG2_TMDS_CONTROL_CHAR 0x427d
#define SEA_mmDIG3_TMDS_CONTROL_CHAR 0x457d
#define SEA_mmDIG4_TMDS_CONTROL_CHAR 0x487d
#define SEA_mmDIG5_TMDS_CONTROL_CHAR 0x4b7d
#define SEA_mmDIG6_TMDS_CONTROL_CHAR 0x4e7d
#define SEA_mmTMDS_CONTROL0_FEEDBACK 0x1c7e
#define SEA_mmDIG0_TMDS_CONTROL0_FEEDBACK 0x1c7e
#define SEA_mmDIG1_TMDS_CONTROL0_FEEDBACK 0x1f7e
#define SEA_mmDIG2_TMDS_CONTROL0_FEEDBACK 0x427e
#define SEA_mmDIG3_TMDS_CONTROL0_FEEDBACK 0x457e
#define SEA_mmDIG4_TMDS_CONTROL0_FEEDBACK 0x487e
#define SEA_mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4b7e
#define SEA_mmDIG6_TMDS_CONTROL0_FEEDBACK 0x4e7e
#define SEA_mmTMDS_STEREOSYNC_CTL_SEL 0x1c7f
#define SEA_mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x1c7f
#define SEA_mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x1f7f
#define SEA_mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x427f
#define SEA_mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x457f
#define SEA_mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x487f
#define SEA_mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4b7f
#define SEA_mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x4e7f
#define SEA_mmTMDS_SYNC_CHAR_PATTERN_0_1 0x1c80
#define SEA_mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x1c80
#define SEA_mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x1f80
#define SEA_mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4280
#define SEA_mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4580
#define SEA_mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4880
#define SEA_mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b80
#define SEA_mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e80
#define SEA_mmTMDS_SYNC_CHAR_PATTERN_2_3 0x1c81
#define SEA_mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x1c81
#define SEA_mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x1f81
#define SEA_mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4281
#define SEA_mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4581
#define SEA_mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4881
#define SEA_mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b81
#define SEA_mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e81
#define SEA_mmTMDS_DEBUG 0x1c82
#define SEA_mmDIG0_TMDS_DEBUG 0x1c82
#define SEA_mmDIG1_TMDS_DEBUG 0x1f82
#define SEA_mmDIG2_TMDS_DEBUG 0x4282
#define SEA_mmDIG3_TMDS_DEBUG 0x4582
#define SEA_mmDIG4_TMDS_DEBUG 0x4882
#define SEA_mmDIG5_TMDS_DEBUG 0x4b82
#define SEA_mmDIG6_TMDS_DEBUG 0x4e82
#define SEA_mmTMDS_CTL_BITS 0x1c83
#define SEA_mmDIG0_TMDS_CTL_BITS 0x1c83
#define SEA_mmDIG1_TMDS_CTL_BITS 0x1f83
#define SEA_mmDIG2_TMDS_CTL_BITS 0x4283
#define SEA_mmDIG3_TMDS_CTL_BITS 0x4583
#define SEA_mmDIG4_TMDS_CTL_BITS 0x4883
#define SEA_mmDIG5_TMDS_CTL_BITS 0x4b83
#define SEA_mmDIG6_TMDS_CTL_BITS 0x4e83
#define SEA_mmTMDS_DCBALANCER_CONTROL 0x1c84
#define SEA_mmDIG0_TMDS_DCBALANCER_CONTROL 0x1c84
#define SEA_mmDIG1_TMDS_DCBALANCER_CONTROL 0x1f84
#define SEA_mmDIG2_TMDS_DCBALANCER_CONTROL 0x4284
#define SEA_mmDIG3_TMDS_DCBALANCER_CONTROL 0x4584
#define SEA_mmDIG4_TMDS_DCBALANCER_CONTROL 0x4884
#define SEA_mmDIG5_TMDS_DCBALANCER_CONTROL 0x4b84
#define SEA_mmDIG6_TMDS_DCBALANCER_CONTROL 0x4e84
#define SEA_mmTMDS_CTL0_1_GEN_CNTL 0x1c86
#define SEA_mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x1c86
#define SEA_mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x1f86
#define SEA_mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4286
#define SEA_mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4586
#define SEA_mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4886
#define SEA_mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4b86
#define SEA_mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x4e86
#define SEA_mmTMDS_CTL2_3_GEN_CNTL 0x1c87
#define SEA_mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x1c87
#define SEA_mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x1f87
#define SEA_mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4287
#define SEA_mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4587
#define SEA_mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4887
#define SEA_mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4b87
#define SEA_mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x4e87
#define SEA_mmLVDS_DATA_CNTL 0x1c8c
#define SEA_mmDIG0_LVDS_DATA_CNTL 0x1c8c
#define SEA_mmDIG1_LVDS_DATA_CNTL 0x1f8c
#define SEA_mmDIG2_LVDS_DATA_CNTL 0x428c
#define SEA_mmDIG3_LVDS_DATA_CNTL 0x458c
#define SEA_mmDIG4_LVDS_DATA_CNTL 0x488c
#define SEA_mmDIG5_LVDS_DATA_CNTL 0x4b8c
#define SEA_mmDIG6_LVDS_DATA_CNTL 0x4e8c
#define SEA_mmDIG_LANE_ENABLE 0x1c8d
#define SEA_mmDIG0_DIG_LANE_ENABLE 0x1c8d
#define SEA_mmDIG1_DIG_LANE_ENABLE 0x1f8d
#define SEA_mmDIG2_DIG_LANE_ENABLE 0x428d
#define SEA_mmDIG3_DIG_LANE_ENABLE 0x458d
#define SEA_mmDIG4_DIG_LANE_ENABLE 0x488d
#define SEA_mmDIG5_DIG_LANE_ENABLE 0x4b8d
#define SEA_mmDIG6_DIG_LANE_ENABLE 0x4e8d
#define SEA_mmDOUT_SCRATCH0 0x1844
#define SEA_mmDOUT_SCRATCH1 0x1845
#define SEA_mmDOUT_SCRATCH2 0x1846
#define SEA_mmDOUT_SCRATCH3 0x1847
#define SEA_mmDOUT_SCRATCH4 0x1848
#define SEA_mmDOUT_SCRATCH5 0x1849
#define SEA_mmDOUT_SCRATCH6 0x184a
#define SEA_mmDOUT_SCRATCH7 0x184b
#define SEA_mmDOUT_DCE_VCE_CONTROL 0x18ff
#define SEA_mmDC_HPD1_INT_STATUS 0x1807
#define SEA_mmDC_HPD1_INT_CONTROL 0x1808
#define SEA_mmDC_HPD1_CONTROL 0x1809
#define SEA_mmDC_HPD2_INT_STATUS 0x180a
#define SEA_mmDC_HPD2_INT_CONTROL 0x180b
#define SEA_mmDC_HPD2_CONTROL 0x180c
#define SEA_mmDC_HPD3_INT_STATUS 0x180d
#define SEA_mmDC_HPD3_INT_CONTROL 0x180e
#define SEA_mmDC_HPD3_CONTROL 0x180f
#define SEA_mmDC_HPD4_INT_STATUS 0x1810
#define SEA_mmDC_HPD4_INT_CONTROL 0x1811
#define SEA_mmDC_HPD4_CONTROL 0x1812
#define SEA_mmDC_HPD5_INT_STATUS 0x1813
#define SEA_mmDC_HPD5_INT_CONTROL 0x1814
#define SEA_mmDC_HPD5_CONTROL 0x1815
#define SEA_mmDC_HPD6_INT_STATUS 0x1816
#define SEA_mmDC_HPD6_INT_CONTROL 0x1817
#define SEA_mmDC_HPD6_CONTROL 0x1818
#define SEA_mmDC_HPD1_FAST_TRAIN_CNTL 0x1864
#define SEA_mmDC_HPD2_FAST_TRAIN_CNTL 0x1865
#define SEA_mmDC_HPD3_FAST_TRAIN_CNTL 0x1866
#define SEA_mmDC_HPD4_FAST_TRAIN_CNTL 0x1867
#define SEA_mmDC_HPD5_FAST_TRAIN_CNTL 0x1868
#define SEA_mmDC_HPD6_FAST_TRAIN_CNTL 0x1869
#define SEA_mmDC_HPD1_TOGGLE_FILT_CNTL 0x18bc
#define SEA_mmDC_HPD2_TOGGLE_FILT_CNTL 0x18bd
#define SEA_mmDC_HPD3_TOGGLE_FILT_CNTL 0x18be
#define SEA_mmDC_HPD4_TOGGLE_FILT_CNTL 0x18fc
#define SEA_mmDC_HPD5_TOGGLE_FILT_CNTL 0x18fd
#define SEA_mmDC_HPD6_TOGGLE_FILT_CNTL 0x18fe
#define SEA_mmDC_I2C_CONTROL 0x1819
#define SEA_mmDC_I2C_ARBITRATION 0x181a
#define SEA_mmDC_I2C_INTERRUPT_CONTROL 0x181b
#define SEA_mmDC_I2C_SW_STATUS 0x181c
#define SEA_mmDC_I2C_DDC1_HW_STATUS 0x181d
#define SEA_mmDC_I2C_DDC2_HW_STATUS 0x181e
#define SEA_mmDC_I2C_DDC3_HW_STATUS 0x181f
#define SEA_mmDC_I2C_DDC4_HW_STATUS 0x1820
#define SEA_mmDC_I2C_DDC5_HW_STATUS 0x1821
#define SEA_mmDC_I2C_DDC6_HW_STATUS 0x1822
#define SEA_mmDC_I2C_DDC1_SPEED 0x1823
#define SEA_mmDC_I2C_DDC1_SETUP 0x1824
#define SEA_mmDC_I2C_DDC2_SPEED 0x1825
#define SEA_mmDC_I2C_DDC2_SETUP 0x1826
#define SEA_mmDC_I2C_DDC3_SPEED 0x1827
#define SEA_mmDC_I2C_DDC3_SETUP 0x1828
#define SEA_mmDC_I2C_DDC4_SPEED 0x1829
#define SEA_mmDC_I2C_DDC4_SETUP 0x182a
#define SEA_mmDC_I2C_DDC5_SPEED 0x182b
#define SEA_mmDC_I2C_DDC5_SETUP 0x182c
#define SEA_mmDC_I2C_DDC6_SPEED 0x182d
#define SEA_mmDC_I2C_DDC6_SETUP 0x182e
#define SEA_mmDC_I2C_TRANSACTION0 0x182f
#define SEA_mmDC_I2C_TRANSACTION1 0x1830
#define SEA_mmDC_I2C_TRANSACTION2 0x1831
#define SEA_mmDC_I2C_TRANSACTION3 0x1832
#define SEA_mmDC_I2C_DATA 0x1833
#define SEA_mmGENERIC_I2C_CONTROL 0x1834
#define SEA_mmGENERIC_I2C_INTERRUPT_CONTROL 0x1835
#define SEA_mmGENERIC_I2C_STATUS 0x1836
#define SEA_mmGENERIC_I2C_SPEED 0x1837
#define SEA_mmGENERIC_I2C_SETUP 0x1838
#define SEA_mmGENERIC_I2C_TRANSACTION 0x1839
#define SEA_mmGENERIC_I2C_DATA 0x183a
#define SEA_mmGENERIC_I2C_PIN_SELECTION 0x183b
#define SEA_mmGENERIC_I2C_PIN_DEBUG 0x183c
#define SEA_mmDISP_INTERRUPT_STATUS 0x183d
#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE 0x183e
#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE2 0x183f
#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE3 0x1840
#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE4 0x1853
#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE5 0x1854
#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE6 0x19e0
#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE7 0x19e1
#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE8 0x19e2
#define SEA_mmDISP_INTERRUPT_STATUS_CONTINUE9 0x19e3
#define SEA_mmDOUT_POWER_MANAGEMENT_CNTL 0x1841
#define SEA_mmDISP_TIMER_CONTROL 0x1842
#define SEA_mmDC_I2C_DDCVGA_HW_STATUS 0x1855
#define SEA_mmDC_I2C_DDCVGA_SPEED 0x1856
#define SEA_mmDC_I2C_DDCVGA_SETUP 0x1857
#define SEA_mmDC_I2C_EDID_DETECT_CTRL 0x186f
#define SEA_mmDISPOUT_STEREOSYNC_SEL 0x18bf
#define SEA_mmDOUT_TEST_DEBUG_INDEX 0x184d
#define SEA_mmDOUT_TEST_DEBUG_DATA 0x184e
#define SEA_ixDP_AUX1_DEBUG_A 0x10
#define SEA_ixDP_AUX1_DEBUG_B 0x11
#define SEA_ixDP_AUX1_DEBUG_C 0x12
#define SEA_ixDP_AUX1_DEBUG_D 0x13
#define SEA_ixDP_AUX1_DEBUG_E 0x14
#define SEA_ixDP_AUX1_DEBUG_F 0x15
#define SEA_ixDP_AUX1_DEBUG_G 0x16
#define SEA_ixDP_AUX1_DEBUG_H 0x17
#define SEA_ixDP_AUX1_DEBUG_I 0x18
#define SEA_ixDP_AUX1_DEBUG_J 0x19
#define SEA_ixDP_AUX1_DEBUG_K 0x1a
#define SEA_ixDP_AUX1_DEBUG_L 0x1b
#define SEA_ixDP_AUX1_DEBUG_M 0x1c
#define SEA_ixDP_AUX1_DEBUG_N 0x1d
#define SEA_ixDP_AUX1_DEBUG_O 0x1e
#define SEA_ixDP_AUX1_DEBUG_P 0x1f
#define SEA_ixDP_AUX1_DEBUG_Q 0x90
#define SEA_ixDP_AUX2_DEBUG_A 0x20
#define SEA_ixDP_AUX2_DEBUG_B 0x21
#define SEA_ixDP_AUX2_DEBUG_C 0x22
#define SEA_ixDP_AUX2_DEBUG_D 0x23
#define SEA_ixDP_AUX2_DEBUG_E 0x24
#define SEA_ixDP_AUX2_DEBUG_F 0x25
#define SEA_ixDP_AUX2_DEBUG_G 0x26
#define SEA_ixDP_AUX2_DEBUG_H 0x27
#define SEA_ixDP_AUX2_DEBUG_I 0x28
#define SEA_ixDP_AUX2_DEBUG_J 0x29
#define SEA_ixDP_AUX2_DEBUG_K 0x2a
#define SEA_ixDP_AUX2_DEBUG_L 0x2b
#define SEA_ixDP_AUX2_DEBUG_M 0x2c
#define SEA_ixDP_AUX2_DEBUG_N 0x2d
#define SEA_ixDP_AUX2_DEBUG_O 0x2e
#define SEA_ixDP_AUX2_DEBUG_P 0x2f
#define SEA_ixDP_AUX2_DEBUG_Q 0x91
#define SEA_ixDP_AUX3_DEBUG_A 0x30
#define SEA_ixDP_AUX3_DEBUG_B 0x31
#define SEA_ixDP_AUX3_DEBUG_C 0x32
#define SEA_ixDP_AUX3_DEBUG_D 0x33
#define SEA_ixDP_AUX3_DEBUG_E 0x34
#define SEA_ixDP_AUX3_DEBUG_F 0x35
#define SEA_ixDP_AUX3_DEBUG_G 0x36
#define SEA_ixDP_AUX3_DEBUG_H 0x37
#define SEA_ixDP_AUX3_DEBUG_I 0x38
#define SEA_ixDP_AUX3_DEBUG_J 0x39
#define SEA_ixDP_AUX3_DEBUG_K 0x3a
#define SEA_ixDP_AUX3_DEBUG_L 0x3b
#define SEA_ixDP_AUX3_DEBUG_M 0x3c
#define SEA_ixDP_AUX3_DEBUG_N 0x3d
#define SEA_ixDP_AUX3_DEBUG_O 0x3e
#define SEA_ixDP_AUX3_DEBUG_P 0x3f
#define SEA_ixDP_AUX3_DEBUG_Q 0x92
#define SEA_ixDP_AUX4_DEBUG_A 0x40
#define SEA_ixDP_AUX4_DEBUG_B 0x41
#define SEA_ixDP_AUX4_DEBUG_C 0x42
#define SEA_ixDP_AUX4_DEBUG_D 0x43
#define SEA_ixDP_AUX4_DEBUG_E 0x44
#define SEA_ixDP_AUX4_DEBUG_F 0x45
#define SEA_ixDP_AUX4_DEBUG_G 0x46
#define SEA_ixDP_AUX4_DEBUG_H 0x47
#define SEA_ixDP_AUX4_DEBUG_I 0x48
#define SEA_ixDP_AUX4_DEBUG_J 0x49
#define SEA_ixDP_AUX4_DEBUG_K 0x4a
#define SEA_ixDP_AUX4_DEBUG_L 0x4b
#define SEA_ixDP_AUX4_DEBUG_M 0x4c
#define SEA_ixDP_AUX4_DEBUG_N 0x4d
#define SEA_ixDP_AUX4_DEBUG_O 0x4e
#define SEA_ixDP_AUX4_DEBUG_P 0x4f
#define SEA_ixDP_AUX4_DEBUG_Q 0x93
#define SEA_ixDP_AUX5_DEBUG_A 0x70
#define SEA_ixDP_AUX5_DEBUG_B 0x71
#define SEA_ixDP_AUX5_DEBUG_C 0x72
#define SEA_ixDP_AUX5_DEBUG_D 0x73
#define SEA_ixDP_AUX5_DEBUG_E 0x74
#define SEA_ixDP_AUX5_DEBUG_F 0x75
#define SEA_ixDP_AUX5_DEBUG_G 0x76
#define SEA_ixDP_AUX5_DEBUG_H 0x77
#define SEA_ixDP_AUX5_DEBUG_I 0x78
#define SEA_ixDP_AUX5_DEBUG_J 0x79
#define SEA_ixDP_AUX5_DEBUG_K 0x7a
#define SEA_ixDP_AUX5_DEBUG_L 0x7b
#define SEA_ixDP_AUX5_DEBUG_M 0x7c
#define SEA_ixDP_AUX5_DEBUG_N 0x7d
#define SEA_ixDP_AUX5_DEBUG_O 0x7f
#define SEA_ixDP_AUX5_DEBUG_P 0x94
#define SEA_ixDP_AUX5_DEBUG_Q 0x95
#define SEA_ixDP_AUX6_DEBUG_A 0x80
#define SEA_ixDP_AUX6_DEBUG_B 0x81
#define SEA_ixDP_AUX6_DEBUG_C 0x82
#define SEA_ixDP_AUX6_DEBUG_D 0x83
#define SEA_ixDP_AUX6_DEBUG_E 0x84
#define SEA_ixDP_AUX6_DEBUG_F 0x85
#define SEA_ixDP_AUX6_DEBUG_G 0x86
#define SEA_ixDP_AUX6_DEBUG_H 0x87
#define SEA_ixDP_AUX6_DEBUG_I 0x88
#define SEA_ixDP_AUX6_DEBUG_J 0x89
#define SEA_ixDP_AUX6_DEBUG_K 0x8a
#define SEA_ixDP_AUX6_DEBUG_L 0x8b
#define SEA_ixDP_AUX6_DEBUG_M 0x8c
#define SEA_ixDP_AUX6_DEBUG_N 0x8d
#define SEA_ixDP_AUX6_DEBUG_O 0x8f
#define SEA_ixDP_AUX6_DEBUG_P 0x96
#define SEA_ixDP_AUX6_DEBUG_Q 0x97
#define SEA_mmDMCU_CTRL 0x1600
#define SEA_mmDMCU_STATUS 0x1601
#define SEA_mmDMCU_PC_START_ADDR 0x1602
#define SEA_mmDMCU_FW_START_ADDR 0x1603
#define SEA_mmDMCU_FW_END_ADDR 0x1604
#define SEA_mmDMCU_FW_ISR_START_ADDR 0x1605
#define SEA_mmDMCU_FW_CS_HI 0x1606
#define SEA_mmDMCU_FW_CS_LO 0x1607
#define SEA_mmDMCU_RAM_ACCESS_CTRL 0x1608
#define SEA_mmDMCU_ERAM_WR_CTRL 0x1609
#define SEA_mmDMCU_ERAM_WR_DATA 0x160a
#define SEA_mmDMCU_ERAM_RD_CTRL 0x160b
#define SEA_mmDMCU_ERAM_RD_DATA 0x160c
#define SEA_mmDMCU_IRAM_WR_CTRL 0x160d
#define SEA_mmDMCU_IRAM_WR_DATA 0x160e
#define SEA_mmDMCU_IRAM_RD_CTRL 0x160f
#define SEA_mmDMCU_IRAM_RD_DATA 0x1610
#define SEA_mmDMCU_EVENT_TRIGGER 0x1611
#define SEA_mmDMCU_UC_INTERNAL_INT_STATUS 0x1612
#define SEA_mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613
#define SEA_mmDMCU_INTERRUPT_STATUS 0x1614
#define SEA_mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615
#define SEA_mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616
#define SEA_mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617
#define SEA_mmDC_DMCU_SCRATCH 0x1618
#define SEA_mmDMCU_INT_CNT 0x1619
#define SEA_mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a
#define SEA_mmDMCU_UC_CLK_GATING_CNTL 0x161b
#define SEA_mmMASTER_COMM_DATA_REG1 0x161c
#define SEA_mmMASTER_COMM_DATA_REG2 0x161d
#define SEA_mmMASTER_COMM_DATA_REG3 0x161e
#define SEA_mmMASTER_COMM_CMD_REG 0x161f
#define SEA_mmMASTER_COMM_CNTL_REG 0x1620
#define SEA_mmSLAVE_COMM_DATA_REG1 0x1621
#define SEA_mmSLAVE_COMM_DATA_REG2 0x1622
#define SEA_mmSLAVE_COMM_DATA_REG3 0x1623
#define SEA_mmSLAVE_COMM_CMD_REG 0x1624
#define SEA_mmSLAVE_COMM_CNTL_REG 0x1625
#define SEA_mmDMCU_TEST_DEBUG_INDEX 0x1626
#define SEA_mmDMCU_TEST_DEBUG_DATA 0x1627
#define SEA_mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1750
#define SEA_mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1751
#define SEA_mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1752
#define SEA_mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1753
#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1754
#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1755
#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1756
#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1757
#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1758
#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1759
#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x175a
#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x175b
#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1 0x175c
#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2 0x175d
#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3 0x175e
#define SEA_mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4 0x175f
#define SEA_mmDP_LINK_CNTL 0x1cc0
#define SEA_mmDP0_DP_LINK_CNTL 0x1cc0
#define SEA_mmDP1_DP_LINK_CNTL 0x1fc0
#define SEA_mmDP2_DP_LINK_CNTL 0x42c0
#define SEA_mmDP3_DP_LINK_CNTL 0x45c0
#define SEA_mmDP4_DP_LINK_CNTL 0x48c0
#define SEA_mmDP5_DP_LINK_CNTL 0x4bc0
#define SEA_mmDP6_DP_LINK_CNTL 0x4ec0
#define SEA_mmDP_PIXEL_FORMAT 0x1cc1
#define SEA_mmDP0_DP_PIXEL_FORMAT 0x1cc1
#define SEA_mmDP1_DP_PIXEL_FORMAT 0x1fc1
#define SEA_mmDP2_DP_PIXEL_FORMAT 0x42c1
#define SEA_mmDP3_DP_PIXEL_FORMAT 0x45c1
#define SEA_mmDP4_DP_PIXEL_FORMAT 0x48c1
#define SEA_mmDP5_DP_PIXEL_FORMAT 0x4bc1
#define SEA_mmDP6_DP_PIXEL_FORMAT 0x4ec1
#define SEA_mmDP_MSA_COLORIMETRY 0x1cda
#define SEA_mmDP0_DP_MSA_COLORIMETRY 0x1cda
#define SEA_mmDP1_DP_MSA_COLORIMETRY 0x1fda
#define SEA_mmDP2_DP_MSA_COLORIMETRY 0x42da
#define SEA_mmDP3_DP_MSA_COLORIMETRY 0x45da
#define SEA_mmDP4_DP_MSA_COLORIMETRY 0x48da
#define SEA_mmDP5_DP_MSA_COLORIMETRY 0x4bda
#define SEA_mmDP6_DP_MSA_COLORIMETRY 0x4eda
#define SEA_mmDP_CONFIG 0x1cc2
#define SEA_mmDP0_DP_CONFIG 0x1cc2
#define SEA_mmDP1_DP_CONFIG 0x1fc2
#define SEA_mmDP2_DP_CONFIG 0x42c2
#define SEA_mmDP3_DP_CONFIG 0x45c2
#define SEA_mmDP4_DP_CONFIG 0x48c2
#define SEA_mmDP5_DP_CONFIG 0x4bc2
#define SEA_mmDP6_DP_CONFIG 0x4ec2
#define SEA_mmDP_VID_STREAM_CNTL 0x1cc3
#define SEA_mmDP0_DP_VID_STREAM_CNTL 0x1cc3
#define SEA_mmDP1_DP_VID_STREAM_CNTL 0x1fc3
#define SEA_mmDP2_DP_VID_STREAM_CNTL 0x42c3
#define SEA_mmDP3_DP_VID_STREAM_CNTL 0x45c3
#define SEA_mmDP4_DP_VID_STREAM_CNTL 0x48c3
#define SEA_mmDP5_DP_VID_STREAM_CNTL 0x4bc3
#define SEA_mmDP6_DP_VID_STREAM_CNTL 0x4ec3
#define SEA_mmDP_STEER_FIFO 0x1cc4
#define SEA_mmDP0_DP_STEER_FIFO 0x1cc4
#define SEA_mmDP1_DP_STEER_FIFO 0x1fc4
#define SEA_mmDP2_DP_STEER_FIFO 0x42c4
#define SEA_mmDP3_DP_STEER_FIFO 0x45c4
#define SEA_mmDP4_DP_STEER_FIFO 0x48c4
#define SEA_mmDP5_DP_STEER_FIFO 0x4bc4
#define SEA_mmDP6_DP_STEER_FIFO 0x4ec4
#define SEA_mmDP_MSA_MISC 0x1cc5
#define SEA_mmDP0_DP_MSA_MISC 0x1cc5
#define SEA_mmDP1_DP_MSA_MISC 0x1fc5
#define SEA_mmDP2_DP_MSA_MISC 0x42c5
#define SEA_mmDP3_DP_MSA_MISC 0x45c5
#define SEA_mmDP4_DP_MSA_MISC 0x48c5
#define SEA_mmDP5_DP_MSA_MISC 0x4bc5
#define SEA_mmDP6_DP_MSA_MISC 0x4ec5
#define SEA_mmDP_VID_TIMING 0x1cc9
#define SEA_mmDP0_DP_VID_TIMING 0x1cc9
#define SEA_mmDP1_DP_VID_TIMING 0x1fc9
#define SEA_mmDP2_DP_VID_TIMING 0x42c9
#define SEA_mmDP3_DP_VID_TIMING 0x45c9
#define SEA_mmDP4_DP_VID_TIMING 0x48c9
#define SEA_mmDP5_DP_VID_TIMING 0x4bc9
#define SEA_mmDP6_DP_VID_TIMING 0x4ec9
#define SEA_mmDP_VID_N 0x1cca
#define SEA_mmDP0_DP_VID_N 0x1cca
#define SEA_mmDP1_DP_VID_N 0x1fca
#define SEA_mmDP2_DP_VID_N 0x42ca
#define SEA_mmDP3_DP_VID_N 0x45ca
#define SEA_mmDP4_DP_VID_N 0x48ca
#define SEA_mmDP5_DP_VID_N 0x4bca
#define SEA_mmDP6_DP_VID_N 0x4eca
#define SEA_mmDP_VID_M 0x1ccb
#define SEA_mmDP0_DP_VID_M 0x1ccb
#define SEA_mmDP1_DP_VID_M 0x1fcb
#define SEA_mmDP2_DP_VID_M 0x42cb
#define SEA_mmDP3_DP_VID_M 0x45cb
#define SEA_mmDP4_DP_VID_M 0x48cb
#define SEA_mmDP5_DP_VID_M 0x4bcb
#define SEA_mmDP6_DP_VID_M 0x4ecb
#define SEA_mmDP_LINK_FRAMING_CNTL 0x1ccc
#define SEA_mmDP0_DP_LINK_FRAMING_CNTL 0x1ccc
#define SEA_mmDP1_DP_LINK_FRAMING_CNTL 0x1fcc
#define SEA_mmDP2_DP_LINK_FRAMING_CNTL 0x42cc
#define SEA_mmDP3_DP_LINK_FRAMING_CNTL 0x45cc
#define SEA_mmDP4_DP_LINK_FRAMING_CNTL 0x48cc
#define SEA_mmDP5_DP_LINK_FRAMING_CNTL 0x4bcc
#define SEA_mmDP6_DP_LINK_FRAMING_CNTL 0x4ecc
#define SEA_mmDP_HBR2_EYE_PATTERN 0x1cc8
#define SEA_mmDP0_DP_HBR2_EYE_PATTERN 0x1cc8
#define SEA_mmDP1_DP_HBR2_EYE_PATTERN 0x1fc8
#define SEA_mmDP2_DP_HBR2_EYE_PATTERN 0x42c8
#define SEA_mmDP3_DP_HBR2_EYE_PATTERN 0x45c8
#define SEA_mmDP4_DP_HBR2_EYE_PATTERN 0x48c8
#define SEA_mmDP5_DP_HBR2_EYE_PATTERN 0x4bc8
#define SEA_mmDP6_DP_HBR2_EYE_PATTERN 0x4ec8
#define SEA_mmDP_VID_MSA_VBID 0x1ccd
#define SEA_mmDP0_DP_VID_MSA_VBID 0x1ccd
#define SEA_mmDP1_DP_VID_MSA_VBID 0x1fcd
#define SEA_mmDP2_DP_VID_MSA_VBID 0x42cd
#define SEA_mmDP3_DP_VID_MSA_VBID 0x45cd
#define SEA_mmDP4_DP_VID_MSA_VBID 0x48cd
#define SEA_mmDP5_DP_VID_MSA_VBID 0x4bcd
#define SEA_mmDP6_DP_VID_MSA_VBID 0x4ecd
#define SEA_mmDP_VID_INTERRUPT_CNTL 0x1ccf
#define SEA_mmDP0_DP_VID_INTERRUPT_CNTL 0x1ccf
#define SEA_mmDP1_DP_VID_INTERRUPT_CNTL 0x1fcf
#define SEA_mmDP2_DP_VID_INTERRUPT_CNTL 0x42cf
#define SEA_mmDP3_DP_VID_INTERRUPT_CNTL 0x45cf
#define SEA_mmDP4_DP_VID_INTERRUPT_CNTL 0x48cf
#define SEA_mmDP5_DP_VID_INTERRUPT_CNTL 0x4bcf
#define SEA_mmDP6_DP_VID_INTERRUPT_CNTL 0x4ecf
#define SEA_mmDP_DPHY_CNTL 0x1cd0
#define SEA_mmDP0_DP_DPHY_CNTL 0x1cd0
#define SEA_mmDP1_DP_DPHY_CNTL 0x1fd0
#define SEA_mmDP2_DP_DPHY_CNTL 0x42d0
#define SEA_mmDP3_DP_DPHY_CNTL 0x45d0
#define SEA_mmDP4_DP_DPHY_CNTL 0x48d0
#define SEA_mmDP5_DP_DPHY_CNTL 0x4bd0
#define SEA_mmDP6_DP_DPHY_CNTL 0x4ed0
#define SEA_mmDP_DPHY_TRAINING_PATTERN_SEL 0x1cd1
#define SEA_mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x1cd1
#define SEA_mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1fd1
#define SEA_mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x42d1
#define SEA_mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x45d1
#define SEA_mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x48d1
#define SEA_mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4bd1
#define SEA_mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x4ed1
#define SEA_mmDP_DPHY_SYM0 0x1cd2
#define SEA_mmDP0_DP_DPHY_SYM0 0x1cd2
#define SEA_mmDP1_DP_DPHY_SYM0 0x1fd2
#define SEA_mmDP2_DP_DPHY_SYM0 0x42d2
#define SEA_mmDP3_DP_DPHY_SYM0 0x45d2
#define SEA_mmDP4_DP_DPHY_SYM0 0x48d2
#define SEA_mmDP5_DP_DPHY_SYM0 0x4bd2
#define SEA_mmDP6_DP_DPHY_SYM0 0x4ed2
#define SEA_mmDP_DPHY_SYM1 0x1ce0
#define SEA_mmDP0_DP_DPHY_SYM1 0x1ce0
#define SEA_mmDP1_DP_DPHY_SYM1 0x1fe0
#define SEA_mmDP2_DP_DPHY_SYM1 0x42e0
#define SEA_mmDP3_DP_DPHY_SYM1 0x45e0
#define SEA_mmDP4_DP_DPHY_SYM1 0x48e0
#define SEA_mmDP5_DP_DPHY_SYM1 0x4be0
#define SEA_mmDP6_DP_DPHY_SYM1 0x4ee0
#define SEA_mmDP_DPHY_SYM2 0x1cdf
#define SEA_mmDP0_DP_DPHY_SYM2 0x1cdf
#define SEA_mmDP1_DP_DPHY_SYM2 0x1fdf
#define SEA_mmDP2_DP_DPHY_SYM2 0x42df
#define SEA_mmDP3_DP_DPHY_SYM2 0x45df
#define SEA_mmDP4_DP_DPHY_SYM2 0x48df
#define SEA_mmDP5_DP_DPHY_SYM2 0x4bdf
#define SEA_mmDP6_DP_DPHY_SYM2 0x4edf
#define SEA_mmDP_DPHY_8B10B_CNTL 0x1cd3
#define SEA_mmDP0_DP_DPHY_8B10B_CNTL 0x1cd3
#define SEA_mmDP1_DP_DPHY_8B10B_CNTL 0x1fd3
#define SEA_mmDP2_DP_DPHY_8B10B_CNTL 0x42d3
#define SEA_mmDP3_DP_DPHY_8B10B_CNTL 0x45d3
#define SEA_mmDP4_DP_DPHY_8B10B_CNTL 0x48d3
#define SEA_mmDP5_DP_DPHY_8B10B_CNTL 0x4bd3
#define SEA_mmDP6_DP_DPHY_8B10B_CNTL 0x4ed3
#define SEA_mmDP_DPHY_PRBS_CNTL 0x1cd4
#define SEA_mmDP0_DP_DPHY_PRBS_CNTL 0x1cd4
#define SEA_mmDP1_DP_DPHY_PRBS_CNTL 0x1fd4
#define SEA_mmDP2_DP_DPHY_PRBS_CNTL 0x42d4
#define SEA_mmDP3_DP_DPHY_PRBS_CNTL 0x45d4
#define SEA_mmDP4_DP_DPHY_PRBS_CNTL 0x48d4
#define SEA_mmDP5_DP_DPHY_PRBS_CNTL 0x4bd4
#define SEA_mmDP6_DP_DPHY_PRBS_CNTL 0x4ed4
#define SEA_mmDP_DPHY_CRC_EN 0x1cd6
#define SEA_mmDP0_DP_DPHY_CRC_EN 0x1cd6
#define SEA_mmDP1_DP_DPHY_CRC_EN 0x1fd6
#define SEA_mmDP2_DP_DPHY_CRC_EN 0x42d6
#define SEA_mmDP3_DP_DPHY_CRC_EN 0x45d6
#define SEA_mmDP4_DP_DPHY_CRC_EN 0x48d6
#define SEA_mmDP5_DP_DPHY_CRC_EN 0x4bd6
#define SEA_mmDP6_DP_DPHY_CRC_EN 0x4ed6
#define SEA_mmDP_DPHY_CRC_CNTL 0x1cd7
#define SEA_mmDP0_DP_DPHY_CRC_CNTL 0x1cd7
#define SEA_mmDP1_DP_DPHY_CRC_CNTL 0x1fd7
#define SEA_mmDP2_DP_DPHY_CRC_CNTL 0x42d7
#define SEA_mmDP3_DP_DPHY_CRC_CNTL 0x45d7
#define SEA_mmDP4_DP_DPHY_CRC_CNTL 0x48d7
#define SEA_mmDP5_DP_DPHY_CRC_CNTL 0x4bd7
#define SEA_mmDP6_DP_DPHY_CRC_CNTL 0x4ed7
#define SEA_mmDP_DPHY_CRC_RESULT 0x1cd8
#define SEA_mmDP0_DP_DPHY_CRC_RESULT 0x1cd8
#define SEA_mmDP1_DP_DPHY_CRC_RESULT 0x1fd8
#define SEA_mmDP2_DP_DPHY_CRC_RESULT 0x42d8
#define SEA_mmDP3_DP_DPHY_CRC_RESULT 0x45d8
#define SEA_mmDP4_DP_DPHY_CRC_RESULT 0x48d8
#define SEA_mmDP5_DP_DPHY_CRC_RESULT 0x4bd8
#define SEA_mmDP6_DP_DPHY_CRC_RESULT 0x4ed8
#define SEA_mmDP_DPHY_CRC_MST_CNTL 0x1cc6
#define SEA_mmDP0_DP_DPHY_CRC_MST_CNTL 0x1cc6
#define SEA_mmDP1_DP_DPHY_CRC_MST_CNTL 0x1fc6
#define SEA_mmDP2_DP_DPHY_CRC_MST_CNTL 0x42c6
#define SEA_mmDP3_DP_DPHY_CRC_MST_CNTL 0x45c6
#define SEA_mmDP4_DP_DPHY_CRC_MST_CNTL 0x48c6
#define SEA_mmDP5_DP_DPHY_CRC_MST_CNTL 0x4bc6
#define SEA_mmDP6_DP_DPHY_CRC_MST_CNTL 0x4ec6
#define SEA_mmDP_DPHY_CRC_MST_STATUS 0x1cc7
#define SEA_mmDP0_DP_DPHY_CRC_MST_STATUS 0x1cc7
#define SEA_mmDP1_DP_DPHY_CRC_MST_STATUS 0x1fc7
#define SEA_mmDP2_DP_DPHY_CRC_MST_STATUS 0x42c7
#define SEA_mmDP3_DP_DPHY_CRC_MST_STATUS 0x45c7
#define SEA_mmDP4_DP_DPHY_CRC_MST_STATUS 0x48c7
#define SEA_mmDP5_DP_DPHY_CRC_MST_STATUS 0x4bc7
#define SEA_mmDP6_DP_DPHY_CRC_MST_STATUS 0x4ec7
#define SEA_mmDP_DPHY_FAST_TRAINING 0x1cce
#define SEA_mmDP0_DP_DPHY_FAST_TRAINING 0x1cce
#define SEA_mmDP1_DP_DPHY_FAST_TRAINING 0x1fce
#define SEA_mmDP2_DP_DPHY_FAST_TRAINING 0x42ce
#define SEA_mmDP3_DP_DPHY_FAST_TRAINING 0x45ce
#define SEA_mmDP4_DP_DPHY_FAST_TRAINING 0x48ce
#define SEA_mmDP5_DP_DPHY_FAST_TRAINING 0x4bce
#define SEA_mmDP6_DP_DPHY_FAST_TRAINING 0x4ece
#define SEA_mmDP_DPHY_FAST_TRAINING_STATUS 0x1ce9
#define SEA_mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x1ce9
#define SEA_mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1fe9
#define SEA_mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x42e9
#define SEA_mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x45e9
#define SEA_mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x48e9
#define SEA_mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4be9
#define SEA_mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x4ee9
#define SEA_mmDP_MSA_V_TIMING_OVERRIDE1 0x1cea
#define SEA_mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x1cea
#define SEA_mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1fea
#define SEA_mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x42ea
#define SEA_mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x45ea
#define SEA_mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x48ea
#define SEA_mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4bea
#define SEA_mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x4eea
#define SEA_mmDP_MSA_V_TIMING_OVERRIDE2 0x1ceb
#define SEA_mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x1ceb
#define SEA_mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1feb
#define SEA_mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x42eb
#define SEA_mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x45eb
#define SEA_mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x48eb
#define SEA_mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4beb
#define SEA_mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x4eeb
#define SEA_mmDP_SEC_CNTL 0x1ca0
#define SEA_mmDP0_DP_SEC_CNTL 0x1ca0
#define SEA_mmDP1_DP_SEC_CNTL 0x1fa0
#define SEA_mmDP2_DP_SEC_CNTL 0x42a0
#define SEA_mmDP3_DP_SEC_CNTL 0x45a0
#define SEA_mmDP4_DP_SEC_CNTL 0x48a0
#define SEA_mmDP5_DP_SEC_CNTL 0x4ba0
#define SEA_mmDP6_DP_SEC_CNTL 0x4ea0
#define SEA_mmDP_SEC_CNTL1 0x1cab
#define SEA_mmDP0_DP_SEC_CNTL1 0x1cab
#define SEA_mmDP1_DP_SEC_CNTL1 0x1fab
#define SEA_mmDP2_DP_SEC_CNTL1 0x42ab
#define SEA_mmDP3_DP_SEC_CNTL1 0x45ab
#define SEA_mmDP4_DP_SEC_CNTL1 0x48ab
#define SEA_mmDP5_DP_SEC_CNTL1 0x4bab
#define SEA_mmDP6_DP_SEC_CNTL1 0x4eab
#define SEA_mmDP_SEC_FRAMING1 0x1ca1
#define SEA_mmDP0_DP_SEC_FRAMING1 0x1ca1
#define SEA_mmDP1_DP_SEC_FRAMING1 0x1fa1
#define SEA_mmDP2_DP_SEC_FRAMING1 0x42a1
#define SEA_mmDP3_DP_SEC_FRAMING1 0x45a1
#define SEA_mmDP4_DP_SEC_FRAMING1 0x48a1
#define SEA_mmDP5_DP_SEC_FRAMING1 0x4ba1
#define SEA_mmDP6_DP_SEC_FRAMING1 0x4ea1
#define SEA_mmDP_SEC_FRAMING2 0x1ca2
#define SEA_mmDP0_DP_SEC_FRAMING2 0x1ca2
#define SEA_mmDP1_DP_SEC_FRAMING2 0x1fa2
#define SEA_mmDP2_DP_SEC_FRAMING2 0x42a2
#define SEA_mmDP3_DP_SEC_FRAMING2 0x45a2
#define SEA_mmDP4_DP_SEC_FRAMING2 0x48a2
#define SEA_mmDP5_DP_SEC_FRAMING2 0x4ba2
#define SEA_mmDP6_DP_SEC_FRAMING2 0x4ea2
#define SEA_mmDP_SEC_FRAMING3 0x1ca3
#define SEA_mmDP0_DP_SEC_FRAMING3 0x1ca3
#define SEA_mmDP1_DP_SEC_FRAMING3 0x1fa3
#define SEA_mmDP2_DP_SEC_FRAMING3 0x42a3
#define SEA_mmDP3_DP_SEC_FRAMING3 0x45a3
#define SEA_mmDP4_DP_SEC_FRAMING3 0x48a3
#define SEA_mmDP5_DP_SEC_FRAMING3 0x4ba3
#define SEA_mmDP6_DP_SEC_FRAMING3 0x4ea3
#define SEA_mmDP_SEC_FRAMING4 0x1ca4
#define SEA_mmDP0_DP_SEC_FRAMING4 0x1ca4
#define SEA_mmDP1_DP_SEC_FRAMING4 0x1fa4
#define SEA_mmDP2_DP_SEC_FRAMING4 0x42a4
#define SEA_mmDP3_DP_SEC_FRAMING4 0x45a4
#define SEA_mmDP4_DP_SEC_FRAMING4 0x48a4
#define SEA_mmDP5_DP_SEC_FRAMING4 0x4ba4
#define SEA_mmDP6_DP_SEC_FRAMING4 0x4ea4
#define SEA_mmDP_SEC_AUD_N 0x1ca5
#define SEA_mmDP0_DP_SEC_AUD_N 0x1ca5
#define SEA_mmDP1_DP_SEC_AUD_N 0x1fa5
#define SEA_mmDP2_DP_SEC_AUD_N 0x42a5
#define SEA_mmDP3_DP_SEC_AUD_N 0x45a5
#define SEA_mmDP4_DP_SEC_AUD_N 0x48a5
#define SEA_mmDP5_DP_SEC_AUD_N 0x4ba5
#define SEA_mmDP6_DP_SEC_AUD_N 0x4ea5
#define SEA_mmDP_SEC_AUD_N_READBACK 0x1ca6
#define SEA_mmDP0_DP_SEC_AUD_N_READBACK 0x1ca6
#define SEA_mmDP1_DP_SEC_AUD_N_READBACK 0x1fa6
#define SEA_mmDP2_DP_SEC_AUD_N_READBACK 0x42a6
#define SEA_mmDP3_DP_SEC_AUD_N_READBACK 0x45a6
#define SEA_mmDP4_DP_SEC_AUD_N_READBACK 0x48a6
#define SEA_mmDP5_DP_SEC_AUD_N_READBACK 0x4ba6
#define SEA_mmDP6_DP_SEC_AUD_N_READBACK 0x4ea6
#define SEA_mmDP_SEC_AUD_M 0x1ca7
#define SEA_mmDP0_DP_SEC_AUD_M 0x1ca7
#define SEA_mmDP1_DP_SEC_AUD_M 0x1fa7
#define SEA_mmDP2_DP_SEC_AUD_M 0x42a7
#define SEA_mmDP3_DP_SEC_AUD_M 0x45a7
#define SEA_mmDP4_DP_SEC_AUD_M 0x48a7
#define SEA_mmDP5_DP_SEC_AUD_M 0x4ba7
#define SEA_mmDP6_DP_SEC_AUD_M 0x4ea7
#define SEA_mmDP_SEC_AUD_M_READBACK 0x1ca8
#define SEA_mmDP0_DP_SEC_AUD_M_READBACK 0x1ca8
#define SEA_mmDP1_DP_SEC_AUD_M_READBACK 0x1fa8
#define SEA_mmDP2_DP_SEC_AUD_M_READBACK 0x42a8
#define SEA_mmDP3_DP_SEC_AUD_M_READBACK 0x45a8
#define SEA_mmDP4_DP_SEC_AUD_M_READBACK 0x48a8
#define SEA_mmDP5_DP_SEC_AUD_M_READBACK 0x4ba8
#define SEA_mmDP6_DP_SEC_AUD_M_READBACK 0x4ea8
#define SEA_mmDP_SEC_TIMESTAMP 0x1ca9
#define SEA_mmDP0_DP_SEC_TIMESTAMP 0x1ca9
#define SEA_mmDP1_DP_SEC_TIMESTAMP 0x1fa9
#define SEA_mmDP2_DP_SEC_TIMESTAMP 0x42a9
#define SEA_mmDP3_DP_SEC_TIMESTAMP 0x45a9
#define SEA_mmDP4_DP_SEC_TIMESTAMP 0x48a9
#define SEA_mmDP5_DP_SEC_TIMESTAMP 0x4ba9
#define SEA_mmDP6_DP_SEC_TIMESTAMP 0x4ea9
#define SEA_mmDP_SEC_PACKET_CNTL 0x1caa
#define SEA_mmDP0_DP_SEC_PACKET_CNTL 0x1caa
#define SEA_mmDP1_DP_SEC_PACKET_CNTL 0x1faa
#define SEA_mmDP2_DP_SEC_PACKET_CNTL 0x42aa
#define SEA_mmDP3_DP_SEC_PACKET_CNTL 0x45aa
#define SEA_mmDP4_DP_SEC_PACKET_CNTL 0x48aa
#define SEA_mmDP5_DP_SEC_PACKET_CNTL 0x4baa
#define SEA_mmDP6_DP_SEC_PACKET_CNTL 0x4eaa
#define SEA_mmDP_MSE_RATE_CNTL 0x1ce1
#define SEA_mmDP0_DP_MSE_RATE_CNTL 0x1ce1
#define SEA_mmDP1_DP_MSE_RATE_CNTL 0x1fe1
#define SEA_mmDP2_DP_MSE_RATE_CNTL 0x42e1
#define SEA_mmDP3_DP_MSE_RATE_CNTL 0x45e1
#define SEA_mmDP4_DP_MSE_RATE_CNTL 0x48e1
#define SEA_mmDP5_DP_MSE_RATE_CNTL 0x4be1
#define SEA_mmDP6_DP_MSE_RATE_CNTL 0x4ee1
#define SEA_mmDP_MSE_RATE_UPDATE 0x1ce3
#define SEA_mmDP0_DP_MSE_RATE_UPDATE 0x1ce3
#define SEA_mmDP1_DP_MSE_RATE_UPDATE 0x1fe3
#define SEA_mmDP2_DP_MSE_RATE_UPDATE 0x42e3
#define SEA_mmDP3_DP_MSE_RATE_UPDATE 0x45e3
#define SEA_mmDP4_DP_MSE_RATE_UPDATE 0x48e3
#define SEA_mmDP5_DP_MSE_RATE_UPDATE 0x4be3
#define SEA_mmDP6_DP_MSE_RATE_UPDATE 0x4ee3
#define SEA_mmDP_MSE_SAT0 0x1ce4
#define SEA_mmDP0_DP_MSE_SAT0 0x1ce4
#define SEA_mmDP1_DP_MSE_SAT0 0x1fe4
#define SEA_mmDP2_DP_MSE_SAT0 0x42e4
#define SEA_mmDP3_DP_MSE_SAT0 0x45e4
#define SEA_mmDP4_DP_MSE_SAT0 0x48e4
#define SEA_mmDP5_DP_MSE_SAT0 0x4be4
#define SEA_mmDP6_DP_MSE_SAT0 0x4ee4
#define SEA_mmDP_MSE_SAT1 0x1ce5
#define SEA_mmDP0_DP_MSE_SAT1 0x1ce5
#define SEA_mmDP1_DP_MSE_SAT1 0x1fe5
#define SEA_mmDP2_DP_MSE_SAT1 0x42e5
#define SEA_mmDP3_DP_MSE_SAT1 0x45e5
#define SEA_mmDP4_DP_MSE_SAT1 0x48e5
#define SEA_mmDP5_DP_MSE_SAT1 0x4be5
#define SEA_mmDP6_DP_MSE_SAT1 0x4ee5
#define SEA_mmDP_MSE_SAT2 0x1ce6
#define SEA_mmDP0_DP_MSE_SAT2 0x1ce6
#define SEA_mmDP1_DP_MSE_SAT2 0x1fe6
#define SEA_mmDP2_DP_MSE_SAT2 0x42e6
#define SEA_mmDP3_DP_MSE_SAT2 0x45e6
#define SEA_mmDP4_DP_MSE_SAT2 0x48e6
#define SEA_mmDP5_DP_MSE_SAT2 0x4be6
#define SEA_mmDP6_DP_MSE_SAT2 0x4ee6
#define SEA_mmDP_MSE_SAT_UPDATE 0x1ce7
#define SEA_mmDP0_DP_MSE_SAT_UPDATE 0x1ce7
#define SEA_mmDP1_DP_MSE_SAT_UPDATE 0x1fe7
#define SEA_mmDP2_DP_MSE_SAT_UPDATE 0x42e7
#define SEA_mmDP3_DP_MSE_SAT_UPDATE 0x45e7
#define SEA_mmDP4_DP_MSE_SAT_UPDATE 0x48e7
#define SEA_mmDP5_DP_MSE_SAT_UPDATE 0x4be7
#define SEA_mmDP6_DP_MSE_SAT_UPDATE 0x4ee7
#define SEA_mmDP_MSE_LINK_TIMING 0x1ce8
#define SEA_mmDP0_DP_MSE_LINK_TIMING 0x1ce8
#define SEA_mmDP1_DP_MSE_LINK_TIMING 0x1fe8
#define SEA_mmDP2_DP_MSE_LINK_TIMING 0x42e8
#define SEA_mmDP3_DP_MSE_LINK_TIMING 0x45e8
#define SEA_mmDP4_DP_MSE_LINK_TIMING 0x48e8
#define SEA_mmDP5_DP_MSE_LINK_TIMING 0x4be8
#define SEA_mmDP6_DP_MSE_LINK_TIMING 0x4ee8
#define SEA_mmDP_MSE_MISC_CNTL 0x1cdb
#define SEA_mmDP0_DP_MSE_MISC_CNTL 0x1cdb
#define SEA_mmDP1_DP_MSE_MISC_CNTL 0x1fdb
#define SEA_mmDP2_DP_MSE_MISC_CNTL 0x42db
#define SEA_mmDP3_DP_MSE_MISC_CNTL 0x45db
#define SEA_mmDP4_DP_MSE_MISC_CNTL 0x48db
#define SEA_mmDP5_DP_MSE_MISC_CNTL 0x4bdb
#define SEA_mmDP6_DP_MSE_MISC_CNTL 0x4edb
#define SEA_mmDP_TEST_DEBUG_INDEX 0x1cfc
#define SEA_mmDP0_DP_TEST_DEBUG_INDEX 0x1cfc
#define SEA_mmDP1_DP_TEST_DEBUG_INDEX 0x1ffc
#define SEA_mmDP2_DP_TEST_DEBUG_INDEX 0x42fc
#define SEA_mmDP3_DP_TEST_DEBUG_INDEX 0x45fc
#define SEA_mmDP4_DP_TEST_DEBUG_INDEX 0x48fc
#define SEA_mmDP5_DP_TEST_DEBUG_INDEX 0x4bfc
#define SEA_mmDP6_DP_TEST_DEBUG_INDEX 0x4efc
#define SEA_mmDP_TEST_DEBUG_DATA 0x1cfd
#define SEA_mmDP0_DP_TEST_DEBUG_DATA 0x1cfd
#define SEA_mmDP1_DP_TEST_DEBUG_DATA 0x1ffd
#define SEA_mmDP2_DP_TEST_DEBUG_DATA 0x42fd
#define SEA_mmDP3_DP_TEST_DEBUG_DATA 0x45fd
#define SEA_mmDP4_DP_TEST_DEBUG_DATA 0x48fd
#define SEA_mmDP5_DP_TEST_DEBUG_DATA 0x4bfd
#define SEA_mmDP6_DP_TEST_DEBUG_DATA 0x4efd
#define SEA_mmAUX_CONTROL 0x1880
#define SEA_mmDP_AUX0_AUX_CONTROL 0x1880
#define SEA_mmDP_AUX1_AUX_CONTROL 0x1894
#define SEA_mmDP_AUX2_AUX_CONTROL 0x18a8
#define SEA_mmDP_AUX3_AUX_CONTROL 0x18c0
#define SEA_mmDP_AUX4_AUX_CONTROL 0x18d4
#define SEA_mmDP_AUX5_AUX_CONTROL 0x18e8
#define SEA_mmAUX_SW_CONTROL 0x1881
#define SEA_mmDP_AUX0_AUX_SW_CONTROL 0x1881
#define SEA_mmDP_AUX1_AUX_SW_CONTROL 0x1895
#define SEA_mmDP_AUX2_AUX_SW_CONTROL 0x18a9
#define SEA_mmDP_AUX3_AUX_SW_CONTROL 0x18c1
#define SEA_mmDP_AUX4_AUX_SW_CONTROL 0x18d5
#define SEA_mmDP_AUX5_AUX_SW_CONTROL 0x18e9
#define SEA_mmAUX_ARB_CONTROL 0x1882
#define SEA_mmDP_AUX0_AUX_ARB_CONTROL 0x1882
#define SEA_mmDP_AUX1_AUX_ARB_CONTROL 0x1896
#define SEA_mmDP_AUX2_AUX_ARB_CONTROL 0x18aa
#define SEA_mmDP_AUX3_AUX_ARB_CONTROL 0x18c2
#define SEA_mmDP_AUX4_AUX_ARB_CONTROL 0x18d6
#define SEA_mmDP_AUX5_AUX_ARB_CONTROL 0x18ea
#define SEA_mmAUX_INTERRUPT_CONTROL 0x1883
#define SEA_mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1883
#define SEA_mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1897
#define SEA_mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x18ab
#define SEA_mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x18c3
#define SEA_mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x18d7
#define SEA_mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x18eb
#define SEA_mmAUX_SW_STATUS 0x1884
#define SEA_mmDP_AUX0_AUX_SW_STATUS 0x1884
#define SEA_mmDP_AUX1_AUX_SW_STATUS 0x1898
#define SEA_mmDP_AUX2_AUX_SW_STATUS 0x18ac
#define SEA_mmDP_AUX3_AUX_SW_STATUS 0x18c4
#define SEA_mmDP_AUX4_AUX_SW_STATUS 0x18d8
#define SEA_mmDP_AUX5_AUX_SW_STATUS 0x18ec
#define SEA_mmAUX_LS_STATUS 0x1885
#define SEA_mmDP_AUX0_AUX_LS_STATUS 0x1885
#define SEA_mmDP_AUX1_AUX_LS_STATUS 0x1899
#define SEA_mmDP_AUX2_AUX_LS_STATUS 0x18ad
#define SEA_mmDP_AUX3_AUX_LS_STATUS 0x18c5
#define SEA_mmDP_AUX4_AUX_LS_STATUS 0x18d9
#define SEA_mmDP_AUX5_AUX_LS_STATUS 0x18ed
#define SEA_mmAUX_SW_DATA 0x1886
#define SEA_mmDP_AUX0_AUX_SW_DATA 0x1886
#define SEA_mmDP_AUX1_AUX_SW_DATA 0x189a
#define SEA_mmDP_AUX2_AUX_SW_DATA 0x18ae
#define SEA_mmDP_AUX3_AUX_SW_DATA 0x18c6
#define SEA_mmDP_AUX4_AUX_SW_DATA 0x18da
#define SEA_mmDP_AUX5_AUX_SW_DATA 0x18ee
#define SEA_mmAUX_LS_DATA 0x1887
#define SEA_mmDP_AUX0_AUX_LS_DATA 0x1887
#define SEA_mmDP_AUX1_AUX_LS_DATA 0x189b
#define SEA_mmDP_AUX2_AUX_LS_DATA 0x18af
#define SEA_mmDP_AUX3_AUX_LS_DATA 0x18c7
#define SEA_mmDP_AUX4_AUX_LS_DATA 0x18db
#define SEA_mmDP_AUX5_AUX_LS_DATA 0x18ef
#define SEA_mmAUX_DPHY_TX_REF_CONTROL 0x1888
#define SEA_mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1888
#define SEA_mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x189c
#define SEA_mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x18b0
#define SEA_mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x18c8
#define SEA_mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x18dc
#define SEA_mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x18f0
#define SEA_mmAUX_DPHY_TX_CONTROL 0x1889
#define SEA_mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1889
#define SEA_mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x189d
#define SEA_mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x18b1
#define SEA_mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x18c9
#define SEA_mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x18dd
#define SEA_mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x18f1
#define SEA_mmAUX_DPHY_RX_CONTROL0 0x188a
#define SEA_mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x188a
#define SEA_mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x189e
#define SEA_mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x18b2
#define SEA_mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x18ca
#define SEA_mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x18de
#define SEA_mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x18f2
#define SEA_mmAUX_DPHY_RX_CONTROL1 0x188b
#define SEA_mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x188b
#define SEA_mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x189f
#define SEA_mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x18b3
#define SEA_mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x18cb
#define SEA_mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x18df
#define SEA_mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x18f3
#define SEA_mmAUX_DPHY_TX_STATUS 0x188c
#define SEA_mmDP_AUX0_AUX_DPHY_TX_STATUS 0x188c
#define SEA_mmDP_AUX1_AUX_DPHY_TX_STATUS 0x18a0
#define SEA_mmDP_AUX2_AUX_DPHY_TX_STATUS 0x18b4
#define SEA_mmDP_AUX3_AUX_DPHY_TX_STATUS 0x18cc
#define SEA_mmDP_AUX4_AUX_DPHY_TX_STATUS 0x18e0
#define SEA_mmDP_AUX5_AUX_DPHY_TX_STATUS 0x18f4
#define SEA_mmAUX_DPHY_RX_STATUS 0x188d
#define SEA_mmDP_AUX0_AUX_DPHY_RX_STATUS 0x188d
#define SEA_mmDP_AUX1_AUX_DPHY_RX_STATUS 0x18a1
#define SEA_mmDP_AUX2_AUX_DPHY_RX_STATUS 0x18b5
#define SEA_mmDP_AUX3_AUX_DPHY_RX_STATUS 0x18cd
#define SEA_mmDP_AUX4_AUX_DPHY_RX_STATUS 0x18e1
#define SEA_mmDP_AUX5_AUX_DPHY_RX_STATUS 0x18f5
#define SEA_mmAUX_GTC_SYNC_CONTROL 0x188e
#define SEA_mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x188e
#define SEA_mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x18a2
#define SEA_mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x18b6
#define SEA_mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x18ce
#define SEA_mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x18e2
#define SEA_mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x18f6
#define SEA_mmAUX_GTC_SYNC_ERROR_CONTROL 0x188f
#define SEA_mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x188f
#define SEA_mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x18a3
#define SEA_mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x18b7
#define SEA_mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x18cf
#define SEA_mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x18e3
#define SEA_mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x18f7
#define SEA_mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x1890
#define SEA_mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1890
#define SEA_mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18a4
#define SEA_mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18b8
#define SEA_mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18d0
#define SEA_mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18e4
#define SEA_mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18f8
#define SEA_mmAUX_GTC_SYNC_STATUS 0x1891
#define SEA_mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1891
#define SEA_mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x18a5
#define SEA_mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x18b9
#define SEA_mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x18d1
#define SEA_mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x18e5
#define SEA_mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x18f9
#define SEA_mmAUX_GTC_SYNC_DATA 0x1892
#define SEA_mmDP_AUX0_AUX_GTC_SYNC_DATA 0x1892
#define SEA_mmDP_AUX1_AUX_GTC_SYNC_DATA 0x18a6
#define SEA_mmDP_AUX2_AUX_GTC_SYNC_DATA 0x18ba
#define SEA_mmDP_AUX3_AUX_GTC_SYNC_DATA 0x18d2
#define SEA_mmDP_AUX4_AUX_GTC_SYNC_DATA 0x18e6
#define SEA_mmDP_AUX5_AUX_GTC_SYNC_DATA 0x18fa
#define SEA_mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x1893
#define SEA_mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x1893
#define SEA_mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18a7
#define SEA_mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18bb
#define SEA_mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18d3
#define SEA_mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18e7
#define SEA_mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18fb
#define SEA_mmDVO_ENABLE 0x1858
#define SEA_mmDVO_SOURCE_SELECT 0x1859
#define SEA_mmDVO_OUTPUT 0x185a
#define SEA_mmDVO_CONTROL 0x185b
#define SEA_mmDVO_CRC_EN 0x185c
#define SEA_mmDVO_CRC2_SIG_MASK 0x185d
#define SEA_mmDVO_CRC2_SIG_RESULT 0x185e
#define SEA_mmDVO_FIFO_ERROR_STATUS 0x185f
#define SEA_mmFBC_CNTL 0x16d0
#define SEA_mmFBC_IDLE_MASK 0x16d1
#define SEA_mmFBC_IDLE_FORCE_CLEAR_MASK 0x16d2
#define SEA_mmFBC_START_STOP_DELAY 0x16d3
#define SEA_mmFBC_COMP_CNTL 0x16d4
#define SEA_mmFBC_COMP_MODE 0x16d5
#define SEA_mmFBC_DEBUG0 0x16d6
#define SEA_mmFBC_DEBUG1 0x16d7
#define SEA_mmFBC_DEBUG2 0x16d8
#define SEA_mmFBC_IND_LUT0 0x16d9
#define SEA_mmFBC_IND_LUT1 0x16da
#define SEA_mmFBC_IND_LUT2 0x16db
#define SEA_mmFBC_IND_LUT3 0x16dc
#define SEA_mmFBC_IND_LUT4 0x16dd
#define SEA_mmFBC_IND_LUT5 0x16de
#define SEA_mmFBC_IND_LUT6 0x16df
#define SEA_mmFBC_IND_LUT7 0x16e0
#define SEA_mmFBC_IND_LUT8 0x16e1
#define SEA_mmFBC_IND_LUT9 0x16e2
#define SEA_mmFBC_IND_LUT10 0x16e3
#define SEA_mmFBC_IND_LUT11 0x16e4
#define SEA_mmFBC_IND_LUT12 0x16e5
#define SEA_mmFBC_IND_LUT13 0x16e6
#define SEA_mmFBC_IND_LUT14 0x16e7
#define SEA_mmFBC_IND_LUT15 0x16e8
#define SEA_mmFBC_CSM_REGION_OFFSET_01 0x16e9
#define SEA_mmFBC_CSM_REGION_OFFSET_23 0x16ea
#define SEA_mmFBC_CLIENT_REGION_MASK 0x16eb
#define SEA_mmFBC_DEBUG_COMP 0x16ec
#define SEA_mmFBC_DEBUG_CSR 0x16ed
#define SEA_mmFBC_DEBUG_CSR_RDATA 0x16ee
#define SEA_mmFBC_DEBUG_CSR_WDATA 0x16ef
#define SEA_mmFBC_DEBUG_CSR_RDATA_HI 0x16f6
#define SEA_mmFBC_DEBUG_CSR_WDATA_HI 0x16f7
#define SEA_mmFBC_MISC 0x16f0
#define SEA_mmFBC_STATUS 0x16f1
#define SEA_mmFBC_TEST_DEBUG_INDEX 0x16f4
#define SEA_mmFBC_TEST_DEBUG_DATA 0x16f5
#define SEA_mmFMT_CLAMP_COMPONENT_R 0x1be8
#define SEA_mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8
#define SEA_mmFMT1_FMT_CLAMP_COMPONENT_R 0x1ee8
#define SEA_mmFMT2_FMT_CLAMP_COMPONENT_R 0x41e8
#define SEA_mmFMT3_FMT_CLAMP_COMPONENT_R 0x44e8
#define SEA_mmFMT4_FMT_CLAMP_COMPONENT_R 0x47e8
#define SEA_mmFMT5_FMT_CLAMP_COMPONENT_R 0x4ae8
#define SEA_mmFMT_CLAMP_COMPONENT_G 0x1be9
#define SEA_mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9
#define SEA_mmFMT1_FMT_CLAMP_COMPONENT_G 0x1ee9
#define SEA_mmFMT2_FMT_CLAMP_COMPONENT_G 0x41e9
#define SEA_mmFMT3_FMT_CLAMP_COMPONENT_G 0x44e9
#define SEA_mmFMT4_FMT_CLAMP_COMPONENT_G 0x47e9
#define SEA_mmFMT5_FMT_CLAMP_COMPONENT_G 0x4ae9
#define SEA_mmFMT_CLAMP_COMPONENT_B 0x1bea
#define SEA_mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea
#define SEA_mmFMT1_FMT_CLAMP_COMPONENT_B 0x1eea
#define SEA_mmFMT2_FMT_CLAMP_COMPONENT_B 0x41ea
#define SEA_mmFMT3_FMT_CLAMP_COMPONENT_B 0x44ea
#define SEA_mmFMT4_FMT_CLAMP_COMPONENT_B 0x47ea
#define SEA_mmFMT5_FMT_CLAMP_COMPONENT_B 0x4aea
#define SEA_mmFMT_DYNAMIC_EXP_CNTL 0x1bed
#define SEA_mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed
#define SEA_mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1eed
#define SEA_mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x41ed
#define SEA_mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x44ed
#define SEA_mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x47ed
#define SEA_mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x4aed
#define SEA_mmFMT_CONTROL 0x1bee
#define SEA_mmFMT0_FMT_CONTROL 0x1bee
#define SEA_mmFMT1_FMT_CONTROL 0x1eee
#define SEA_mmFMT2_FMT_CONTROL 0x41ee
#define SEA_mmFMT3_FMT_CONTROL 0x44ee
#define SEA_mmFMT4_FMT_CONTROL 0x47ee
#define SEA_mmFMT5_FMT_CONTROL 0x4aee
#define SEA_mmFMT_FORCE_OUTPUT_CNTL 0x1bef
#define SEA_mmFMT0_FMT_FORCE_OUTPUT_CNTL 0x1bef
#define SEA_mmFMT1_FMT_FORCE_OUTPUT_CNTL 0x1eef
#define SEA_mmFMT2_FMT_FORCE_OUTPUT_CNTL 0x41ef
#define SEA_mmFMT3_FMT_FORCE_OUTPUT_CNTL 0x44ef
#define SEA_mmFMT4_FMT_FORCE_OUTPUT_CNTL 0x47ef
#define SEA_mmFMT5_FMT_FORCE_OUTPUT_CNTL 0x4aef
#define SEA_mmFMT_FORCE_DATA_0_1 0x1bf0
#define SEA_mmFMT0_FMT_FORCE_DATA_0_1 0x1bf0
#define SEA_mmFMT1_FMT_FORCE_DATA_0_1 0x1ef0
#define SEA_mmFMT2_FMT_FORCE_DATA_0_1 0x41f0
#define SEA_mmFMT3_FMT_FORCE_DATA_0_1 0x44f0
#define SEA_mmFMT4_FMT_FORCE_DATA_0_1 0x47f0
#define SEA_mmFMT5_FMT_FORCE_DATA_0_1 0x4af0
#define SEA_mmFMT_FORCE_DATA_2_3 0x1bf1
#define SEA_mmFMT0_FMT_FORCE_DATA_2_3 0x1bf1
#define SEA_mmFMT1_FMT_FORCE_DATA_2_3 0x1ef1
#define SEA_mmFMT2_FMT_FORCE_DATA_2_3 0x41f1
#define SEA_mmFMT3_FMT_FORCE_DATA_2_3 0x44f1
#define SEA_mmFMT4_FMT_FORCE_DATA_2_3 0x47f1
#define SEA_mmFMT5_FMT_FORCE_DATA_2_3 0x4af1
#define SEA_mmFMT_BIT_DEPTH_CONTROL 0x1bf2
#define SEA_mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2
#define SEA_mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1ef2
#define SEA_mmFMT2_FMT_BIT_DEPTH_CONTROL 0x41f2
#define SEA_mmFMT3_FMT_BIT_DEPTH_CONTROL 0x44f2
#define SEA_mmFMT4_FMT_BIT_DEPTH_CONTROL 0x47f2
#define SEA_mmFMT5_FMT_BIT_DEPTH_CONTROL 0x4af2
#define SEA_mmFMT_DITHER_RAND_R_SEED 0x1bf3
#define SEA_mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3
#define SEA_mmFMT1_FMT_DITHER_RAND_R_SEED 0x1ef3
#define SEA_mmFMT2_FMT_DITHER_RAND_R_SEED 0x41f3
#define SEA_mmFMT3_FMT_DITHER_RAND_R_SEED 0x44f3
#define SEA_mmFMT4_FMT_DITHER_RAND_R_SEED 0x47f3
#define SEA_mmFMT5_FMT_DITHER_RAND_R_SEED 0x4af3
#define SEA_mmFMT_DITHER_RAND_G_SEED 0x1bf4
#define SEA_mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4
#define SEA_mmFMT1_FMT_DITHER_RAND_G_SEED 0x1ef4
#define SEA_mmFMT2_FMT_DITHER_RAND_G_SEED 0x41f4
#define SEA_mmFMT3_FMT_DITHER_RAND_G_SEED 0x44f4
#define SEA_mmFMT4_FMT_DITHER_RAND_G_SEED 0x47f4
#define SEA_mmFMT5_FMT_DITHER_RAND_G_SEED 0x4af4
#define SEA_mmFMT_DITHER_RAND_B_SEED 0x1bf5
#define SEA_mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5
#define SEA_mmFMT1_FMT_DITHER_RAND_B_SEED 0x1ef5
#define SEA_mmFMT2_FMT_DITHER_RAND_B_SEED 0x41f5
#define SEA_mmFMT3_FMT_DITHER_RAND_B_SEED 0x44f5
#define SEA_mmFMT4_FMT_DITHER_RAND_B_SEED 0x47f5
#define SEA_mmFMT5_FMT_DITHER_RAND_B_SEED 0x4af5
#define SEA_mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6
#define SEA_mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6
#define SEA_mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ef6
#define SEA_mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6
#define SEA_mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x44f6
#define SEA_mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x47f6
#define SEA_mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x4af6
#define SEA_mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7
#define SEA_mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7
#define SEA_mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ef7
#define SEA_mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7
#define SEA_mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x44f7
#define SEA_mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x47f7
#define SEA_mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x4af7
#define SEA_mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8
#define SEA_mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8
#define SEA_mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ef8
#define SEA_mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8
#define SEA_mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x44f8
#define SEA_mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x47f8
#define SEA_mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x4af8
#define SEA_mmFMT_CLAMP_CNTL 0x1bf9
#define SEA_mmFMT0_FMT_CLAMP_CNTL 0x1bf9
#define SEA_mmFMT1_FMT_CLAMP_CNTL 0x1ef9
#define SEA_mmFMT2_FMT_CLAMP_CNTL 0x41f9
#define SEA_mmFMT3_FMT_CLAMP_CNTL 0x44f9
#define SEA_mmFMT4_FMT_CLAMP_CNTL 0x47f9
#define SEA_mmFMT5_FMT_CLAMP_CNTL 0x4af9
#define SEA_mmFMT_CRC_CNTL 0x1bfa
#define SEA_mmFMT0_FMT_CRC_CNTL 0x1bfa
#define SEA_mmFMT1_FMT_CRC_CNTL 0x1efa
#define SEA_mmFMT2_FMT_CRC_CNTL 0x41fa
#define SEA_mmFMT3_FMT_CRC_CNTL 0x44fa
#define SEA_mmFMT4_FMT_CRC_CNTL 0x47fa
#define SEA_mmFMT5_FMT_CRC_CNTL 0x4afa
#define SEA_mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb
#define SEA_mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb
#define SEA_mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1efb
#define SEA_mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb
#define SEA_mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x44fb
#define SEA_mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x47fb
#define SEA_mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x4afb
#define SEA_mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc
#define SEA_mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc
#define SEA_mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1efc
#define SEA_mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc
#define SEA_mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x44fc
#define SEA_mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x47fc
#define SEA_mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x4afc
#define SEA_mmFMT_CRC_SIG_RED_GREEN 0x1bfd
#define SEA_mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd
#define SEA_mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1efd
#define SEA_mmFMT2_FMT_CRC_SIG_RED_GREEN 0x41fd
#define SEA_mmFMT3_FMT_CRC_SIG_RED_GREEN 0x44fd
#define SEA_mmFMT4_FMT_CRC_SIG_RED_GREEN 0x47fd
#define SEA_mmFMT5_FMT_CRC_SIG_RED_GREEN 0x4afd
#define SEA_mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe
#define SEA_mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe
#define SEA_mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1efe
#define SEA_mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x41fe
#define SEA_mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x44fe
#define SEA_mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x47fe
#define SEA_mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x4afe
#define SEA_mmFMT_DEBUG_CNTL 0x1bff
#define SEA_mmFMT0_FMT_DEBUG_CNTL 0x1bff
#define SEA_mmFMT1_FMT_DEBUG_CNTL 0x1eff
#define SEA_mmFMT2_FMT_DEBUG_CNTL 0x41ff
#define SEA_mmFMT3_FMT_DEBUG_CNTL 0x44ff
#define SEA_mmFMT4_FMT_DEBUG_CNTL 0x47ff
#define SEA_mmFMT5_FMT_DEBUG_CNTL 0x4aff
#define SEA_mmFMT_TEST_DEBUG_INDEX 0x1beb
#define SEA_mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb
#define SEA_mmFMT1_FMT_TEST_DEBUG_INDEX 0x1eeb
#define SEA_mmFMT2_FMT_TEST_DEBUG_INDEX 0x41eb
#define SEA_mmFMT3_FMT_TEST_DEBUG_INDEX 0x44eb
#define SEA_mmFMT4_FMT_TEST_DEBUG_INDEX 0x47eb
#define SEA_mmFMT5_FMT_TEST_DEBUG_INDEX 0x4aeb
#define SEA_mmFMT_TEST_DEBUG_DATA 0x1bec
#define SEA_mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec
#define SEA_mmFMT1_FMT_TEST_DEBUG_DATA 0x1eec
#define SEA_mmFMT2_FMT_TEST_DEBUG_DATA 0x41ec
#define SEA_mmFMT3_FMT_TEST_DEBUG_DATA 0x44ec
#define SEA_mmFMT4_FMT_TEST_DEBUG_DATA 0x47ec
#define SEA_mmFMT5_FMT_TEST_DEBUG_DATA 0x4aec
#define SEA_ixFMT_DEBUG0 0x1
#define SEA_ixFMT_DEBUG1 0x2
#define SEA_ixFMT_DEBUG2 0x3
#define SEA_ixFMT_DEBUG_ID 0x0
#define SEA_mmLB_DATA_FORMAT 0x1ac0
#define SEA_mmLB0_LB_DATA_FORMAT 0x1ac0
#define SEA_mmLB1_LB_DATA_FORMAT 0x1dc0
#define SEA_mmLB2_LB_DATA_FORMAT 0x40c0
#define SEA_mmLB3_LB_DATA_FORMAT 0x43c0
#define SEA_mmLB4_LB_DATA_FORMAT 0x46c0
#define SEA_mmLB5_LB_DATA_FORMAT 0x49c0
#define SEA_mmLB_MEMORY_CTRL 0x1ac1
#define SEA_mmLB0_LB_MEMORY_CTRL 0x1ac1
#define SEA_mmLB1_LB_MEMORY_CTRL 0x1dc1
#define SEA_mmLB2_LB_MEMORY_CTRL 0x40c1
#define SEA_mmLB3_LB_MEMORY_CTRL 0x43c1
#define SEA_mmLB4_LB_MEMORY_CTRL 0x46c1
#define SEA_mmLB5_LB_MEMORY_CTRL 0x49c1
#define SEA_mmLB_MEMORY_SIZE_STATUS 0x1ac2
#define SEA_mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2
#define SEA_mmLB1_LB_MEMORY_SIZE_STATUS 0x1dc2
#define SEA_mmLB2_LB_MEMORY_SIZE_STATUS 0x40c2
#define SEA_mmLB3_LB_MEMORY_SIZE_STATUS 0x43c2
#define SEA_mmLB4_LB_MEMORY_SIZE_STATUS 0x46c2
#define SEA_mmLB5_LB_MEMORY_SIZE_STATUS 0x49c2
#define SEA_mmLB_DESKTOP_HEIGHT 0x1ac3
#define SEA_mmLB0_LB_DESKTOP_HEIGHT 0x1ac3
#define SEA_mmLB1_LB_DESKTOP_HEIGHT 0x1dc3
#define SEA_mmLB2_LB_DESKTOP_HEIGHT 0x40c3
#define SEA_mmLB3_LB_DESKTOP_HEIGHT 0x43c3
#define SEA_mmLB4_LB_DESKTOP_HEIGHT 0x46c3
#define SEA_mmLB5_LB_DESKTOP_HEIGHT 0x49c3
#define SEA_mmLB_VLINE_START_END 0x1ac4
#define SEA_mmLB0_LB_VLINE_START_END 0x1ac4
#define SEA_mmLB1_LB_VLINE_START_END 0x1dc4
#define SEA_mmLB2_LB_VLINE_START_END 0x40c4
#define SEA_mmLB3_LB_VLINE_START_END 0x43c4
#define SEA_mmLB4_LB_VLINE_START_END 0x46c4
#define SEA_mmLB5_LB_VLINE_START_END 0x49c4
#define SEA_mmLB_VLINE2_START_END 0x1ac5
#define SEA_mmLB0_LB_VLINE2_START_END 0x1ac5
#define SEA_mmLB1_LB_VLINE2_START_END 0x1dc5
#define SEA_mmLB2_LB_VLINE2_START_END 0x40c5
#define SEA_mmLB3_LB_VLINE2_START_END 0x43c5
#define SEA_mmLB4_LB_VLINE2_START_END 0x46c5
#define SEA_mmLB5_LB_VLINE2_START_END 0x49c5
#define SEA_mmLB_V_COUNTER 0x1ac6
#define SEA_mmLB0_LB_V_COUNTER 0x1ac6
#define SEA_mmLB1_LB_V_COUNTER 0x1dc6
#define SEA_mmLB2_LB_V_COUNTER 0x40c6
#define SEA_mmLB3_LB_V_COUNTER 0x43c6
#define SEA_mmLB4_LB_V_COUNTER 0x46c6
#define SEA_mmLB5_LB_V_COUNTER 0x49c6
#define SEA_mmLB_SNAPSHOT_V_COUNTER 0x1ac7
#define SEA_mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7
#define SEA_mmLB1_LB_SNAPSHOT_V_COUNTER 0x1dc7
#define SEA_mmLB2_LB_SNAPSHOT_V_COUNTER 0x40c7
#define SEA_mmLB3_LB_SNAPSHOT_V_COUNTER 0x43c7
#define SEA_mmLB4_LB_SNAPSHOT_V_COUNTER 0x46c7
#define SEA_mmLB5_LB_SNAPSHOT_V_COUNTER 0x49c7
#define SEA_mmLB_INTERRUPT_MASK 0x1ac8
#define SEA_mmLB0_LB_INTERRUPT_MASK 0x1ac8
#define SEA_mmLB1_LB_INTERRUPT_MASK 0x1dc8
#define SEA_mmLB2_LB_INTERRUPT_MASK 0x40c8
#define SEA_mmLB3_LB_INTERRUPT_MASK 0x43c8
#define SEA_mmLB4_LB_INTERRUPT_MASK 0x46c8
#define SEA_mmLB5_LB_INTERRUPT_MASK 0x49c8
#define SEA_mmLB_VLINE_STATUS 0x1ac9
#define SEA_mmLB0_LB_VLINE_STATUS 0x1ac9
#define SEA_mmLB1_LB_VLINE_STATUS 0x1dc9
#define SEA_mmLB2_LB_VLINE_STATUS 0x40c9
#define SEA_mmLB3_LB_VLINE_STATUS 0x43c9
#define SEA_mmLB4_LB_VLINE_STATUS 0x46c9
#define SEA_mmLB5_LB_VLINE_STATUS 0x49c9
#define SEA_mmLB_VLINE2_STATUS 0x1aca
#define SEA_mmLB0_LB_VLINE2_STATUS 0x1aca
#define SEA_mmLB1_LB_VLINE2_STATUS 0x1dca
#define SEA_mmLB2_LB_VLINE2_STATUS 0x40ca
#define SEA_mmLB3_LB_VLINE2_STATUS 0x43ca
#define SEA_mmLB4_LB_VLINE2_STATUS 0x46ca
#define SEA_mmLB5_LB_VLINE2_STATUS 0x49ca
#define SEA_mmLB_VBLANK_STATUS 0x1acb
#define SEA_mmLB0_LB_VBLANK_STATUS 0x1acb
#define SEA_mmLB1_LB_VBLANK_STATUS 0x1dcb
#define SEA_mmLB2_LB_VBLANK_STATUS 0x40cb
#define SEA_mmLB3_LB_VBLANK_STATUS 0x43cb
#define SEA_mmLB4_LB_VBLANK_STATUS 0x46cb
#define SEA_mmLB5_LB_VBLANK_STATUS 0x49cb
#define SEA_mmLB_SYNC_RESET_SEL 0x1acc
#define SEA_mmLB0_LB_SYNC_RESET_SEL 0x1acc
#define SEA_mmLB1_LB_SYNC_RESET_SEL 0x1dcc
#define SEA_mmLB2_LB_SYNC_RESET_SEL 0x40cc
#define SEA_mmLB3_LB_SYNC_RESET_SEL 0x43cc
#define SEA_mmLB4_LB_SYNC_RESET_SEL 0x46cc
#define SEA_mmLB5_LB_SYNC_RESET_SEL 0x49cc
#define SEA_mmLB_BLACK_KEYER_R_CR 0x1acd
#define SEA_mmLB0_LB_BLACK_KEYER_R_CR 0x1acd
#define SEA_mmLB1_LB_BLACK_KEYER_R_CR 0x1dcd
#define SEA_mmLB2_LB_BLACK_KEYER_R_CR 0x40cd
#define SEA_mmLB3_LB_BLACK_KEYER_R_CR 0x43cd
#define SEA_mmLB4_LB_BLACK_KEYER_R_CR 0x46cd
#define SEA_mmLB5_LB_BLACK_KEYER_R_CR 0x49cd
#define SEA_mmLB_BLACK_KEYER_G_Y 0x1ace
#define SEA_mmLB0_LB_BLACK_KEYER_G_Y 0x1ace
#define SEA_mmLB1_LB_BLACK_KEYER_G_Y 0x1dce
#define SEA_mmLB2_LB_BLACK_KEYER_G_Y 0x40ce
#define SEA_mmLB3_LB_BLACK_KEYER_G_Y 0x43ce
#define SEA_mmLB4_LB_BLACK_KEYER_G_Y 0x46ce
#define SEA_mmLB5_LB_BLACK_KEYER_G_Y 0x49ce
#define SEA_mmLB_BLACK_KEYER_B_CB 0x1acf
#define SEA_mmLB0_LB_BLACK_KEYER_B_CB 0x1acf
#define SEA_mmLB1_LB_BLACK_KEYER_B_CB 0x1dcf
#define SEA_mmLB2_LB_BLACK_KEYER_B_CB 0x40cf
#define SEA_mmLB3_LB_BLACK_KEYER_B_CB 0x43cf
#define SEA_mmLB4_LB_BLACK_KEYER_B_CB 0x46cf
#define SEA_mmLB5_LB_BLACK_KEYER_B_CB 0x49cf
#define SEA_mmLB_KEYER_COLOR_CTRL 0x1ad0
#define SEA_mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0
#define SEA_mmLB1_LB_KEYER_COLOR_CTRL 0x1dd0
#define SEA_mmLB2_LB_KEYER_COLOR_CTRL 0x40d0
#define SEA_mmLB3_LB_KEYER_COLOR_CTRL 0x43d0
#define SEA_mmLB4_LB_KEYER_COLOR_CTRL 0x46d0
#define SEA_mmLB5_LB_KEYER_COLOR_CTRL 0x49d0
#define SEA_mmLB_KEYER_COLOR_R_CR 0x1ad1
#define SEA_mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1
#define SEA_mmLB1_LB_KEYER_COLOR_R_CR 0x1dd1
#define SEA_mmLB2_LB_KEYER_COLOR_R_CR 0x40d1
#define SEA_mmLB3_LB_KEYER_COLOR_R_CR 0x43d1
#define SEA_mmLB4_LB_KEYER_COLOR_R_CR 0x46d1
#define SEA_mmLB5_LB_KEYER_COLOR_R_CR 0x49d1
#define SEA_mmLB_KEYER_COLOR_G_Y 0x1ad2
#define SEA_mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2
#define SEA_mmLB1_LB_KEYER_COLOR_G_Y 0x1dd2
#define SEA_mmLB2_LB_KEYER_COLOR_G_Y 0x40d2
#define SEA_mmLB3_LB_KEYER_COLOR_G_Y 0x43d2
#define SEA_mmLB4_LB_KEYER_COLOR_G_Y 0x46d2
#define SEA_mmLB5_LB_KEYER_COLOR_G_Y 0x49d2
#define SEA_mmLB_KEYER_COLOR_B_CB 0x1ad3
#define SEA_mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3
#define SEA_mmLB1_LB_KEYER_COLOR_B_CB 0x1dd3
#define SEA_mmLB2_LB_KEYER_COLOR_B_CB 0x40d3
#define SEA_mmLB3_LB_KEYER_COLOR_B_CB 0x43d3
#define SEA_mmLB4_LB_KEYER_COLOR_B_CB 0x46d3
#define SEA_mmLB5_LB_KEYER_COLOR_B_CB 0x49d3
#define SEA_mmLB_KEYER_COLOR_REP_R_CR 0x1ad4
#define SEA_mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4
#define SEA_mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1dd4
#define SEA_mmLB2_LB_KEYER_COLOR_REP_R_CR 0x40d4
#define SEA_mmLB3_LB_KEYER_COLOR_REP_R_CR 0x43d4
#define SEA_mmLB4_LB_KEYER_COLOR_REP_R_CR 0x46d4
#define SEA_mmLB5_LB_KEYER_COLOR_REP_R_CR 0x49d4
#define SEA_mmLB_KEYER_COLOR_REP_G_Y 0x1ad5
#define SEA_mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5
#define SEA_mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1dd5
#define SEA_mmLB2_LB_KEYER_COLOR_REP_G_Y 0x40d5
#define SEA_mmLB3_LB_KEYER_COLOR_REP_G_Y 0x43d5
#define SEA_mmLB4_LB_KEYER_COLOR_REP_G_Y 0x46d5
#define SEA_mmLB5_LB_KEYER_COLOR_REP_G_Y 0x49d5
#define SEA_mmLB_KEYER_COLOR_REP_B_CB 0x1ad6
#define SEA_mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6
#define SEA_mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1dd6
#define SEA_mmLB2_LB_KEYER_COLOR_REP_B_CB 0x40d6
#define SEA_mmLB3_LB_KEYER_COLOR_REP_B_CB 0x43d6
#define SEA_mmLB4_LB_KEYER_COLOR_REP_B_CB 0x46d6
#define SEA_mmLB5_LB_KEYER_COLOR_REP_B_CB 0x49d6
#define SEA_mmLB_BUFFER_LEVEL_STATUS 0x1ad7
#define SEA_mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7
#define SEA_mmLB1_LB_BUFFER_LEVEL_STATUS 0x1dd7
#define SEA_mmLB2_LB_BUFFER_LEVEL_STATUS 0x40d7
#define SEA_mmLB3_LB_BUFFER_LEVEL_STATUS 0x43d7
#define SEA_mmLB4_LB_BUFFER_LEVEL_STATUS 0x46d7
#define SEA_mmLB5_LB_BUFFER_LEVEL_STATUS 0x49d7
#define SEA_mmLB_BUFFER_URGENCY_CTRL 0x1ad8
#define SEA_mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8
#define SEA_mmLB1_LB_BUFFER_URGENCY_CTRL 0x1dd8
#define SEA_mmLB2_LB_BUFFER_URGENCY_CTRL 0x40d8
#define SEA_mmLB3_LB_BUFFER_URGENCY_CTRL 0x43d8
#define SEA_mmLB4_LB_BUFFER_URGENCY_CTRL 0x46d8
#define SEA_mmLB5_LB_BUFFER_URGENCY_CTRL 0x49d8
#define SEA_mmLB_BUFFER_URGENCY_STATUS 0x1ad9
#define SEA_mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9
#define SEA_mmLB1_LB_BUFFER_URGENCY_STATUS 0x1dd9
#define SEA_mmLB2_LB_BUFFER_URGENCY_STATUS 0x40d9
#define SEA_mmLB3_LB_BUFFER_URGENCY_STATUS 0x43d9
#define SEA_mmLB4_LB_BUFFER_URGENCY_STATUS 0x46d9
#define SEA_mmLB5_LB_BUFFER_URGENCY_STATUS 0x49d9
#define SEA_mmLB_BUFFER_STATUS 0x1ada
#define SEA_mmLB0_LB_BUFFER_STATUS 0x1ada
#define SEA_mmLB1_LB_BUFFER_STATUS 0x1dda
#define SEA_mmLB2_LB_BUFFER_STATUS 0x40da
#define SEA_mmLB3_LB_BUFFER_STATUS 0x43da
#define SEA_mmLB4_LB_BUFFER_STATUS 0x46da
#define SEA_mmLB5_LB_BUFFER_STATUS 0x49da
#define SEA_mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc
#define SEA_mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc
#define SEA_mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1ddc
#define SEA_mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc
#define SEA_mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x43dc
#define SEA_mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x46dc
#define SEA_mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x49dc
#define SEA_mmMVP_AFR_FLIP_MODE 0x1ae0
#define SEA_mmLB0_MVP_AFR_FLIP_MODE 0x1ae0
#define SEA_mmLB1_MVP_AFR_FLIP_MODE 0x1de0
#define SEA_mmLB2_MVP_AFR_FLIP_MODE 0x40e0
#define SEA_mmLB3_MVP_AFR_FLIP_MODE 0x43e0
#define SEA_mmLB4_MVP_AFR_FLIP_MODE 0x46e0
#define SEA_mmLB5_MVP_AFR_FLIP_MODE 0x49e0
#define SEA_mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1
#define SEA_mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1
#define SEA_mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1de1
#define SEA_mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x40e1
#define SEA_mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x43e1
#define SEA_mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x46e1
#define SEA_mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x49e1
#define SEA_mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2
#define SEA_mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2
#define SEA_mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1de2
#define SEA_mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x40e2
#define SEA_mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x43e2
#define SEA_mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x46e2
#define SEA_mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x49e2
#define SEA_mmDC_MVP_LB_CONTROL 0x1ae3
#define SEA_mmLB0_DC_MVP_LB_CONTROL 0x1ae3
#define SEA_mmLB1_DC_MVP_LB_CONTROL 0x1de3
#define SEA_mmLB2_DC_MVP_LB_CONTROL 0x40e3
#define SEA_mmLB3_DC_MVP_LB_CONTROL 0x43e3
#define SEA_mmLB4_DC_MVP_LB_CONTROL 0x46e3
#define SEA_mmLB5_DC_MVP_LB_CONTROL 0x49e3
#define SEA_mmLB_DEBUG 0x1ae4
#define SEA_mmLB0_LB_DEBUG 0x1ae4
#define SEA_mmLB1_LB_DEBUG 0x1de4
#define SEA_mmLB2_LB_DEBUG 0x40e4
#define SEA_mmLB3_LB_DEBUG 0x43e4
#define SEA_mmLB4_LB_DEBUG 0x46e4
#define SEA_mmLB5_LB_DEBUG 0x49e4
#define SEA_mmLB_DEBUG2 0x1ae5
#define SEA_mmLB0_LB_DEBUG2 0x1ae5
#define SEA_mmLB1_LB_DEBUG2 0x1de5
#define SEA_mmLB2_LB_DEBUG2 0x40e5
#define SEA_mmLB3_LB_DEBUG2 0x43e5
#define SEA_mmLB4_LB_DEBUG2 0x46e5
#define SEA_mmLB5_LB_DEBUG2 0x49e5
#define SEA_mmLB_DEBUG3 0x1ae6
#define SEA_mmLB0_LB_DEBUG3 0x1ae6
#define SEA_mmLB1_LB_DEBUG3 0x1de6
#define SEA_mmLB2_LB_DEBUG3 0x40e6
#define SEA_mmLB3_LB_DEBUG3 0x43e6
#define SEA_mmLB4_LB_DEBUG3 0x46e6
#define SEA_mmLB5_LB_DEBUG3 0x49e6
#define SEA_mmLB_TEST_DEBUG_INDEX 0x1afe
#define SEA_mmLB0_LB_TEST_DEBUG_INDEX 0x1afe
#define SEA_mmLB1_LB_TEST_DEBUG_INDEX 0x1dfe
#define SEA_mmLB2_LB_TEST_DEBUG_INDEX 0x40fe
#define SEA_mmLB3_LB_TEST_DEBUG_INDEX 0x43fe
#define SEA_mmLB4_LB_TEST_DEBUG_INDEX 0x46fe
#define SEA_mmLB5_LB_TEST_DEBUG_INDEX 0x49fe
#define SEA_mmLB_TEST_DEBUG_DATA 0x1aff
#define SEA_mmLB0_LB_TEST_DEBUG_DATA 0x1aff
#define SEA_mmLB1_LB_TEST_DEBUG_DATA 0x1dff
#define SEA_mmLB2_LB_TEST_DEBUG_DATA 0x40ff
#define SEA_mmLB3_LB_TEST_DEBUG_DATA 0x43ff
#define SEA_mmLB4_LB_TEST_DEBUG_DATA 0x46ff
#define SEA_mmLB5_LB_TEST_DEBUG_DATA 0x49ff
#define SEA_mmMVP_CONTROL1 0x1680
#define SEA_mmMVP_CONTROL2 0x1681
#define SEA_mmMVP_FIFO_CONTROL 0x1682
#define SEA_mmMVP_FIFO_STATUS 0x1683
#define SEA_mmMVP_SLAVE_STATUS 0x1684
#define SEA_mmMVP_INBAND_CNTL_CAP 0x1685
#define SEA_mmMVP_BLACK_KEYER 0x1686
#define SEA_mmMVP_CRC_CNTL 0x1687
#define SEA_mmMVP_CRC_RESULT_BLUE_GREEN 0x1688
#define SEA_mmMVP_CRC_RESULT_RED 0x1689
#define SEA_mmMVP_CONTROL3 0x168a
#define SEA_mmMVP_RECEIVE_CNT_CNTL1 0x168b
#define SEA_mmMVP_RECEIVE_CNT_CNTL2 0x168c
#define SEA_mmMVP_DEBUG 0x168f
#define SEA_mmMVP_TEST_DEBUG_INDEX 0x168d
#define SEA_mmMVP_TEST_DEBUG_DATA 0x168e
#define SEA_ixMVP_DEBUG_12 0xc
#define SEA_ixMVP_DEBUG_13 0xd
#define SEA_ixMVP_DEBUG_14 0xe
#define SEA_ixMVP_DEBUG_15 0xf
#define SEA_ixMVP_DEBUG_16 0x10
#define SEA_ixMVP_DEBUG_17 0x11
#define SEA_mmSCL_COEF_RAM_SELECT 0x1b40
#define SEA_mmSCL0_SCL_COEF_RAM_SELECT 0x1b40
#define SEA_mmSCL1_SCL_COEF_RAM_SELECT 0x1e40
#define SEA_mmSCL2_SCL_COEF_RAM_SELECT 0x4140
#define SEA_mmSCL3_SCL_COEF_RAM_SELECT 0x4440
#define SEA_mmSCL4_SCL_COEF_RAM_SELECT 0x4740
#define SEA_mmSCL5_SCL_COEF_RAM_SELECT 0x4a40
#define SEA_mmSCL_COEF_RAM_TAP_DATA 0x1b41
#define SEA_mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41
#define SEA_mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1e41
#define SEA_mmSCL2_SCL_COEF_RAM_TAP_DATA 0x4141
#define SEA_mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4441
#define SEA_mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4741
#define SEA_mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4a41
#define SEA_mmSCL_MODE 0x1b42
#define SEA_mmSCL0_SCL_MODE 0x1b42
#define SEA_mmSCL1_SCL_MODE 0x1e42
#define SEA_mmSCL2_SCL_MODE 0x4142
#define SEA_mmSCL3_SCL_MODE 0x4442
#define SEA_mmSCL4_SCL_MODE 0x4742
#define SEA_mmSCL5_SCL_MODE 0x4a42
#define SEA_mmSCL_TAP_CONTROL 0x1b43
#define SEA_mmSCL0_SCL_TAP_CONTROL 0x1b43
#define SEA_mmSCL1_SCL_TAP_CONTROL 0x1e43
#define SEA_mmSCL2_SCL_TAP_CONTROL 0x4143
#define SEA_mmSCL3_SCL_TAP_CONTROL 0x4443
#define SEA_mmSCL4_SCL_TAP_CONTROL 0x4743
#define SEA_mmSCL5_SCL_TAP_CONTROL 0x4a43
#define SEA_mmSCL_CONTROL 0x1b44
#define SEA_mmSCL0_SCL_CONTROL 0x1b44
#define SEA_mmSCL1_SCL_CONTROL 0x1e44
#define SEA_mmSCL2_SCL_CONTROL 0x4144
#define SEA_mmSCL3_SCL_CONTROL 0x4444
#define SEA_mmSCL4_SCL_CONTROL 0x4744
#define SEA_mmSCL5_SCL_CONTROL 0x4a44
#define SEA_mmSCL_BYPASS_CONTROL 0x1b45
#define SEA_mmSCL0_SCL_BYPASS_CONTROL 0x1b45
#define SEA_mmSCL1_SCL_BYPASS_CONTROL 0x1e45
#define SEA_mmSCL2_SCL_BYPASS_CONTROL 0x4145
#define SEA_mmSCL3_SCL_BYPASS_CONTROL 0x4445
#define SEA_mmSCL4_SCL_BYPASS_CONTROL 0x4745
#define SEA_mmSCL5_SCL_BYPASS_CONTROL 0x4a45
#define SEA_mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46
#define SEA_mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46
#define SEA_mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1e46
#define SEA_mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x4146
#define SEA_mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4446
#define SEA_mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4746
#define SEA_mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4a46
#define SEA_mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47
#define SEA_mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47
#define SEA_mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1e47
#define SEA_mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x4147
#define SEA_mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4447
#define SEA_mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4747
#define SEA_mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4a47
#define SEA_mmSCL_HORZ_FILTER_CONTROL 0x1b48
#define SEA_mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48
#define SEA_mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1e48
#define SEA_mmSCL2_SCL_HORZ_FILTER_CONTROL 0x4148
#define SEA_mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4448
#define SEA_mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4748
#define SEA_mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4a48
#define SEA_mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49
#define SEA_mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49
#define SEA_mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1e49
#define SEA_mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x4149
#define SEA_mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4449
#define SEA_mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4749
#define SEA_mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4a49
#define SEA_mmSCL_HORZ_FILTER_INIT 0x1b4a
#define SEA_mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a
#define SEA_mmSCL1_SCL_HORZ_FILTER_INIT 0x1e4a
#define SEA_mmSCL2_SCL_HORZ_FILTER_INIT 0x414a
#define SEA_mmSCL3_SCL_HORZ_FILTER_INIT 0x444a
#define SEA_mmSCL4_SCL_HORZ_FILTER_INIT 0x474a
#define SEA_mmSCL5_SCL_HORZ_FILTER_INIT 0x4a4a
#define SEA_mmSCL_VERT_FILTER_CONTROL 0x1b4b
#define SEA_mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b
#define SEA_mmSCL1_SCL_VERT_FILTER_CONTROL 0x1e4b
#define SEA_mmSCL2_SCL_VERT_FILTER_CONTROL 0x414b
#define SEA_mmSCL3_SCL_VERT_FILTER_CONTROL 0x444b
#define SEA_mmSCL4_SCL_VERT_FILTER_CONTROL 0x474b
#define SEA_mmSCL5_SCL_VERT_FILTER_CONTROL 0x4a4b
#define SEA_mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c
#define SEA_mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c
#define SEA_mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1e4c
#define SEA_mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x414c
#define SEA_mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x444c
#define SEA_mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x474c
#define SEA_mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x4a4c
#define SEA_mmSCL_VERT_FILTER_INIT 0x1b4d
#define SEA_mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d
#define SEA_mmSCL1_SCL_VERT_FILTER_INIT 0x1e4d
#define SEA_mmSCL2_SCL_VERT_FILTER_INIT 0x414d
#define SEA_mmSCL3_SCL_VERT_FILTER_INIT 0x444d
#define SEA_mmSCL4_SCL_VERT_FILTER_INIT 0x474d
#define SEA_mmSCL5_SCL_VERT_FILTER_INIT 0x4a4d
#define SEA_mmSCL_VERT_FILTER_INIT_BOT 0x1b4e
#define SEA_mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e
#define SEA_mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1e4e
#define SEA_mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x414e
#define SEA_mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x444e
#define SEA_mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x474e
#define SEA_mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x4a4e
#define SEA_mmSCL_ROUND_OFFSET 0x1b4f
#define SEA_mmSCL0_SCL_ROUND_OFFSET 0x1b4f
#define SEA_mmSCL1_SCL_ROUND_OFFSET 0x1e4f
#define SEA_mmSCL2_SCL_ROUND_OFFSET 0x414f
#define SEA_mmSCL3_SCL_ROUND_OFFSET 0x444f
#define SEA_mmSCL4_SCL_ROUND_OFFSET 0x474f
#define SEA_mmSCL5_SCL_ROUND_OFFSET 0x4a4f
#define SEA_mmSCL_UPDATE 0x1b51
#define SEA_mmSCL0_SCL_UPDATE 0x1b51
#define SEA_mmSCL1_SCL_UPDATE 0x1e51
#define SEA_mmSCL2_SCL_UPDATE 0x4151
#define SEA_mmSCL3_SCL_UPDATE 0x4451
#define SEA_mmSCL4_SCL_UPDATE 0x4751
#define SEA_mmSCL5_SCL_UPDATE 0x4a51
#define SEA_mmSCL_F_SHARP_CONTROL 0x1b53
#define SEA_mmSCL0_SCL_F_SHARP_CONTROL 0x1b53
#define SEA_mmSCL1_SCL_F_SHARP_CONTROL 0x1e53
#define SEA_mmSCL2_SCL_F_SHARP_CONTROL 0x4153
#define SEA_mmSCL3_SCL_F_SHARP_CONTROL 0x4453
#define SEA_mmSCL4_SCL_F_SHARP_CONTROL 0x4753
#define SEA_mmSCL5_SCL_F_SHARP_CONTROL 0x4a53
#define SEA_mmSCL_ALU_CONTROL 0x1b54
#define SEA_mmSCL0_SCL_ALU_CONTROL 0x1b54
#define SEA_mmSCL1_SCL_ALU_CONTROL 0x1e54
#define SEA_mmSCL2_SCL_ALU_CONTROL 0x4154
#define SEA_mmSCL3_SCL_ALU_CONTROL 0x4454
#define SEA_mmSCL4_SCL_ALU_CONTROL 0x4754
#define SEA_mmSCL5_SCL_ALU_CONTROL 0x4a54
#define SEA_mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55
#define SEA_mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55
#define SEA_mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1e55
#define SEA_mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x4155
#define SEA_mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4455
#define SEA_mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4755
#define SEA_mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4a55
#define SEA_mmVIEWPORT_START 0x1b5c
#define SEA_mmSCL0_VIEWPORT_START 0x1b5c
#define SEA_mmSCL1_VIEWPORT_START 0x1e5c
#define SEA_mmSCL2_VIEWPORT_START 0x415c
#define SEA_mmSCL3_VIEWPORT_START 0x445c
#define SEA_mmSCL4_VIEWPORT_START 0x475c
#define SEA_mmSCL5_VIEWPORT_START 0x4a5c
#define SEA_mmVIEWPORT_SIZE 0x1b5d
#define SEA_mmSCL0_VIEWPORT_SIZE 0x1b5d
#define SEA_mmSCL1_VIEWPORT_SIZE 0x1e5d
#define SEA_mmSCL2_VIEWPORT_SIZE 0x415d
#define SEA_mmSCL3_VIEWPORT_SIZE 0x445d
#define SEA_mmSCL4_VIEWPORT_SIZE 0x475d
#define SEA_mmSCL5_VIEWPORT_SIZE 0x4a5d
#define SEA_mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e
#define SEA_mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e
#define SEA_mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1e5e
#define SEA_mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x415e
#define SEA_mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x445e
#define SEA_mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x475e
#define SEA_mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x4a5e
#define SEA_mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f
#define SEA_mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f
#define SEA_mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1e5f
#define SEA_mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x415f
#define SEA_mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x445f
#define SEA_mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x475f
#define SEA_mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x4a5f
#define SEA_mmSCL_MODE_CHANGE_DET1 0x1b60
#define SEA_mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60
#define SEA_mmSCL1_SCL_MODE_CHANGE_DET1 0x1e60
#define SEA_mmSCL2_SCL_MODE_CHANGE_DET1 0x4160
#define SEA_mmSCL3_SCL_MODE_CHANGE_DET1 0x4460
#define SEA_mmSCL4_SCL_MODE_CHANGE_DET1 0x4760
#define SEA_mmSCL5_SCL_MODE_CHANGE_DET1 0x4a60
#define SEA_mmSCL_MODE_CHANGE_DET2 0x1b61
#define SEA_mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61
#define SEA_mmSCL1_SCL_MODE_CHANGE_DET2 0x1e61
#define SEA_mmSCL2_SCL_MODE_CHANGE_DET2 0x4161
#define SEA_mmSCL3_SCL_MODE_CHANGE_DET2 0x4461
#define SEA_mmSCL4_SCL_MODE_CHANGE_DET2 0x4761
#define SEA_mmSCL5_SCL_MODE_CHANGE_DET2 0x4a61
#define SEA_mmSCL_MODE_CHANGE_DET3 0x1b62
#define SEA_mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62
#define SEA_mmSCL1_SCL_MODE_CHANGE_DET3 0x1e62
#define SEA_mmSCL2_SCL_MODE_CHANGE_DET3 0x4162
#define SEA_mmSCL3_SCL_MODE_CHANGE_DET3 0x4462
#define SEA_mmSCL4_SCL_MODE_CHANGE_DET3 0x4762
#define SEA_mmSCL5_SCL_MODE_CHANGE_DET3 0x4a62
#define SEA_mmSCL_MODE_CHANGE_MASK 0x1b63
#define SEA_mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63
#define SEA_mmSCL1_SCL_MODE_CHANGE_MASK 0x1e63
#define SEA_mmSCL2_SCL_MODE_CHANGE_MASK 0x4163
#define SEA_mmSCL3_SCL_MODE_CHANGE_MASK 0x4463
#define SEA_mmSCL4_SCL_MODE_CHANGE_MASK 0x4763
#define SEA_mmSCL5_SCL_MODE_CHANGE_MASK 0x4a63
#define SEA_mmSCL_DEBUG2 0x1b69
#define SEA_mmSCL0_SCL_DEBUG2 0x1b69
#define SEA_mmSCL1_SCL_DEBUG2 0x1e69
#define SEA_mmSCL2_SCL_DEBUG2 0x4169
#define SEA_mmSCL3_SCL_DEBUG2 0x4469
#define SEA_mmSCL4_SCL_DEBUG2 0x4769
#define SEA_mmSCL5_SCL_DEBUG2 0x4a69
#define SEA_mmSCL_DEBUG 0x1b6a
#define SEA_mmSCL0_SCL_DEBUG 0x1b6a
#define SEA_mmSCL1_SCL_DEBUG 0x1e6a
#define SEA_mmSCL2_SCL_DEBUG 0x416a
#define SEA_mmSCL3_SCL_DEBUG 0x446a
#define SEA_mmSCL4_SCL_DEBUG 0x476a
#define SEA_mmSCL5_SCL_DEBUG 0x4a6a
#define SEA_mmSCL_TEST_DEBUG_INDEX 0x1b6b
#define SEA_mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b
#define SEA_mmSCL1_SCL_TEST_DEBUG_INDEX 0x1e6b
#define SEA_mmSCL2_SCL_TEST_DEBUG_INDEX 0x416b
#define SEA_mmSCL3_SCL_TEST_DEBUG_INDEX 0x446b
#define SEA_mmSCL4_SCL_TEST_DEBUG_INDEX 0x476b
#define SEA_mmSCL5_SCL_TEST_DEBUG_INDEX 0x4a6b
#define SEA_mmSCL_TEST_DEBUG_DATA 0x1b6c
#define SEA_mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c
#define SEA_mmSCL1_SCL_TEST_DEBUG_DATA 0x1e6c
#define SEA_mmSCL2_SCL_TEST_DEBUG_DATA 0x416c
#define SEA_mmSCL3_SCL_TEST_DEBUG_DATA 0x446c
#define SEA_mmSCL4_SCL_TEST_DEBUG_DATA 0x476c
#define SEA_mmSCL5_SCL_TEST_DEBUG_DATA 0x4a6c
#define SEA_mmGENMO_WT 0xf0
#define SEA_mmGENMO_RD 0xf3
#define SEA_mmGENENB 0xf0
#define SEA_mmGENFC_WT 0xee
#define SEA_mmVGA0_GENFC_WT 0xee
#define SEA_mmVGA1_GENFC_WT 0xf6
#define SEA_mmGENFC_RD 0xf2
#define SEA_mmGENS0 0xf0
#define SEA_mmGENS1 0xee
#define SEA_mmVGA0_GENS1 0xee
#define SEA_mmVGA1_GENS1 0xf6
#define SEA_mmDAC_DATA 0xf2
#define SEA_mmDAC_MASK 0xf1
#define SEA_mmDAC_R_INDEX 0xf1
#define SEA_mmDAC_W_INDEX 0xf2
#define SEA_mmSEQ8_IDX 0xf1
#define SEA_mmSEQ8_DATA 0xf1
#define SEA_ixSEQ00 0x0
#define SEA_ixSEQ01 0x1
#define SEA_ixSEQ02 0x2
#define SEA_ixSEQ03 0x3
#define SEA_ixSEQ04 0x4
#define SEA_mmCRTC8_IDX 0xed
#define SEA_mmVGA0_CRTC8_IDX 0xed
#define SEA_mmVGA1_CRTC8_IDX 0xf5
#define SEA_mmCRTC8_DATA 0xed
#define SEA_mmVGA0_CRTC8_DATA 0xed
#define SEA_mmVGA1_CRTC8_DATA 0xf5
#define SEA_ixCRT00 0x0
#define SEA_ixCRT01 0x1
#define SEA_ixCRT02 0x2
#define SEA_ixCRT03 0x3
#define SEA_ixCRT04 0x4
#define SEA_ixCRT05 0x5
#define SEA_ixCRT06 0x6
#define SEA_ixCRT07 0x7
#define SEA_ixCRT08 0x8
#define SEA_ixCRT09 0x9
#define SEA_ixCRT0A 0xa
#define SEA_ixCRT0B 0xb
#define SEA_ixCRT0C 0xc
#define SEA_ixCRT0D 0xd
#define SEA_ixCRT0E 0xe
#define SEA_ixCRT0F 0xf
#define SEA_ixCRT10 0x10
#define SEA_ixCRT11 0x11
#define SEA_ixCRT12 0x12
#define SEA_ixCRT13 0x13
#define SEA_ixCRT14 0x14
#define SEA_ixCRT15 0x15
#define SEA_ixCRT16 0x16
#define SEA_ixCRT17 0x17
#define SEA_ixCRT18 0x18
#define SEA_ixCRT1E 0x1e
#define SEA_ixCRT1F 0x1f
#define SEA_ixCRT22 0x22
#define SEA_mmGRPH8_IDX 0xf3
#define SEA_mmGRPH8_DATA 0xf3
#define SEA_ixGRA00 0x0
#define SEA_ixGRA01 0x1
#define SEA_ixGRA02 0x2
#define SEA_ixGRA03 0x3
#define SEA_ixGRA04 0x4
#define SEA_ixGRA05 0x5
#define SEA_ixGRA06 0x6
#define SEA_ixGRA07 0x7
#define SEA_ixGRA08 0x8
#define SEA_mmATTRX 0xf0
#define SEA_mmATTRDW 0xf0
#define SEA_mmATTRDR 0xf0
#define SEA_ixATTR00 0x0
#define SEA_ixATTR01 0x1
#define SEA_ixATTR02 0x2
#define SEA_ixATTR03 0x3
#define SEA_ixATTR04 0x4
#define SEA_ixATTR05 0x5
#define SEA_ixATTR06 0x6
#define SEA_ixATTR07 0x7
#define SEA_ixATTR08 0x8
#define SEA_ixATTR09 0x9
#define SEA_ixATTR0A 0xa
#define SEA_ixATTR0B 0xb
#define SEA_ixATTR0C 0xc
#define SEA_ixATTR0D 0xd
#define SEA_ixATTR0E 0xe
#define SEA_ixATTR0F 0xf
#define SEA_ixATTR10 0x10
#define SEA_ixATTR11 0x11
#define SEA_ixATTR12 0x12
#define SEA_ixATTR13 0x13
#define SEA_ixATTR14 0x14
#define SEA_mmVGA_RENDER_CONTROL 0xc0
#define SEA_mmVGA_SOURCE_SELECT 0xfc
#define SEA_mmVGA_SEQUENCER_RESET_CONTROL 0xc1
#define SEA_mmVGA_MODE_CONTROL 0xc2
#define SEA_mmVGA_SURFACE_PITCH_SELECT 0xc3
#define SEA_mmVGA_MEMORY_BASE_ADDRESS 0xc4
#define SEA_mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9
#define SEA_mmVGA_DISPBUF1_SURFACE_ADDR 0xc6
#define SEA_mmVGA_DISPBUF2_SURFACE_ADDR 0xc8
#define SEA_mmVGA_HDP_CONTROL 0xca
#define SEA_mmVGA_CACHE_CONTROL 0xcb
#define SEA_mmD1VGA_CONTROL 0xcc
#define SEA_mmD2VGA_CONTROL 0xce
#define SEA_mmD3VGA_CONTROL 0xf8
#define SEA_mmD4VGA_CONTROL 0xf9
#define SEA_mmD5VGA_CONTROL 0xfa
#define SEA_mmD6VGA_CONTROL 0xfb
#define SEA_mmVGA_HW_DEBUG 0xcf
#define SEA_mmVGA_STATUS 0xd0
#define SEA_mmVGA_INTERRUPT_CONTROL 0xd1
#define SEA_mmVGA_STATUS_CLEAR 0xd2
#define SEA_mmVGA_INTERRUPT_STATUS 0xd3
#define SEA_mmVGA_MAIN_CONTROL 0xd4
#define SEA_mmVGA_TEST_CONTROL 0xd5
#define SEA_mmVGA_DEBUG_READBACK_INDEX 0xd6
#define SEA_mmVGA_DEBUG_READBACK_DATA 0xd7
#define SEA_mmVGA_MEM_WRITE_PAGE_ADDR 0x12
#define SEA_mmVGA_MEM_READ_PAGE_ADDR 0x13
#define SEA_mmVGA_TEST_DEBUG_INDEX 0xc5
#define SEA_mmVGA_TEST_DEBUG_DATA 0xc7
#define SEA_ixVGADCC_DBG_DCCIF_C 0x7e
#define SEA_mmBPHYC_DAC_MACRO_CNTL 0x19fd
#define SEA_mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x19fe
#define SEA_mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30
#define SEA_mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30
#define SEA_mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1e30
#define SEA_mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x4130
#define SEA_mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4430
#define SEA_mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4730
#define SEA_mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4a30
#define SEA_mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31
#define SEA_mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31
#define SEA_mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1e31
#define SEA_mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x4131
#define SEA_mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4431
#define SEA_mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4731
#define SEA_mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4a31
#define SEA_mmDPG_WATERMARK_MASK_CONTROL 0x1b32
#define SEA_mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32
#define SEA_mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1e32
#define SEA_mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x4132
#define SEA_mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4432
#define SEA_mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4732
#define SEA_mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4a32
#define SEA_mmDPG_PIPE_URGENCY_CONTROL 0x1b33
#define SEA_mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33
#define SEA_mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1e33
#define SEA_mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x4133
#define SEA_mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4433
#define SEA_mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4733
#define SEA_mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4a33
#define SEA_mmDPG_PIPE_DPM_CONTROL 0x1b34
#define SEA_mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34
#define SEA_mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1e34
#define SEA_mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x4134
#define SEA_mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4434
#define SEA_mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4734
#define SEA_mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4a34
#define SEA_mmDPG_PIPE_STUTTER_CONTROL 0x1b35
#define SEA_mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35
#define SEA_mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1e35
#define SEA_mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x4135
#define SEA_mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4435
#define SEA_mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4735
#define SEA_mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4a35
#define SEA_mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36
#define SEA_mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36
#define SEA_mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1e36
#define SEA_mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136
#define SEA_mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4436
#define SEA_mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736
#define SEA_mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4a36
#define SEA_mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37
#define SEA_mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37
#define SEA_mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1e37
#define SEA_mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137
#define SEA_mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4437
#define SEA_mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737
#define SEA_mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4a37
#define SEA_mmDPG_REPEATER_PROGRAM 0x1b3a
#define SEA_mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a
#define SEA_mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1e3a
#define SEA_mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x413a
#define SEA_mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x443a
#define SEA_mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x473a
#define SEA_mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x4a3a
#define SEA_mmDPG_HW_DEBUG_A 0x1b3b
#define SEA_mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b
#define SEA_mmDMIF_PG1_DPG_HW_DEBUG_A 0x1e3b
#define SEA_mmDMIF_PG2_DPG_HW_DEBUG_A 0x413b
#define SEA_mmDMIF_PG3_DPG_HW_DEBUG_A 0x443b
#define SEA_mmDMIF_PG4_DPG_HW_DEBUG_A 0x473b
#define SEA_mmDMIF_PG5_DPG_HW_DEBUG_A 0x4a3b
#define SEA_mmDPG_HW_DEBUG_B 0x1b3c
#define SEA_mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c
#define SEA_mmDMIF_PG1_DPG_HW_DEBUG_B 0x1e3c
#define SEA_mmDMIF_PG2_DPG_HW_DEBUG_B 0x413c
#define SEA_mmDMIF_PG3_DPG_HW_DEBUG_B 0x443c
#define SEA_mmDMIF_PG4_DPG_HW_DEBUG_B 0x473c
#define SEA_mmDMIF_PG5_DPG_HW_DEBUG_B 0x4a3c
#define SEA_mmDPG_TEST_DEBUG_INDEX 0x1b38
#define SEA_mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38
#define SEA_mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1e38
#define SEA_mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x4138
#define SEA_mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4438
#define SEA_mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4738
#define SEA_mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4a38
#define SEA_mmDPG_TEST_DEBUG_DATA 0x1b39
#define SEA_mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39
#define SEA_mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1e39
#define SEA_mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x4139
#define SEA_mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4439
#define SEA_mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4739
#define SEA_mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4a39
#define SEA_mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18
#define SEA_mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18
#define SEA_ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00
#define SEA_ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02
#define SEA_ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04
#define SEA_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04
#define SEA_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05
#define SEA_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a
#define SEA_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b
#define SEA_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f
#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff
#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
#define SEA_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
#define SEA_mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x17d2
#define SEA_mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x17d3
#define SEA_mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x17d5
#define SEA_mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x17d6
#define SEA_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x17d7
#define SEA_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x17d8
#define SEA_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x17d9
#define SEA_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x17da
#define SEA_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x17db
#define SEA_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x17dc
#define SEA_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x17dd
#define SEA_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x17de
#define SEA_mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x17d4
#define SEA_mmAZALIA_F0_CODEC_DEBUG 0x17df
#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET0 0x17e1
#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET1 0x17e2
#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET2 0x17e3
#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET3 0x17e4
#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET4 0x17e5
#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET5 0x17e6
#define SEA_mmAZALIA_F0_GTC_GROUP_OFFSET6 0x17e7
#define SEA_mmGLOBAL_CAPABILITIES 0x0
#define SEA_mmMINOR_VERSION 0x0
#define SEA_mmMAJOR_VERSION 0x0
#define SEA_mmOUTPUT_PAYLOAD_CAPABILITY 0x1
#define SEA_mmINPUT_PAYLOAD_CAPABILITY 0x1
#define SEA_mmGLOBAL_CONTROL 0x2
#define SEA_mmWAKE_ENABLE 0x3
#define SEA_mmSTATE_CHANGE_STATUS 0x3
#define SEA_mmGLOBAL_STATUS 0x4
#define SEA_mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6
#define SEA_mmINTERRUPT_CONTROL 0x8
#define SEA_mmINTERRUPT_STATUS 0x9
#define SEA_mmWALL_CLOCK_COUNTER 0xc
#define SEA_mmSTREAM_SYNCHRONIZATION 0xe
#define SEA_mmCORB_LOWER_BASE_ADDRESS 0x10
#define SEA_mmCORB_UPPER_BASE_ADDRESS 0x11
#define SEA_mmCORB_WRITE_POINTER 0x12
#define SEA_mmCORB_READ_POINTER 0x12
#define SEA_mmCORB_CONTROL 0x13
#define SEA_mmCORB_STATUS 0x13
#define SEA_mmCORB_SIZE 0x13
#define SEA_mmRIRB_LOWER_BASE_ADDRESS 0x14
#define SEA_mmRIRB_UPPER_BASE_ADDRESS 0x15
#define SEA_mmRIRB_WRITE_POINTER 0x16
#define SEA_mmRESPONSE_INTERRUPT_COUNT 0x16
#define SEA_mmRIRB_CONTROL 0x17
#define SEA_mmRIRB_STATUS 0x17
#define SEA_mmRIRB_SIZE 0x17
#define SEA_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18
#define SEA_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18
#define SEA_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18
#define SEA_mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19
#define SEA_mmIMMEDIATE_COMMAND_STATUS 0x1a
#define SEA_mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c
#define SEA_mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d
#define SEA_mmWALL_CLOCK_COUNTER_ALIAS 0x80c
#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20
#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21
#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22
#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23
#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24
#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24
#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26
#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27
#define SEA_mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821
#define SEA_mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18
#define SEA_mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18
#define SEA_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09
#define SEA_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a
#define SEA_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b
#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d
#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e
#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e
#define SEA_ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
#define SEA_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771
#define SEA_ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09
#define SEA_ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c
#define SEA_ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
#define SEA_ixAUDIO_DESCRIPTOR0 0x1
#define SEA_ixAUDIO_DESCRIPTOR1 0x2
#define SEA_ixAUDIO_DESCRIPTOR2 0x3
#define SEA_ixAUDIO_DESCRIPTOR3 0x4
#define SEA_ixAUDIO_DESCRIPTOR4 0x5
#define SEA_ixAUDIO_DESCRIPTOR5 0x6
#define SEA_ixAUDIO_DESCRIPTOR6 0x7
#define SEA_ixAUDIO_DESCRIPTOR7 0x8
#define SEA_ixAUDIO_DESCRIPTOR8 0x9
#define SEA_ixAUDIO_DESCRIPTOR9 0xa
#define SEA_ixAUDIO_DESCRIPTOR10 0xb
#define SEA_ixAUDIO_DESCRIPTOR11 0xc
#define SEA_ixAUDIO_DESCRIPTOR12 0xd
#define SEA_ixAUDIO_DESCRIPTOR13 0xe
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4
#define SEA_ixSINK_DESCRIPTION0 0x5
#define SEA_ixSINK_DESCRIPTION1 0x6
#define SEA_ixSINK_DESCRIPTION2 0x7
#define SEA_ixSINK_DESCRIPTION3 0x8
#define SEA_ixSINK_DESCRIPTION4 0x9
#define SEA_ixSINK_DESCRIPTION5 0xa
#define SEA_ixSINK_DESCRIPTION6 0xb
#define SEA_ixSINK_DESCRIPTION7 0xc
#define SEA_ixSINK_DESCRIPTION8 0xd
#define SEA_ixSINK_DESCRIPTION9 0xe
#define SEA_ixSINK_DESCRIPTION10 0xf
#define SEA_ixSINK_DESCRIPTION11 0x10
#define SEA_ixSINK_DESCRIPTION12 0x11
#define SEA_ixSINK_DESCRIPTION13 0x12
#define SEA_ixSINK_DESCRIPTION14 0x13
#define SEA_ixSINK_DESCRIPTION15 0x14
#define SEA_ixSINK_DESCRIPTION16 0x15
#define SEA_ixSINK_DESCRIPTION17 0x16
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a
#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b
#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c
#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d
#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e
#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f
#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
#define SEA_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
#define SEA_ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
#define SEA_ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797
#define SEA_mmAZALIA_CONTROLLER_CLOCK_GATING 0x17b9
#define SEA_mmAZALIA_AUDIO_DTO 0x17ba
#define SEA_mmAZALIA_AUDIO_DTO_CONTROL 0x17bb
#define SEA_mmAZALIA_SCLK_CONTROL 0x17bc
#define SEA_mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17bd
#define SEA_mmAZALIA_DATA_DMA_CONTROL 0x17be
#define SEA_mmAZALIA_BDL_DMA_CONTROL 0x17bf
#define SEA_mmAZALIA_RIRB_AND_DP_CONTROL 0x17c0
#define SEA_mmAZALIA_CORB_DMA_CONTROL 0x17c1
#define SEA_mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17c9
#define SEA_mmAZALIA_CYCLIC_BUFFER_SYNC 0x17ca
#define SEA_mmAZALIA_GLOBAL_CAPABILITIES 0x17cb
#define SEA_mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17cc
#define SEA_mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17cd
#define SEA_mmAZALIA_CONTROLLER_DEBUG 0x17cf
#define SEA_mmAZALIA_CRC0_CONTROL0 0x17ae
#define SEA_mmAZALIA_CRC0_CONTROL1 0x17af
#define SEA_mmAZALIA_CRC0_CONTROL2 0x17b0
#define SEA_mmAZALIA_CRC0_CONTROL3 0x17b1
#define SEA_mmAZALIA_CRC0_RESULT 0x17b2
#define SEA_ixAZALIA_CRC0_CHANNEL0 0x0
#define SEA_ixAZALIA_CRC0_CHANNEL1 0x1
#define SEA_ixAZALIA_CRC0_CHANNEL2 0x2
#define SEA_ixAZALIA_CRC0_CHANNEL3 0x3
#define SEA_ixAZALIA_CRC0_CHANNEL4 0x4
#define SEA_ixAZALIA_CRC0_CHANNEL5 0x5
#define SEA_ixAZALIA_CRC0_CHANNEL6 0x6
#define SEA_ixAZALIA_CRC0_CHANNEL7 0x7
#define SEA_mmAZALIA_CRC1_CONTROL0 0x17b3
#define SEA_mmAZALIA_CRC1_CONTROL1 0x17b4
#define SEA_mmAZALIA_CRC1_CONTROL2 0x17b5
#define SEA_mmAZALIA_CRC1_CONTROL3 0x17b6
#define SEA_mmAZALIA_CRC1_RESULT 0x17b7
#define SEA_ixAZALIA_CRC1_CHANNEL0 0x0
#define SEA_ixAZALIA_CRC1_CHANNEL1 0x1
#define SEA_ixAZALIA_CRC1_CHANNEL2 0x2
#define SEA_ixAZALIA_CRC1_CHANNEL3 0x3
#define SEA_ixAZALIA_CRC1_CHANNEL4 0x4
#define SEA_ixAZALIA_CRC1_CHANNEL5 0x5
#define SEA_ixAZALIA_CRC1_CHANNEL6 0x6
#define SEA_ixAZALIA_CRC1_CHANNEL7 0x7
#define SEA_mmAZ_TEST_DEBUG_INDEX 0x17d0
#define SEA_mmAZ_TEST_DEBUG_DATA 0x17d1
#define SEA_mmAZALIA_STREAM_INDEX 0x17e8
#define SEA_mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x17e8
#define SEA_mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x17ec
#define SEA_mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x17f0
#define SEA_mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x17f4
#define SEA_mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x17f8
#define SEA_mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x17fc
#define SEA_mmAZALIA_STREAM_DATA 0x17e9
#define SEA_mmAZF0STREAM0_AZALIA_STREAM_DATA 0x17e9
#define SEA_mmAZF0STREAM1_AZALIA_STREAM_DATA 0x17ed
#define SEA_mmAZF0STREAM2_AZALIA_STREAM_DATA 0x17f1
#define SEA_mmAZF0STREAM3_AZALIA_STREAM_DATA 0x17f5
#define SEA_mmAZF0STREAM4_AZALIA_STREAM_DATA 0x17f9
#define SEA_mmAZF0STREAM5_AZALIA_STREAM_DATA 0x17fd
#define SEA_ixAZALIA_FIFO_SIZE_CONTROL 0x0
#define SEA_ixAZALIA_LATENCY_COUNTER_CONTROL 0x1
#define SEA_ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2
#define SEA_ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3
#define SEA_ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4
#define SEA_ixAZALIA_STREAM_DEBUG 0x5
#define SEA_mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780
#define SEA_mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780
#define SEA_mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1786
#define SEA_mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x178c
#define SEA_mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1792
#define SEA_mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1798
#define SEA_mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x179e
#define SEA_mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a4
#define SEA_mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x1781
#define SEA_mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1781
#define SEA_mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1787
#define SEA_mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x178d
#define SEA_mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1793
#define SEA_mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1799
#define SEA_mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x179f
#define SEA_mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a5
#define SEA_ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0
#define SEA_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1
#define SEA_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2
#define SEA_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3
#define SEA_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4
#define SEA_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5
#define SEA_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6
#define SEA_ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7
#define SEA_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8
#define SEA_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9
#define SEA_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa
#define SEA_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc
#define SEA_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd
#define SEA_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe
#define SEA_ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20
#define SEA_ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56
#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59
#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a
#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b
#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c
#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d
#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e
#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f
#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60
#define SEA_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61
#define SEA_ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62
#define SEA_ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63
#define SEA_mmBLND_CONTROL 0x1b6d
#define SEA_mmBLND0_BLND_CONTROL 0x1b6d
#define SEA_mmBLND1_BLND_CONTROL 0x1e6d
#define SEA_mmBLND2_BLND_CONTROL 0x416d
#define SEA_mmBLND3_BLND_CONTROL 0x446d
#define SEA_mmBLND4_BLND_CONTROL 0x476d
#define SEA_mmBLND5_BLND_CONTROL 0x4a6d
#define SEA_mmSM_CONTROL2 0x1b6e
#define SEA_mmBLND0_SM_CONTROL2 0x1b6e
#define SEA_mmBLND1_SM_CONTROL2 0x1e6e
#define SEA_mmBLND2_SM_CONTROL2 0x416e
#define SEA_mmBLND3_SM_CONTROL2 0x446e
#define SEA_mmBLND4_SM_CONTROL2 0x476e
#define SEA_mmBLND5_SM_CONTROL2 0x4a6e
#define SEA_mmPTI_CONTROL 0x1b6f
#define SEA_mmBLND0_PTI_CONTROL 0x1b6f
#define SEA_mmBLND1_PTI_CONTROL 0x1e6f
#define SEA_mmBLND2_PTI_CONTROL 0x416f
#define SEA_mmBLND3_PTI_CONTROL 0x446f
#define SEA_mmBLND4_PTI_CONTROL 0x476f
#define SEA_mmBLND5_PTI_CONTROL 0x4a6f
#define SEA_mmBLND_UPDATE 0x1b70
#define SEA_mmBLND0_BLND_UPDATE 0x1b70
#define SEA_mmBLND1_BLND_UPDATE 0x1e70
#define SEA_mmBLND2_BLND_UPDATE 0x4170
#define SEA_mmBLND3_BLND_UPDATE 0x4470
#define SEA_mmBLND4_BLND_UPDATE 0x4770
#define SEA_mmBLND5_BLND_UPDATE 0x4a70
#define SEA_mmBLND_UNDERFLOW_INTERRUPT 0x1b71
#define SEA_mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71
#define SEA_mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1e71
#define SEA_mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x4171
#define SEA_mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4471
#define SEA_mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4771
#define SEA_mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4a71
#define SEA_mmBLND_V_UPDATE_LOCK 0x1b73
#define SEA_mmBLND0_BLND_V_UPDATE_LOCK 0x1b73
#define SEA_mmBLND1_BLND_V_UPDATE_LOCK 0x1e73
#define SEA_mmBLND2_BLND_V_UPDATE_LOCK 0x4173
#define SEA_mmBLND3_BLND_V_UPDATE_LOCK 0x4473
#define SEA_mmBLND4_BLND_V_UPDATE_LOCK 0x4773
#define SEA_mmBLND5_BLND_V_UPDATE_LOCK 0x4a73
#define SEA_mmBLND_REG_UPDATE_STATUS 0x1b77
#define SEA_mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77
#define SEA_mmBLND1_BLND_REG_UPDATE_STATUS 0x1e77
#define SEA_mmBLND2_BLND_REG_UPDATE_STATUS 0x4177
#define SEA_mmBLND3_BLND_REG_UPDATE_STATUS 0x4477
#define SEA_mmBLND4_BLND_REG_UPDATE_STATUS 0x4777
#define SEA_mmBLND5_BLND_REG_UPDATE_STATUS 0x4a77
#define SEA_mmBLND_DEBUG 0x1b74
#define SEA_mmBLND0_BLND_DEBUG 0x1b74
#define SEA_mmBLND1_BLND_DEBUG 0x1e74
#define SEA_mmBLND2_BLND_DEBUG 0x4174
#define SEA_mmBLND3_BLND_DEBUG 0x4474
#define SEA_mmBLND4_BLND_DEBUG 0x4774
#define SEA_mmBLND5_BLND_DEBUG 0x4a74
#define SEA_mmBLND_TEST_DEBUG_INDEX 0x1b75
#define SEA_mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75
#define SEA_mmBLND1_BLND_TEST_DEBUG_INDEX 0x1e75
#define SEA_mmBLND2_BLND_TEST_DEBUG_INDEX 0x4175
#define SEA_mmBLND3_BLND_TEST_DEBUG_INDEX 0x4475
#define SEA_mmBLND4_BLND_TEST_DEBUG_INDEX 0x4775
#define SEA_mmBLND5_BLND_TEST_DEBUG_INDEX 0x4a75
#define SEA_mmBLND_TEST_DEBUG_DATA 0x1b76
#define SEA_mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76
#define SEA_mmBLND1_BLND_TEST_DEBUG_DATA 0x1e76
#define SEA_mmBLND2_BLND_TEST_DEBUG_DATA 0x4176
#define SEA_mmBLND3_BLND_TEST_DEBUG_DATA 0x4476
#define SEA_mmBLND4_BLND_TEST_DEBUG_DATA 0x4776
#define SEA_mmBLND5_BLND_TEST_DEBUG_DATA 0x4a76
#define SEA_mmSI_ENABLE 0x4c00
#define SEA_mmSI_EC_CONFIG 0x4c01
#define SEA_mmCNV_MODE 0x4c02
#define SEA_mmCNV_WINDOW_START 0x4c03
#define SEA_mmCNV_WINDOW_SIZE 0x4c04
#define SEA_mmCNV_UPDATE 0x4c05
#define SEA_mmCNV_SOURCE_SIZE 0x4c06
#define SEA_mmCNV_CSC_CONTROL 0x4c07
#define SEA_mmCNV_CSC_C11_C12 0x4c08
#define SEA_mmCNV_CSC_C13_C14 0x4c09
#define SEA_mmCNV_CSC_C21_C22 0x4c0a
#define SEA_mmCNV_CSC_C23_C24 0x4c0b
#define SEA_mmCNV_CSC_C31_C32 0x4c0c
#define SEA_mmCNV_CSC_C33_C34 0x4c0d
#define SEA_mmCNV_CSC_ROUND_OFFSET_R 0x4c0e
#define SEA_mmCNV_CSC_ROUND_OFFSET_G 0x4c0f
#define SEA_mmCNV_CSC_ROUND_OFFSET_B 0x4c10
#define SEA_mmCNV_CSC_CLAMP_R 0x4c11
#define SEA_mmCNV_CSC_CLAMP_G 0x4c12
#define SEA_mmCNV_CSC_CLAMP_B 0x4c13
#define SEA_mmCNV_TEST_CNTL 0x4c14
#define SEA_mmCNV_TEST_CRC_RED 0x4c15
#define SEA_mmCNV_TEST_CRC_GREEN 0x4c16
#define SEA_mmCNV_TEST_CRC_BLUE 0x4c17
#define SEA_mmSI_DEBUG_CTRL 0x4c18
#define SEA_mmSI_DBG_MODE 0x4c1b
#define SEA_mmSI_HARD_DEBUG 0x4c1c
#define SEA_mmCNV_TEST_DEBUG_INDEX 0x4c19
#define SEA_mmCNV_TEST_DEBUG_DATA 0x4c1a
#define SEA_mmSISCL_COEF_RAM_SELECT 0x4c20
#define SEA_mmSISCL_COEF_RAM_TAP_DATA 0x4c21
#define SEA_mmSISCL_MODE 0x4c22
#define SEA_mmSISCL_TAP_CONTROL 0x4c23
#define SEA_mmSISCL_DEST_SIZE 0x4c24
#define SEA_mmSISCL_HORZ_FILTER_SCALE_RATIO 0x4c25
#define SEA_mmSISCL_HORZ_FILTER_INIT_Y_RGB 0x4c26
#define SEA_mmSISCL_HORZ_FILTER_INIT_CBCR 0x4c27
#define SEA_mmSISCL_VERT_FILTER_SCALE_RATIO 0x4c28
#define SEA_mmSISCL_VERT_FILTER_INIT_Y_RGB 0x4c29
#define SEA_mmSISCL_VERT_FILTER_INIT_CBCR 0x4c2a
#define SEA_mmSISCL_ROUND_OFFSET 0x4c2b
#define SEA_mmSISCL_CLAMP 0x4c2c
#define SEA_mmSISCL_OVERFLOW_STATUS 0x4c2d
#define SEA_mmSISCL_COEF_RAM_CONFLICT_STATUS 0x4c2e
#define SEA_mmSISCL_OUTSIDE_PIX_STRATEGY 0x4c2f
#define SEA_mmSISCL_TEST_CNTL 0x4c30
#define SEA_mmSISCL_TEST_CRC_RED 0x4c31
#define SEA_mmSISCL_TEST_CRC_GREEN 0x4c32
#define SEA_mmSISCL_TEST_CRC_BLUE 0x4c33
#define SEA_mmSISCL_BACKPRESSURE_CNT_EN 0x4c36
#define SEA_mmSISCL_MCIF_BACKPRESSURE_CNT 0x4c37
#define SEA_mmSISCL_TEST_DEBUG_INDEX 0x4c34
#define SEA_mmSISCL_TEST_DEBUG_DATA 0x4c35
#define SEA_mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0
#define SEA_mmXDMA_LOCAL_SURFACE_TILING1 0x3e1
#define SEA_mmXDMA_LOCAL_SURFACE_TILING2 0x3e2
#define SEA_mmXDMA_INTERRUPT 0x3e3
#define SEA_mmXDMA_CLOCK_GATING_CNTL 0x3e4
#define SEA_mmXDMA_MEM_POWER_CNTL 0x3e6
#define SEA_mmXDMA_IF_BIF_STATUS 0x3e7
#define SEA_mmXDMA_PERF_MEAS_STATUS 0x3e8
#define SEA_mmXDMA_IF_STATUS 0x3e9
#define SEA_mmXDMA_TEST_DEBUG_INDEX 0x3ea
#define SEA_mmXDMA_TEST_DEBUG_DATA 0x3eb
#define SEA_mmXDMA_RBBMIF_RDWR_CNTL 0x3f8
#define SEA_mmXDMA_PG_CONTROL 0x3f9
#define SEA_mmXDMA_PG_WDATA 0x3fa
#define SEA_mmXDMA_PG_STATUS 0x3fb
#define SEA_mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc
#define SEA_mmXDMA_AON_TEST_DEBUG_DATA 0x3fd
#endif /* DCE_8_0_D_H */
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