2014-05-06 23:15:55 +04:00
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/*
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* Copyright 2014, Paweł Dziepak, pdziepak@quarnos.org.
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* Distributed under the terms of the MIT License.
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*/
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#ifndef _KERNEL_ARCH_X86_64_CPU_H
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#define _KERNEL_ARCH_X86_64_CPU_H
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#include <arch_thread_types.h>
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2014-05-06 23:41:49 +04:00
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static inline uint64_t
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x86_read_msr(uint32_t msr)
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{
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uint64_t high, low;
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asm volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
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return (high << 32) | low;
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}
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static inline void
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x86_write_msr(uint32_t msr, uint64_t value)
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{
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asm volatile("wrmsr" : : "a" (value) , "d" (value >> 32), "c" (msr));
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}
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2014-05-06 23:15:55 +04:00
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static inline void
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x86_context_switch(arch_thread* oldState, arch_thread* newState)
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{
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asm volatile(
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"pushq %%rbp;"
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"movq $1f, %c[rip](%0);"
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"movq %%rsp, %c[rsp](%0);"
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"movq %c[rsp](%1), %%rsp;"
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"jmp *%c[rip](%1);"
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"1:"
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"popq %%rbp;"
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:
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: "a" (oldState), "d" (newState),
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[rsp] "i" (offsetof(arch_thread, current_stack)),
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[rip] "i" (offsetof(arch_thread, instruction_pointer))
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: "rbx", "rcx", "rdi", "rsi", "r8", "r9", "r10", "r11", "r12", "r13",
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"r14", "r15", "memory");
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}
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#endif // _KERNEL_ARCH_X86_64_CPU_H
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