RV32I hw layer update

components/hw/RISC-V/RV32I/hw_cpu.S

@@ -42,6 +42,9 @@
 #endif
 
 ;FX_METADATA(({ implementation: [HW_CPU, RV32I] }))
+ASM_ENTRY1(hw_cpu_mcause_get)
+    csrr    a0, mcause
+    ret
 
 ASM_ENTRY1(hw_cpu_dmb)
     fence
@@ -49,8 +52,7 @@ ASM_ENTRY1(hw_cpu_dmb)
 
 ASM_ENTRY1(hw_cpu_atomic_cas)
     fence
-    csrr    t0, mstatus
-    csrc    mstatus, RV_SPEC_MSTATUS_MIE
+    csrrci  t0, mstatus, RV_SPEC_MSTATUS_MIE
     lw      t1, (a0)
     bne     t1, a1, 1f
     sw      a2, (a0)
@@ -62,8 +64,7 @@ ASM_ENTRY1(hw_cpu_atomic_cas)
 
 ASM_ENTRY1(hw_cpu_atomic_swap)
     fence
-    csrr    t0, mstatus
-    csrc    mstatus, RV_SPEC_MSTATUS_MIE
+    csrrci  t0, mstatus, RV_SPEC_MSTATUS_MIE
     lw      t1, (a0)
     sw      a1, (a0)
     csrw    mstatus, t0
@@ -73,8 +74,7 @@ ASM_ENTRY1(hw_cpu_atomic_swap)
 
 ASM_ENTRY1(hw_cpu_atomic_add)
     fence
-    csrr    t0, mstatus
-    csrc    mstatus, RV_SPEC_MSTATUS_MIE
+    csrrci  t0, mstatus, RV_SPEC_MSTATUS_MIE
     lw      t1, (a0)
     add     a1, a1, t1
     sw      a1, (a0)
@@ -84,7 +84,7 @@ ASM_ENTRY1(hw_cpu_atomic_add)
     ret
 
 ASM_ENTRY1(hw_cpu_clz)
-    mv      a1, a0
+	mv		a1, a0
     li	    a2, 0x80000000
     li      a0, 0
 1:
@@ -114,7 +114,7 @@ ASM_ENTRY1(hw_cpu_idle)
     ret
 
 ASM_ENTRY1(hw_cpu_intr_enable)
-    csrs    mstatus, RV_SPEC_MSTATUS_MIE
+    csrsi   mstatus, RV_SPEC_MSTATUS_MIE
     ret
 
 ASM_ENTRY1(hw_cpu_intr_disable)

components/hw/RISC-V/RV32I/hw_cpu.h

@@ -49,6 +49,7 @@ uintptr_t hw_cpu_mscratch_get(void);
 void hw_cpu_mscratch_set(uintptr_t);
 uintptr_t hw_cpu_mstatus_get(void);
 uintptr_t hw_cpu_mie_get(void);
+uintptr_t hw_cpu_mcause_get(void);
 void hw_cpu_mie_set(uintptr_t);
 void hw_cpu_msie_set(unsigned int);