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update unified HAL and HW for risc-v

This commit is contained in:
cbuilder 2021-05-20 13:59:26 +03:00
parent 604748c0e0
commit 5990e0bfc4
7 changed files with 84 additions and 99 deletions
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113
components/hal/RISCV32I/intr/hal_cpu_intr0.S
View File

@ -33,75 +33,41 @@
;FX_METADATA(({ implementation: [HAL_CPU_INTR, RV32I] }))
#define MSTATUS_MPP_M (3 << 11)
#define MSTATUS_MPIE (1 << 7)
#define CONTEXT_SIZE (29 * 4)
#define SAVE____GPRS \
sw ra, 4(sp); \
sw x5, 8(sp); \
sw x6, 12(sp); \
sw x7, 16(sp); \
sw x28, 20(sp); \
sw x29, 24(sp); \
sw x30, 28(sp); \
sw x31, 32(sp); \
sw x10, 36(sp); \
sw x11, 40(sp); \
sw x12, 44(sp); \
sw x13, 48(sp); \
sw x14, 52(sp); \
sw x15, 56(sp); \
sw x16, 60(sp); \
sw x17, 64(sp); \
sw x8, 68(sp); \
sw x9, 72(sp); \
sw x18, 76(sp); \
sw x19, 80(sp); \
sw x20, 84(sp); \
sw x21, 88(sp); \
sw x22, 92(sp); \
sw x23, 96(sp); \
sw x24, 100(sp); \
sw x25, 104(sp); \
sw x26, 108(sp); \
sw x27, 112(sp);
#define LOAD____GPRS \
lw ra, 4(sp); \
lw x5, 8(sp); \
lw x6, 12(sp); \
lw x7, 16(sp); \
lw x28, 20(sp); \
lw x29, 24(sp); \
lw x30, 28(sp); \
lw x31, 32(sp); \
lw x10, 36(sp); \
lw x11, 40(sp); \
lw x12, 44(sp); \
lw x13, 48(sp); \
lw x14, 52(sp); \
lw x15, 56(sp); \
lw x16, 60(sp); \
lw x17, 64(sp); \
lw x8, 68(sp); \
lw x9, 72(sp); \
lw x18, 76(sp); \
lw x19, 80(sp); \
lw x20, 84(sp); \
lw x21, 88(sp); \
lw x22, 92(sp); \
lw x23, 96(sp); \
lw x24, 100(sp); \
lw x25, 104(sp); \
lw x26, 108(sp); \
lw x27, 112(sp);
/*TODO: context save/restore with interrupts enabled. */
#define MOVE____GPRS(cmd) \
cmd ra, 4(sp); \
cmd x5, 8(sp); \
cmd x6, 12(sp); \
cmd x7, 16(sp); \
cmd x28, 20(sp); \
cmd x29, 24(sp); \
cmd x30, 28(sp); \
cmd x31, 32(sp); \
cmd x10, 36(sp); \
cmd x11, 40(sp); \
cmd x12, 44(sp); \
cmd x13, 48(sp); \
cmd x14, 52(sp); \
cmd x15, 56(sp); \
cmd x16, 60(sp); \
cmd x17, 64(sp); \
cmd x8, 68(sp); \
cmd x9, 72(sp); \
cmd x18, 76(sp); \
cmd x19, 80(sp); \
cmd x20, 84(sp); \
cmd x21, 88(sp); \
cmd x22, 92(sp); \
cmd x23, 96(sp); \
cmd x24, 100(sp); \
cmd x25, 104(sp); \
cmd x26, 108(sp); \
cmd x27, 112(sp);
ASM_ENTRY1(hal_intr_entry)
addi sp, sp, -CONTEXT_SIZE
SAVE____GPRS
MOVE____GPRS(sw)
csrr t0, mepc
sw t0, 0(sp)
csrr a0, mcause
@ -126,13 +92,13 @@ asynchronous_intr:
la t0, g_hal_intr_stack_frame
lw sp, 0(t0)
context_restore:
li t0, (MSTATUS_MPP_M | MSTATUS_MPIE)
csrw mstatus, t0
li t0, (RV_SPEC_MSTATUS_MPP_M | RV_SPEC_MSTATUS_MPIE)
csrs mstatus, t0
lw t0, 0(sp)
csrw mepc, t0
LOAD____GPRS
MOVE____GPRS(lw)
addi sp, sp, CONTEXT_SIZE
mret
RV_SPEC_INT_RET
synchronous_trap:
jal hal_trap_handler
j context_restore
@ -140,9 +106,8 @@ synchronous_trap:
ASM_ENTRY1(hal_intr_check_swi)
addi sp, sp, -CONTEXT_SIZE
SAVE____GPRS
MOVE____GPRS(sw)
sw ra, 0(sp)
csrc mstatus, 8
la t0, g_hal_intr_nesting
li t1, 1
sw t1, 0(t0)
@ -157,8 +122,8 @@ ASM_ENTRY1(hal_intr_check_swi)
lw sp, 0(t0)
lw t0, 0(sp)
csrw mepc, t0
li t0, (MSTATUS_MPP_M | MSTATUS_MPIE)
csrw mstatus, t0
LOAD____GPRS
li t0, (RV_SPEC_MSTATUS_MPP_M | RV_SPEC_MSTATUS_MPIE)
csrs mstatus, t0
MOVE____GPRS(lw)
addi sp, sp, CONTEXT_SIZE
mret
RV_SPEC_INT_RET

27
components/hal/RISCV32I/intr/hal_cpu_intr1.c
View File

@ -30,7 +30,7 @@
#include FX_INTERFACE(HAL_CPU_INTR)
#include FX_INTERFACE(HW_CPU)
FX_METADATA(({ implementation: [HAL_CPU_INTR, RV32I] }))
hal_intr_frame_t* volatile g_hal_intr_stack_frame = NULL;
@ -53,7 +53,7 @@ _hal_async_spl_set(const spl_t spl)
//!
//! Calls Os' dispatch interrupt handler.
//! @warning Caller must raise SP to SPL_SYNC.
//! @warning Caller must raise SPL to SPL_ISR.
//!
static inline void
_hal_intr_swi_dispatch(void)
@ -61,9 +61,9 @@ _hal_intr_swi_dispatch(void)
while (g_hal_intr_dispatch_req != 0)
{
g_hal_intr_dispatch_req = 0;
hal_async_lower_spl(SPL_DISPATCH);
hw_cpu_intr_enable();
fx_dispatch_handler();
(void) hal_async_raise_spl(SPL_SYNC);
hw_cpu_intr_disable();
}
}
@ -75,12 +75,6 @@ hal_async_raise_spl(const spl_t spl)
{
hw_cpu_intr_disable();
const spl_t old_spl = _hal_async_spl_set(spl);
if (spl != SPL_SYNC)
{
hw_cpu_intr_enable();
}
return old_spl;
}
@ -98,8 +92,7 @@ hal_async_lower_spl(const spl_t spl)
{
hal_intr_check_swi();
}
if (spl != SPL_SYNC)
else if (spl != SPL_SYNC)
{
hw_cpu_intr_enable();
}
@ -148,17 +141,16 @@ hal_intr_handler(uint32_t mcause)
}
else
{
hw_cpu_intr_enable();
fx_intr_handler();
}
hw_cpu_intr_disable();
if (prev_spl == SPL_LOW)
{
(void) hal_async_raise_spl(SPL_SYNC);
_hal_intr_swi_dispatch();
}
hw_cpu_intr_disable();
_hal_async_spl_set(prev_spl);
}
@ -173,7 +165,7 @@ hal_intr_handler(uint32_t mcause)
void
hal_swi_handler(void)
{
(void) hal_async_raise_spl(SPL_SYNC);
_hal_async_spl_set(SPL_ISR);
_hal_intr_swi_dispatch();
_hal_async_spl_set(SPL_LOW);
}
@ -242,4 +234,3 @@ hal_intr_frame_alloc(hal_intr_frame_t* base)
return frame;
}

14
components/hw/RISCV32I/RV32I/hw_cpu.S
View File

@ -35,8 +35,10 @@
;//
#ifndef FX_INTERFACE
#include <LANG_ASM.h>
#include <CFG_OPTIONS.h>
#else
#include FX_INTERFACE(LANG_ASM)
#include FX_INTERFACE(CFG_OPTIONS)
#endif
;FX_METADATA(({ implementation: [HW_CPU, RV32I] }))
@ -48,7 +50,7 @@ ASM_ENTRY1(hw_cpu_dmb)
ASM_ENTRY1(hw_cpu_atomic_cas)
fence
csrr t0, mstatus
csrc mstatus, 8
csrc mstatus, RV_SPEC_MSTATUS_MIE
lw t1, (a0)
bne t1, a1, 1f
sw a2, (a0)
@ -61,7 +63,7 @@ ASM_ENTRY1(hw_cpu_atomic_cas)
ASM_ENTRY1(hw_cpu_atomic_swap)
fence
csrr t0, mstatus
csrc mstatus, 8
csrc mstatus, RV_SPEC_MSTATUS_MIE
lw t1, (a0)
sw a1, (a0)
csrw mstatus, t0
@ -72,7 +74,7 @@ ASM_ENTRY1(hw_cpu_atomic_swap)
ASM_ENTRY1(hw_cpu_atomic_add)
fence
csrr t0, mstatus
csrc mstatus, 8
csrc mstatus, RV_SPEC_MSTATUS_MIE
lw t1, (a0)
add a1, a1, t1
sw a1, (a0)
@ -82,7 +84,7 @@ ASM_ENTRY1(hw_cpu_atomic_add)
ret
ASM_ENTRY1(hw_cpu_clz)
mv a1, a0
mv a1, a0
li a2, 0x80000000
li a0, 0
1:
@ -112,9 +114,9 @@ ASM_ENTRY1(hw_cpu_idle)
ret
ASM_ENTRY1(hw_cpu_intr_enable)
csrs mstatus, 8
csrs mstatus, RV_SPEC_MSTATUS_MIE
ret
ASM_ENTRY1(hw_cpu_intr_disable)
csrc mstatus, 8
csrci mstatus, RV_SPEC_MSTATUS_MIE
ret

19
components/hw/RISCV32I/RV32I/hw_cpu.h
View File

@ -33,6 +33,25 @@
#include FX_INTERFACE(LANG_TYPES)
enum
{
HW_CPU_TIMER_VECT = 7,
HW_CPU_SWI_VECT = 3,
HW_CPU_MSTATUS_MIE = 8,
HW_CPU_MIE_MSIE = 8,
};
//!
//! System CSRs access.
//!
uintptr_t hw_cpu_mscratch_get(void);
void hw_cpu_mscratch_set(uintptr_t);
uintptr_t hw_cpu_mstatus_get(void);
uintptr_t hw_cpu_mie_get(void);
void hw_cpu_mie_set(uintptr_t);
void hw_cpu_msie_set(unsigned int);
//!
//! Memory barrier.
//!

3
components/rtl/list/rtl_list.h
View File

@ -64,7 +64,8 @@ rtl_list_remove(rtl_list_t* node)
{
node->prev->next = node->next;
node->next->prev = node->prev;
node->next = node->prev = (rtl_list_linkage_t*)0;
node->next = (rtl_list_linkage_t*)0;
node->prev = (rtl_list_linkage_t*)0;
}
static inline void

6
cores/production/standard-riscv32i-GNU-tools/standard-rv32i-gnu-options.h
View File

@ -37,6 +37,12 @@
#define HAL_INTR_STACK_SIZE 0x400
#define RTL_MEM_POOL_MAX_CHUNK 15
#define RV_SPEC_MSTATUS_MPP_M (3 << 11)
#define RV_SPEC_MSTATUS_MPIE (1 << 7)
#define RV_SPEC_MSTATUS_MIE 8
#define RV_SPEC_INT_RET mret
FX_METADATA(({ interface: [CFG_OPTIONS, STANDARD_RV32I_GNU] }))
#endif

1
cores/production/standard-riscv32i-GNU-tools/standard-rv32i-gnu.h
View File

@ -30,6 +30,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#include FX_INTERFACE(HW_CPU)
#include FX_INTERFACE(HAL_INIT)
#include FX_INTERFACE(HAL_CPU_INTR)
#include FX_INTERFACE(FX_TIMER)