166 lines
3.7 KiB
C
166 lines
3.7 KiB
C
/* $NetBSD: io.c,v 1.7 2010/10/14 05:52:01 kiyohara Exp $ */
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/*-
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* Copyright (C) 1995-1997 Gary Thomas (gdt@linuxppc.org)
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* All rights reserved.
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*
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* PCI/ISA I/O support
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Gary Thomas.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <lib/libsa/stand.h>
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#include "boot.h"
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volatile u_char *PCI_mem = (u_char *)0xc0000000;
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volatile u_char *ISA_io = (u_char *)0x80000000;
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volatile u_char *ISA_mem = (u_char *)0xc0000000;
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static int dcache_line_size = 32;
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void
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outb(int port, u_char val)
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{
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ISA_io[port] = val;
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}
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void
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outw(int port, u_short val)
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{
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outb(port, val >> 8);
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outb(port + 1, val);
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}
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u_char
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inb(int port)
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{
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return ISA_io[port];
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}
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u_short
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inw(int port)
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{
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return *((volatile uint16_t *)(&ISA_io[port]));
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}
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u_short
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inwrb(int port)
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{
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return le16toh(*((volatile uint16_t *)(&ISA_io[port])));
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}
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void
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writeb(u_long addr, u_char val)
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{
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PCI_mem[addr] = val;
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}
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void
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writel(u_long addr, u_long val)
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{
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*((u_long *)&PCI_mem[addr]) = htole32(val);
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}
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u_char
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readb(u_long addr)
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{
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return PCI_mem[addr];
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}
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u_short
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readw(u_long addr)
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{
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return le16toh(*((u_short *)&PCI_mem[addr]));
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}
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u_long
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readl(u_long addr)
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{
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return le32toh(*((u_long *)&PCI_mem[addr]));
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}
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u_long
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local_to_PCI(u_long addr)
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{
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return (addr & 0x7FFFFFFF) | 0x80000000;
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}
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void
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_wbinv(uint32_t adr, uint32_t siz)
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{
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uint32_t bnd;
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asm volatile("eieio");
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for (bnd = adr + siz; adr < bnd; adr += dcache_line_size)
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asm volatile ("dcbf 0,%0" :: "r"(adr));
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asm volatile ("sync");
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}
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void
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_inv(uint32_t adr, uint32_t siz)
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{
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uint32_t bnd, off;
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off = adr & (dcache_line_size - 1);
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adr -= off;
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siz += off;
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asm volatile ("eieio");
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if (off != 0) {
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/* wbinv() leading unaligned dcache line */
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asm volatile ("dcbf 0,%0" :: "r"(adr));
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if (siz < dcache_line_size)
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goto done;
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adr += dcache_line_size;
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siz -= dcache_line_size;
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}
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bnd = adr + siz;
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off = bnd & (dcache_line_size - 1);
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if (off != 0) {
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/* wbinv() trailing unaligned dcache line */
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asm volatile ("dcbf 0,%0" :: "r"(bnd)); /* it's OK */
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if (siz < dcache_line_size)
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goto done;
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siz -= off;
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}
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for (bnd = adr + siz; adr < bnd; adr += dcache_line_size) {
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/* inv() intermediate dcache lines if ever */
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asm volatile ("dcbi 0,%0" :: "r"(adr));
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}
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done:
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asm volatile ("sync");
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}
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