97 lines
3.8 KiB
C
97 lines
3.8 KiB
C
/* $NetBSD: gtpcivar.h,v 1.6 2005/12/24 20:27:42 perry Exp $ */
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/*
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* Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Allegro Networks, Inc., and Wasabi Systems, Inc.
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* 4. The name of Allegro Networks, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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* 5. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
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* WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_MARVELL_GTPCIVAR_H
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#define _DEV_MARVELL_GTPCIVAR_H
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/*
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*/
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struct gtpci_chipset {
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struct pci_chipset gtpc_pc;
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int gtpc_busno;
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pcitag_t gtpc_self;
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bus_space_tag_t gtpc_io_bs;
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bus_space_tag_t gtpc_mem_bs;
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bus_space_tag_t gtpc_gt_memt;
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bus_space_handle_t gtpc_gt_memh;
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bus_size_t gtpc_cfgaddr;
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bus_size_t gtpc_cfgdata;
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bus_size_t gtpc_syncreg;
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boolean_t gtpc_host;
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};
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#ifdef _KERNEL
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static uint32_t inline
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gtpci_read(struct gtpci_chipset *gtpc, bus_size_t reg)
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{
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uint32_t rv;
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(void) bus_space_read_4(gtpc->gtpc_gt_memt, gtpc->gtpc_gt_memh,
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gtpc->gtpc_syncreg);
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rv = bus_space_read_4(gtpc->gtpc_gt_memt, gtpc->gtpc_gt_memh, reg);
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(void) bus_space_read_4(gtpc->gtpc_gt_memt, gtpc->gtpc_gt_memh,
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gtpc->gtpc_syncreg);
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return rv;
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}
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static void inline
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gtpci_write(struct gtpci_chipset *gtpc, bus_size_t reg, uint32_t val)
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{
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(void) bus_space_read_4(gtpc->gtpc_gt_memt, gtpc->gtpc_gt_memh,
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gtpc->gtpc_syncreg);
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bus_space_write_4(gtpc->gtpc_gt_memt, gtpc->gtpc_gt_memh, reg, val);
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(void) bus_space_read_4(gtpc->gtpc_gt_memt, gtpc->gtpc_gt_memh,
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gtpc->gtpc_syncreg);
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}
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void gtpci_bus_configure(struct gtpci_chipset *);
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pcitag_t gtpci_make_tag(pci_chipset_tag_t, int, int, int);
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void gtpci_decompose_tag(pci_chipset_tag_t, pcitag_t, int *, int *, int *);
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pcireg_t gtpci_conf_read(pci_chipset_tag_t, pcitag_t, int);
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void gtpci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t);
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void gtpci_md_bus_devorder(pci_chipset_tag_t, int, char []);
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int gtpci_md_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
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int gtpci_md_conf_hook(pci_chipset_tag_t, int, int, int, pcireg_t);
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void gtpci_md_conf_interrupt(pci_chipset_tag_t, int, int, int, int, int *);
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#endif /* _KERNEL */
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#endif /* _DEV_MARVELL_GTPCIVAR_H */
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