ca42af5e80
devices. Currently the serial ports and ethernet MAC have working drivers, and this has only been physically tested on the Au1000 CPU, but these devices should work on the Au1100 and Au1500 CPUs too.
147 lines
5.0 KiB
C
147 lines
5.0 KiB
C
/* $NetBSD: au_timer.c,v 1.1 2002/07/29 15:39:12 simonb Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Simon Burge for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <machine/bus.h>
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#include <mips/locore.h>
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#include <evbmips/evbmips/clockvar.h>
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#include <mips/alchemy/include/aureg.h>
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#include <mips/alchemy/include/auvar.h>
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/*
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* Set a programmable clock register.
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* If "wait" is non-zero, wait for that bit to become 0 in the
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* counter control register before and after writing to the
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* specified clock register.
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*/
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#define SET_PC_REG(reg, wait, val) \
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do { \
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if (wait) \
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while (bus_space_read_4(st, sh, PC_COUNTER_CONTROL) \
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& (wait)) \
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/* nothing */; \
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bus_space_write_4(st, sh, (reg), (val)); \
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if (wait) \
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while (bus_space_read_4(st, sh, (reg)) & (wait)) \
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/* nothing */; \
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} while (0)
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void
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au_cal_timers(bus_space_tag_t st, bus_space_handle_t sh)
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{
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uint32_t ctrdiff[4], startctr, endctr;
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uint32_t ctl, ctr, octr;
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int i;
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/* Enable the programmable counter 1. */
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ctl = bus_space_read_4(st, sh, PC_COUNTER_CONTROL);
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if ((ctl & (CC_EO | CC_EN1)) != (CC_EO | CC_EN1));
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SET_PC_REG(PC_COUNTER_CONTROL, 0, ctl | CC_EO | CC_EN1);
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/* Initialize for 16Hz. */
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SET_PC_REG(PC_TRIM1, CC_T1S, PC_RATE / 16 - 1);
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/* Run the loop an extra time to prime the cache. */
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for (i = 0; i < 4; i++) {
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/* Reset the counter. */
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SET_PC_REG(PC_COUNTER_WRITE1, CC_C1S, 0);
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/* Wait for 1/16th of a second. */
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//startctr = mips3_cp0_count_read();
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/* Wait for the PC to tick over. */
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ctr = bus_space_read_4(st, sh, PC_COUNTER_READ_1);
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do {
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octr = bus_space_read_4(st, sh, PC_COUNTER_READ_1);
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} while (ctr == octr);
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startctr = mips3_cp0_count_read();
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do {
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ctr = bus_space_read_4(st, sh, PC_COUNTER_READ_1);
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} while (ctr == octr); // while (ctr <= octr + 1);
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endctr = mips3_cp0_count_read();
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ctrdiff[i] = endctr - startctr;
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}
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/* Disable the counter (if it wasn't enabled already). */
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if ((ctl & (CC_EO | CC_EN1)) != (CC_EO | CC_EN1));
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SET_PC_REG(PC_COUNTER_CONTROL, 0, ctl);
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/* Compute the number of cycles per second. */
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curcpu()->ci_cpu_freq = ((ctrdiff[2] + ctrdiff[3]) / 2) * 16;
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/* Compute the number of ticks for hz. */
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curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz;
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/* Compute the delay divisor. */
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curcpu()->ci_divisor_delay =
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((curcpu()->ci_cpu_freq + 500000) / 1000000);
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/*
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* To implement a more accurate microtime using the CP0 COUNT
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* register we need to divide that register by the number of
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* cycles per MHz. But...
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*
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* DIV and DIVU are expensive on MIPS (eg 75 clocks on the
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* R4000). MULT and MULTU are only 12 clocks on the same CPU.
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* On the SB1 these appear to be 40-72 clocks for DIV/DIVU and 3
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* clocks for MUL/MULTU.
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*
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* The strategy we use to to calculate the reciprical of cycles
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* per MHz, scaled by 1<<32. Then we can simply issue a MULTU
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* and pluck of the HI register and have the results of the
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* division.
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*/
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curcpu()->ci_divisor_recip =
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0x100000000ULL / curcpu()->ci_divisor_delay;
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/*
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* Get correct cpu frequency if the CPU runs at twice the
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* external/cp0-count frequency.
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*/
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if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
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curcpu()->ci_cpu_freq *= 2;
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#ifdef DEBUG
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printf("Timer calibration: %lu cycles/sec [(%u, %u) * 16]\n",
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curcpu()->ci_cpu_freq, ctrdiff[2], ctrdiff[3]);
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#endif
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}
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