0823f75d49
StrongARM SA110 processor The DC21285 provides memory controller, timers, interrupt controller PCI-HOST bridge and diagnostic serial port.
91 lines
3.7 KiB
C
91 lines
3.7 KiB
C
/* $NetBSD: dc21285mem.h,v 1.1 1998/09/06 02:20:33 mark Exp $ */
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/*
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* Copyright (c) 1997,1998 Mark Brinicombe.
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* Copyright (c) 1997,1998 Causality Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe
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* for the NetBSD Project.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Physical memory map provided by the DC21285 'Footbridge'
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*/
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#define DC21285_SDRAM_BASE 0x00000000
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#define DC21285_SDRAM_SIZE 0x10000000 /* 256 MB */
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#define DC21285_SDRAM_A0MR 0x40000000
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#define DC21285_SDRAM_A1MR 0x40004000
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#define DC21285_SDRAM_A2MR 0x40008000
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#define DC21285_SDRAM_A3MR 0x4000C000
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#define DC21285_XBUS_XCS0 0x40010000
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#define DC21285_XBUS_XCS1 0x40011000
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#define DC21285_XBUS_XCS2 0x40012000
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#define DC21285_XBUS_NOCS 0x40013000
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#define DC21285_ROM_BASE 0x41000000
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#define DC21285_ROM_SIZE 0x01000000 /* 16MB */
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#define DC21285_ARMCSR_BASE 0x42000000
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#define DC21285_ARMCSR_SIZE 0x00100000 /* 1MB */
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#define DC28285_SA_CACHE_FLUSH_BASE 0x50000000
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#define DC21285_SA_CACHE_FLUSH_SIZE 0x01000000 /* 16MB */
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#define DC21285_OUTBOUND_WRITE_FLUSH 0x78000000
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#define DC21285_PCI_IACK_SPECIAL 0x79000000
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#define DC21285_PCI_TYPE_1_CONFIG 0x7A000000
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#define DC21285_PCI_TYPE_0_CONFIG 0x7B000000
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#define DC21285_PCI_IO_BASE 0x7C000000
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#define DC21285_PCI_IO_SIZE 0x00010000 /* 64K */
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#define DC21285_PCI_MEM_BASE 0x80000000
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#define DC21285_PCI_MEM_SIZE 0x80000000 /* 2GB */
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/*
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* Standard Virtual memory map used for the DC21285 'Footbridge'
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*/
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#define DC21285_ARMCSR_VBASE 0xF4000000
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#define DC21285_ARMCSR_VSIZE 0x00100000 /* 1MB */
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#define DC21285_CACHE_FLUSH_VBASE 0xF4100000
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#define DC21285_CACHE_FLUSH_VSIZE 0x00100000 /* 1MB */
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#define DC21285_PCI_IO_VBASE 0xF4200000
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#define DC21285_PCI_IO_VSIZE 0x00100000 /* 1MB */
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#define DC21285_PCI_IACK_VBASE 0xF4300000
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#define DC21285_PCI_IACK_VSIZE 0x00100000 /* 1MB */
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#define DC21285_PCI_TYPE_1_CONFIG_VBASE 0xF5000000
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#define DC21285_PCI_TYPE_1_CONFIG_VSIZE 0x01000000 /* 16MB */
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#define DC21285_PCI_TYPE_0_CONFIG_VBASE 0xF6000000
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#define DC21285_PCI_TYPE_0_CONFIG_VSIZE 0x01000000 /* 16MB */
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#define DC21285_PCI_MEM_VBASE 0xF7000000
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#define DC21285_PCI_MEM_VSIZE 0x09000000 /* 144MB */
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