281 lines
7.0 KiB
C
281 lines
7.0 KiB
C
/* $NetBSD: i2c_bitbang.c,v 1.14 2016/06/07 01:06:27 pgoyette Exp $ */
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/*
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* Copyright (c) 2003 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Common module for bit-bang'ing an I2C bus.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: i2c_bitbang.c,v 1.14 2016/06/07 01:06:27 pgoyette Exp $");
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#include <sys/module.h>
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#include <sys/param.h>
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#include <dev/i2c/i2cvar.h>
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#include <dev/i2c/i2c_bitbang.h>
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#define SETBITS(x) ops->ibo_set_bits(v, (x))
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#define DIR(x) ops->ibo_set_dir(v, (x))
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#define READ ops->ibo_read_bits(v)
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#define SDA ops->ibo_bits[I2C_BIT_SDA] /* i2c signal */
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#define SCL ops->ibo_bits[I2C_BIT_SCL] /* i2c signal */
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#define OUTPUT ops->ibo_bits[I2C_BIT_OUTPUT] /* SDA is output */
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#define INPUT ops->ibo_bits[I2C_BIT_INPUT] /* SDA is input */
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#ifndef SCL_BAIL_COUNT
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#define SCL_BAIL_COUNT 1000
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#endif
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static inline int i2c_wait_for_scl(void *, i2c_bitbang_ops_t);
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static inline int
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i2c_wait_for_scl(void *v, i2c_bitbang_ops_t ops)
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{
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int bail = 0;
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while (((READ & SCL) == 0) && (bail < SCL_BAIL_COUNT)) {
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delay(1);
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bail++;
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}
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if (bail == SCL_BAIL_COUNT) {
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i2c_bitbang_send_stop(v, 0, ops);
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return EIO;
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}
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return 0;
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}
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/*ARGSUSED*/
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int
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i2c_bitbang_send_start(void *v, int flags, i2c_bitbang_ops_t ops)
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{
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/* start condition: put SDA H->L edge during SCL=H */
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DIR(OUTPUT);
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SETBITS(SDA | SCL);
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delay(5); /* bus free time (4.7 us) */
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SETBITS( 0 | SCL);
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if (i2c_wait_for_scl(v, ops) != 0)
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return EIO;
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delay(4); /* start hold time (4.0 us) */
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/* leave SCL=L and SDA=L to avoid unexpected start/stop condition */
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SETBITS( 0 | 0);
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return 0;
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}
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/*ARGSUSED*/
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int
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i2c_bitbang_send_stop(void *v, int flags, i2c_bitbang_ops_t ops)
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{
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/* stop condition: put SDA L->H edge during SCL=H */
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/* assume SCL=L, SDA=L here */
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DIR(OUTPUT);
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SETBITS( 0 | SCL);
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delay(4); /* stop setup time (4.0 us) */
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SETBITS(SDA | SCL);
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return 0;
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}
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int
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i2c_bitbang_initiate_xfer(void *v, i2c_addr_t addr, int flags,
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i2c_bitbang_ops_t ops)
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{
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if (addr < 0x80) {
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uint8_t i2caddr;
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/* disallow the 10-bit address prefix */
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if ((addr & 0x78) == 0x78)
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return EINVAL;
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i2caddr = (addr << 1) | ((flags & I2C_F_READ) ? 1 : 0);
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(void) i2c_bitbang_send_start(v, flags, ops);
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return (i2c_bitbang_write_byte(v, i2caddr,
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flags & ~I2C_F_STOP, ops));
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} else if (addr < 0x400) {
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uint16_t i2caddr;
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int rv;
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i2caddr = (addr << 1) | ((flags & I2C_F_READ) ? 1 : 0) |
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0xf000;
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(void) i2c_bitbang_send_start(v, flags, ops);
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rv = i2c_bitbang_write_byte(v, i2caddr >> 8,
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flags & ~I2C_F_STOP, ops);
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/* did a slave ack the 10-bit prefix? */
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if (rv != 0)
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return rv;
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/* send the lower 7-bits (+ read/write mode) */
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return (i2c_bitbang_write_byte(v, i2caddr & 0xff,
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flags & ~I2C_F_STOP, ops));
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} else
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return EINVAL;
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}
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int
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i2c_bitbang_read_byte(void *v, uint8_t *valp, int flags, i2c_bitbang_ops_t ops)
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{
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int i;
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uint8_t val = 0;
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uint32_t bit;
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/* assume SCL=L, SDA=L here */
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DIR(INPUT);
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for (i = 0; i < 8; i++) {
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val <<= 1;
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/* data is set at SCL H->L edge */
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/* SDA is set here because DIR() is INPUT */
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SETBITS(SDA | 0);
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delay(5); /* clock low time (4.7 us) */
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/* read data at SCL L->H edge */
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SETBITS(SDA | SCL);
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if (i2c_wait_for_scl(v, ops) != 0)
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return EIO;
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if (READ & SDA)
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val |= 1;
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delay(4); /* clock high time (4.0 us) */
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}
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/* set SCL H->L before set SDA direction OUTPUT */
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SETBITS(SDA | 0);
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/* set ack after SCL H->L edge */
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bit = (flags & I2C_F_LAST) ? SDA : 0;
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DIR(OUTPUT);
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SETBITS(bit | 0);
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delay(5); /* clock low time (4.7 us) */
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/* ack is checked at SCL L->H edge */
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SETBITS(bit | SCL);
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if (i2c_wait_for_scl(v, ops) != 0)
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return EIO;
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delay(4); /* clock high time (4.0 us) */
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/* set SCL H->L for next data; don't change SDA here */
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SETBITS(bit | 0);
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/* leave SCL=L and SDA=L to avoid unexpected start/stop condition */
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SETBITS( 0 | 0);
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if ((flags & (I2C_F_STOP | I2C_F_LAST)) == (I2C_F_STOP | I2C_F_LAST))
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(void) i2c_bitbang_send_stop(v, flags, ops);
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*valp = val;
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return 0;
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}
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int
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i2c_bitbang_write_byte(void *v, uint8_t val, int flags, i2c_bitbang_ops_t ops)
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{
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uint32_t bit;
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uint8_t mask;
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int error;
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/* assume at SCL=L, SDA=L here */
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DIR(OUTPUT);
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for (mask = 0x80; mask != 0; mask >>= 1) {
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bit = (val & mask) ? SDA : 0;
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/* set data after SCL H->L edge */
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SETBITS(bit | 0);
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delay(5); /* clock low time (4.7 us) */
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/* data is fetched at SCL L->H edge */
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SETBITS(bit | SCL);
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if (i2c_wait_for_scl(v, ops))
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return EIO;
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delay(4); /* clock high time (4.0 us) */
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/* put SCL H->L edge; don't change SDA here */
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SETBITS(bit | 0);
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}
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/* ack is set at H->L edge */
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DIR(INPUT);
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delay(5); /* clock low time (4.7 us) */
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/* read ack at L->H edge */
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/* SDA is set here because DIR() is INPUT */
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SETBITS(SDA | SCL);
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if (i2c_wait_for_scl(v, ops) != 0)
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return EIO;
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error = (READ & SDA) ? EIO : 0;
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delay(4); /* clock high time (4.0 us) */
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/* set SCL H->L before set SDA direction OUTPUT */
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SETBITS(SDA | 0);
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DIR(OUTPUT);
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/* leave SCL=L and SDA=L to avoid unexpected start/stop condition */
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SETBITS( 0 | 0);
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if (flags & I2C_F_STOP)
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(void) i2c_bitbang_send_stop(v, flags, ops);
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return error;
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}
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MODULE(MODULE_CLASS_MISC, i2c_bitbang, NULL);
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static int
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i2c_bitbang_modcmd(modcmd_t cmd, void *opaque)
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{
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switch (cmd) {
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case MODULE_CMD_INIT:
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return 0;
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case MODULE_CMD_FINI:
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return 0;
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default:
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return ENOTTY;
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}
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}
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