347 lines
9.9 KiB
C
347 lines
9.9 KiB
C
/* $NetBSD: rmixl_obio.c,v 1.5 2011/07/10 23:13:22 matt Exp $ */
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/*
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* Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* On-board device autoconfiguration support for RMI {XLP, XLR, XLS} chips
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rmixl_obio.c,v 1.5 2011/07/10 23:13:22 matt Exp $");
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#include "locators.h"
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#include "pci.h"
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#define _MIPS_BUS_DMA_PRIVATE
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/extent.h>
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#include <sys/malloc.h>
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#include <sys/systm.h>
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#include <mips/int_fmtio.h>
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#include <mips/rmi/rmixlreg.h>
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#include <mips/rmi/rmixlvar.h>
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#include <mips/rmi/rmixl_intr.h>
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#include <mips/rmi/rmixl_obiovar.h>
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#include <mips/rmi/rmixl_pcievar.h>
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#include <evbmips/rmixl/autoconf.h>
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#ifdef OBIO_DEBUG
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int obio_rmixl_debug = OBIO_DEBUG;
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# define DPRINTF(x) do { if (obio_rmixl_debug) printf x ; } while (0)
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#else
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# define DPRINTF(x)
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#endif
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static int obio_match(device_t, cfdata_t, void *);
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static void obio_attach(device_t, device_t, void *);
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static int obio_print(void *, const char *);
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static int obio_search(device_t, cfdata_t, const int *, void *);
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static void obio_bus_init(struct obio_softc *);
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static void obio_dma_init_64(bus_dma_tag_t);
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static int rmixl_addr_error_intr(void *);
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CFATTACH_DECL_NEW(obio_rmixl, sizeof(struct obio_softc),
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obio_match, obio_attach, NULL, NULL);
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int obio_found;
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static int
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obio_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct mainbus_attach_args *aa = aux;
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if (obio_found == 0)
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if (strncmp(aa->ma_name, cf->cf_name, strlen(cf->cf_name)) == 0)
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return 1;
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return 0;
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}
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static void
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obio_attach(device_t parent, device_t self, void *aux)
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{
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struct obio_softc *sc = device_private(self);
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bus_addr_t ba;
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obio_found = 1;
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sc->sc_dev = self;
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ba = (bus_addr_t)rmixl_configuration.rc_io_pbase;
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KASSERT(ba != 0);
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obio_bus_init(sc);
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aprint_normal(" addr %#"PRIxBUSADDR" size %#"PRIxBUSSIZE"\n",
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ba, (bus_size_t)RMIXL_IO_DEV_SIZE);
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aprint_naive("\n");
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/*
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* Attach on-board devices as specified in the kernel config file.
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*/
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config_search_ia(obio_search, self, "obio", NULL);
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}
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static int
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obio_print(void *aux, const char *pnp)
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{
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struct obio_attach_args *obio = aux;
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if (obio->obio_addr != OBIOCF_ADDR_DEFAULT) {
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aprint_normal(" addr %#"PRIxBUSADDR, obio->obio_addr);
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if (obio->obio_size != OBIOCF_SIZE_DEFAULT)
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aprint_normal("-%#"PRIxBUSADDR,
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obio->obio_addr + (obio->obio_size - 1));
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}
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if (obio->obio_mult != OBIOCF_MULT_DEFAULT)
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aprint_normal(" mult %d", obio->obio_mult);
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if (obio->obio_intr != OBIOCF_INTR_DEFAULT)
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aprint_normal(" intr %d", obio->obio_intr);
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if (obio->obio_tmsk != OBIOCF_TMSK_DEFAULT)
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aprint_normal(" tmsk %d", obio->obio_tmsk);
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return (UNCONF);
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}
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static int
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obio_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
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{
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struct obio_softc *sc = device_private(parent);
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struct obio_attach_args obio;
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obio.obio_eb_bst = sc->sc_eb_bst;
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obio.obio_el_bst = sc->sc_el_bst;
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obio.obio_addr = cf->cf_loc[OBIOCF_ADDR];
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obio.obio_size = cf->cf_loc[OBIOCF_SIZE];
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obio.obio_mult = cf->cf_loc[OBIOCF_MULT];
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obio.obio_intr = cf->cf_loc[OBIOCF_INTR];
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obio.obio_tmsk = cf->cf_loc[OBIOCF_TMSK];
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obio.obio_29bit_dmat = sc->sc_29bit_dmat;
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obio.obio_32bit_dmat = sc->sc_32bit_dmat;
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obio.obio_64bit_dmat = sc->sc_64bit_dmat;
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if (config_match(parent, cf, &obio) > 0)
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config_attach(parent, cf, &obio, obio_print);
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return 0;
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}
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static void
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obio_bus_init(struct obio_softc *sc)
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{
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struct rmixl_config *rcp = &rmixl_configuration;
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static int done = 0;
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int error;
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if (done)
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return;
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done = 1;
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/* obio (devio) space, Big Endian */
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if (rcp->rc_obio_eb_memt.bs_cookie == 0)
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rmixl_obio_eb_bus_mem_init(&rcp->rc_obio_eb_memt, rcp);
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/* obio (devio) space, Little Endian */
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if (rcp->rc_obio_el_memt.bs_cookie == 0)
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rmixl_obio_el_bus_mem_init(&rcp->rc_obio_el_memt, rcp);
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/* dma space for all memory, including >= 4GB */
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if (rcp->rc_dma_tag._cookie == 0)
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obio_dma_init_64(&rcp->rc_dma_tag);
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rcp->rc_64bit_dmat = &rcp->rc_dma_tag;
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/* dma space for addr < 4GB */
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if (rcp->rc_32bit_dmat == NULL) {
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error = bus_dmatag_subregion(rcp->rc_64bit_dmat,
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0, (bus_addr_t)1 << 32, &rcp->rc_32bit_dmat, 0);
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if (error)
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panic("%s: failed to create 32bit dma tag: %d",
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__func__, error);
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}
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/* dma space for addr < 512MB */
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if (rcp->rc_29bit_dmat == NULL) {
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error = bus_dmatag_subregion(rcp->rc_32bit_dmat,
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0, (bus_addr_t)1 << 29, &rcp->rc_29bit_dmat, 0);
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if (error)
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panic("%s: failed to create 29bit dma tag: %d",
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__func__, error);
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}
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sc->sc_base = (bus_addr_t)rcp->rc_io_pbase;
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sc->sc_size = (bus_size_t)RMIXL_IO_DEV_SIZE;
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sc->sc_eb_bst = (bus_space_tag_t)&rcp->rc_obio_eb_memt;
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sc->sc_el_bst = (bus_space_tag_t)&rcp->rc_obio_el_memt;
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sc->sc_29bit_dmat = rcp->rc_29bit_dmat;
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sc->sc_32bit_dmat = rcp->rc_32bit_dmat;
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sc->sc_64bit_dmat = rcp->rc_64bit_dmat;
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}
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static void
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obio_dma_init_64(bus_dma_tag_t t)
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{
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t->_cookie = t;
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t->_wbase = 0;
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t->_bounce_alloc_lo = 0;
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t->_bounce_alloc_hi = 0;
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t->_dmamap_ops = mips_bus_dmamap_ops;
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t->_dmamem_ops = mips_bus_dmamem_ops;
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t->_dmatag_ops = mips_bus_dmatag_ops;
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}
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void
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rmixl_addr_error_init(void)
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{
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uint32_t r;
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/*
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* activate error addr detection on all (configurable) devices
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* preserve reserved bit fields
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* note some of these bits are read-only (writes are ignored)
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*/
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r = RMIXL_IOREG_READ(RMIXL_ADDR_ERR_DEVICE_MASK);
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r |= ~(__BITS(19,16) | __BITS(10,9) | __BITS(7,5));
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RMIXL_IOREG_WRITE(RMIXL_ADDR_ERR_DEVICE_MASK, r);
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/*
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* enable the address error interrupts
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* "upgrade" cache and CPU errors to A1
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*/
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#define _ADDR_ERR_DEVSTAT_A1 (__BIT(8) | __BIT(1) | __BIT(0))
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#define _ADDR_ERR_RESV \
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(__BITS(31,21) | __BITS(15,14) | __BITS(10,9) | __BITS(7,2))
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#define _BITERR_INT_EN_RESV (__BITS(31,8) | __BIT(4))
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r = RMIXL_IOREG_READ(RMIXL_ADDR_ERR_AERR0_EN);
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r &= _ADDR_ERR_RESV;
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r |= ~_ADDR_ERR_RESV;
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RMIXL_IOREG_WRITE(RMIXL_ADDR_ERR_AERR0_EN, r);
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r = RMIXL_IOREG_READ(RMIXL_ADDR_ERR_AERR0_UPG);
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r &= _ADDR_ERR_RESV;
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r |= _ADDR_ERR_DEVSTAT_A1;
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RMIXL_IOREG_WRITE(RMIXL_ADDR_ERR_AERR0_UPG, r);
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/*
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* clear the log regs and the dev stat (interrupt status) regs
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* "Write any value to bit[0] to clear"
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*/
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r = RMIXL_IOREG_READ(RMIXL_ADDR_ERR_AERR1_CLEAR);
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RMIXL_IOREG_WRITE(RMIXL_ADDR_ERR_AERR1_CLEAR, r);
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/*
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* enable the double bit error interrupts
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* (assume reserved bits, which are read-only, are ignored)
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*/
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r = RMIXL_IOREG_READ(RMIXL_ADDR_ERR_BITERR_INT_EN);
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r &= _BITERR_INT_EN_RESV;
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r |= __BITS(7,5);
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RMIXL_IOREG_WRITE(RMIXL_ADDR_ERR_BITERR_INT_EN, r);
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/*
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* establish address error ISR
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* XXX assuming "int 16 (bridge_tb)" is our irq
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* XXX is true for XLS family only
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*/
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if (cpu_rmixls(mips_options.mips_cpu))
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rmixl_intr_establish(16, 1, IPL_HIGH,
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RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH,
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rmixl_addr_error_intr, NULL, false);
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}
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int
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rmixl_addr_error_check(void)
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{
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uint32_t aerr0_devstat;
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uint32_t aerr0_log1;
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uint32_t aerr0_log2;
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uint32_t aerr0_log3;
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uint32_t aerr1_devstat;
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uint32_t aerr1_log1;
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uint32_t aerr1_log2;
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uint32_t aerr1_log3;
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uint32_t sbe_counts;
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uint32_t dbe_counts;
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aerr0_devstat = RMIXL_IOREG_READ(RMIXL_ADDR_ERR_AERR0_DEVSTAT);
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aerr0_log1 = RMIXL_IOREG_READ(RMIXL_ADDR_ERR_AERR0_LOG1);
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aerr0_log2 = RMIXL_IOREG_READ(RMIXL_ADDR_ERR_AERR0_LOG2);
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aerr0_log3 = RMIXL_IOREG_READ(RMIXL_ADDR_ERR_AERR0_LOG3);
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aerr1_devstat = RMIXL_IOREG_READ(RMIXL_ADDR_ERR_AERR1_DEVSTAT);
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aerr1_log1 = RMIXL_IOREG_READ(RMIXL_ADDR_ERR_AERR1_LOG1);
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aerr1_log2 = RMIXL_IOREG_READ(RMIXL_ADDR_ERR_AERR1_LOG2);
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aerr1_log3 = RMIXL_IOREG_READ(RMIXL_ADDR_ERR_AERR1_LOG3);
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sbe_counts = RMIXL_IOREG_READ(RMIXL_ADDR_ERR_SBE_COUNTS);
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dbe_counts = RMIXL_IOREG_READ(RMIXL_ADDR_ERR_DBE_COUNTS);
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if (aerr0_log1|aerr0_log2|aerr0_log3
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|aerr1_log1|aerr1_log2|aerr1_log3
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|dbe_counts) {
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printf("aerr0: stat %#x, logs: %#x, %#x, %#x\n",
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aerr0_devstat, aerr0_log1, aerr0_log2, aerr0_log2);
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printf("aerr1: stat %#x, logs: %#x, %#x, %#x\n",
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aerr1_devstat, aerr1_log1, aerr1_log2, aerr1_log2);
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printf("1-bit errors: %#x, 2-bit errors: %#x\n",
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sbe_counts, dbe_counts);
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return 1;
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}
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return 0;
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}
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static int
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rmixl_addr_error_intr(void *arg)
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{
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int err;
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err = rmixl_addr_error_check();
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if (err != 0) {
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#if DDB
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printf("%s\n", __func__);
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Debugger();
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#endif
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panic("Address Error");
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}
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return 1;
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}
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