236 lines
5.5 KiB
C
236 lines
5.5 KiB
C
/* $NetBSD: svreg.h,v 1.4 2005/12/11 12:22:50 christos Exp $ */
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/*
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* Copyright (c) 1998 Constantine Paul Sapuntzakis
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* All rights reserved
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*
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* Author: Constantine Paul Sapuntzakis (csapuntz@cvs.openbsd.org)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The author's name or those of the contributors may be used to
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* endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR(S) AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* PCI BIOS Configuration area ports
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*/
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enum {
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SV_SB_PORTBASE_SLOT = 0x10,
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SV_ENHANCED_PORTBASE_SLOT = 0x14,
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SV_FM_PORTBASE_SLOT = 0x18,
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SV_MIDI_PORTBASE_SLOT = 0x1c,
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SV_GAME_PORTBASE_SLOT = 0x20
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};
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/*
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* Enhanced CODEC registers
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* These are offset from the base specified in the PCI configuration area
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*/
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enum {
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SV_CODEC_CONTROL = 0,
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SV_CODEC_INTMASK = 1,
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SV_CODEC_STATUS = 2,
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SV_CODEC_IADDR = 4,
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SV_CODEC_IDATA = 5
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};
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/*
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* DMA Configuration register
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*/
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enum {
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SV_DMAA_CONFIG_OFF = 0x40,
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SV_DMAC_CONFIG_OFF = 0x48
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};
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#define SV_DMAA_SIZE 0x10
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#define SV_DMAA_ALIGN 0x10
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#define SV_DMAC_SIZE 0x10
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#define SV_DMAC_ALIGN 0x10
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enum {
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SV_DMA_CHANNEL_ENABLE = 0x1,
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SV_DMAA_EXTENDED_ADDR = 0x8,
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SV_DMA_PORTBASE_MASK = 0xFFFFFFF0
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};
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enum {
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SV_DMA_ADDR0 = 0,
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SV_DMA_ADDR1 = 1,
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SV_DMA_ADDR2 = 2,
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SV_DMA_ADDR3 = 3,
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SV_DMA_COUNT0 = 4,
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SV_DMA_COUNT1 = 5,
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SV_DMA_COUNT2 = 6,
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SV_DMA_CMDSTATUS = 8,
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SV_DMA_MODE = 0xB,
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SV_DMA_MASTERCLEAR = 0xD,
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SV_DMA_MASK = 0xF
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};
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/*
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* DMA Mode (see reg 0xB)
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*/
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enum {
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SV_DMA_MODE_IOR_MASK = 0x0C,
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SV_DMA_MODE_IOW_MASK = 0x0C,
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SV_DMA_MODE_IOR = 0x04,
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SV_DMA_MODE_IOW = 0x08,
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SV_DMA_MODE_AUTOINIT = 0x10
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};
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enum {
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SV_CTL_ENHANCED = 0x01,
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SV_CTL_MD1 = 0x04,
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SV_CTL_FWS = 0x08,
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SV_CTL_INTA = 0x20,
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SV_CTL_RESET = 0x80
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};
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enum {
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SV_INTMASK_DMAA = 0x1,
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SV_INTMASK_DMAC = 0x4,
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SV_INTMASK_SINT = 0x8,
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SV_INTMASK_UD = 0x40,
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SV_INTMASK_MIDI = 0x80
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};
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enum {
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SV_INTSTATUS_DMAA = 0x1,
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SV_INTSTATUS_DMAC = 0x4,
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SV_INTSTATUS_SINT = 0x8,
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SV_INTSTATUS_UD = 0x40,
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SV_INTSTATUS_MIDI = 0x80
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};
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enum {
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SV_IADDR_MASK = 0x3f,
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SV_IADDR_MCE = 0x40,
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/* TRD = DMA Transfer request disable */
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SV_IADDR_TRD = 0x80
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};
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enum {
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SV_LEFT_ADC_INPUT_CONTROL = 0x0,
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SV_RIGHT_ADC_INPUT_CONTROL = 0x1,
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SV_LEFT_AUX1_INPUT_CONTROL = 0x2,
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SV_RIGHT_AUX1_INPUT_CONTROL = 0x3,
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SV_LEFT_CD_INPUT_CONTROL = 0x4,
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SV_RIGHT_CD_INPUT_CONTROL = 0x5,
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SV_LEFT_LINE_IN_INPUT_CONTROL = 0x6,
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SV_RIGHT_LINE_IN_INPUT_CONTROL = 0x7,
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SV_MIC_INPUT_CONTROL = 0x8,
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SV_GAME_PORT_CONTROL = 0x9,
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SV_LEFT_SYNTH_INPUT_CONTROL = 0x0A,
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SV_RIGHT_SYNTH_INPUT_CONTROL = 0x0B,
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SV_LEFT_AUX2_INPUT_CONTROL = 0x0C,
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SV_RIGHT_AUX2_INPUT_CONTROL = 0x0D,
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SV_LEFT_MIXER_OUTPUT_CONTROL = 0x0E,
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SV_RIGHT_MIXER_OUTPUT_CONTROL = 0x0F,
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SV_LEFT_PCM_INPUT_CONTROL = 0x10,
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SV_RIGHT_PCM_INPUT_CONTROL = 0x11,
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SV_DMA_DATA_FORMAT = 0x12,
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SV_PLAY_RECORD_ENABLE = 0x13,
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SV_UP_DOWN_CONTROL = 0x14,
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SV_REVISION_LEVEL = 0x15,
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SV_MONITOR_CONTROL = 0x16,
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SV_DMAA_COUNT1 = 0x18,
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SV_DMAA_COUNT0 = 0x19,
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SV_DMAC_COUNT1 = 0x1C,
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SV_DMAC_COUNT0 = 0x1d,
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SV_PCM_SAMPLE_RATE_0 = 0x1e,
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SV_PCM_SAMPLE_RATE_1 = 0x1f,
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SV_SYNTH_SAMPLE_RATE_0 = 0x20,
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SV_SYNTH_SAMPLE_RATE_1 = 0x21,
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SV_ADC_CLOCK_SOURCE = 0x22,
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SV_ADC_ALT_SAMPLE_RATE = 0x23,
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SV_ADC_PLL_M = 0x24,
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SV_ADC_PLL_N = 0x25,
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SV_SYNTH_PLL_M = 0x26,
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SV_SYNTH_PLL_N = 0x27,
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SV_MPU401 = 0x2A,
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SV_DRIVE_CONTROL = 0x2B,
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SV_SRS_SPACE_CONTROL = 0x2c,
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SV_SRS_CENTER_CONTROL = 0x2d,
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SV_WAVETABLE_SOURCE_SELECT = 0x2e,
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SV_ANALOG_POWER_DOWN_CONTROL = 0x30,
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SV_DIGITAL_POWER_DOWN_CONTROL = 0x31
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};
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enum {
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SV_MUTE_BIT = 0x80,
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SV_AUX1_MASK = 0x1F,
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SV_CD_MASK = 0x1F,
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SV_LINE_IN_MASK = 0x1F,
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SV_MIC_MASK = 0x0F,
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SV_SYNTH_MASK = 0x1F,
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SV_AUX2_MASK = 0x1F,
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SV_MIXER_OUT_MASK = 0x1F,
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SV_PCM_MASK = 0x3F
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};
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enum {
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SV_DMAA_STEREO = 0x1,
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SV_DMAA_FORMAT16 = 0x2,
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SV_DMAC_STEREO = 0x10,
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SV_DMAC_FORMAT16 = 0x20
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};
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enum {
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SV_PLAY_ENABLE = 0x1,
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SV_RECORD_ENABLE = 0x2
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};
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enum {
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SV_PLL_R_SHIFT = 5
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};
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/* ADC input source (registers 0 & 1) */
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enum {
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SV_REC_SOURCE_MASK = 0xE0,
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SV_REC_SOURCE_SHIFT = 5,
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SV_MIC_BOOST_BIT = 0x10,
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SV_REC_GAIN_MASK = 0x0F,
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SV_REC_CD = 1,
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SV_REC_DAC = 2,
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SV_REC_AUX2 = 3,
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SV_REC_LINE = 4,
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SV_REC_AUX1 = 5,
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SV_REC_MIC = 6,
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SV_REC_MIXER = 7
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};
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/* SRS Space control register (reg 0x2C) */
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enum {
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SV_SRS_SPACE_ONOFF = 0x80
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};
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enum {
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SV_WSS_WT0 = 0x01,
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SV_WSS_WT1 = 0x02,
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};
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