154 lines
6.0 KiB
C
154 lines
6.0 KiB
C
/* $NetBSD: spiflash.h,v 1.4 2009/05/12 14:45:08 cegger Exp $ */
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/*-
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* Copyright (c) 2006 Urbana-Champaign Independent Media Center.
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* Copyright (c) 2006 Garrett D'Amore.
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* All rights reserved.
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*
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* Portions of this code were written by Garrett D'Amore for the
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* Champaign-Urbana Community Wireless Network Project.
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* 3. All advertising materials mentioning features or use of this
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* software must display the following acknowledgements:
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* This product includes software developed by the Urbana-Champaign
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* Independent Media Center.
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* This product includes software developed by Garrett D'Amore.
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* 4. Urbana-Champaign Independent Media Center's name and Garrett
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* D'Amore's name may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT
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* MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT
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* MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_SPI_SPIFLASH_H_
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#define _DEV_SPI_SPIFLASH_H_
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#define SPIFLASH_CMD_RDSR 0x05 /* read status register */
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#define SPIFLASH_CMD_WRSR 0x01 /* write status register */
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#define SPIFLASH_CMD_WREN 0x06 /* enable WRSR */
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#define SPIFLASH_CMD_WRDI 0x04 /* disable WRSR */
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/*
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* Different chips offer different ways to read a device ID, although
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* newer parts should all offer the standard JEDEC variant.
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* Additionally, many parts have a faster read, though how to make use
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* of this sometimes requires special hacks. E.g. some parts use an
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* extra data pin, and some crank the clock rate up.
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*/
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#define SPIFLASH_CMD_READ 0x03 /* read data (normal) */
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#define SPIFLASH_CMD_RDID 0xab /* read id */
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#define SPIFLASH_CMD_RDID2 0x90 /* read id (alternate) */
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#define SPIFLASH_CMD_RDJI 0x9f /* read JEDEC id */
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#define SPIFLASH_CMD_READFAST 0x0b /* fast read */
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/*
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* Different chips offer different variations on the sector erase.
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* E.g. SST parts offer 4k, 32k, and 64k erase sizes on the same part,
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* with just different cmds. However, at least SST, AMD, and Winbond
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* all offer at least the main (0xd8) variant.
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*/
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#define SPIFLASH_CMD_ERASE 0xd8 /* sector erase */
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#define SPIFLASH_CMD_ERASE2 0x52 /* sector erase (alternate) */
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#define SPIFLASH_CMD_ERASE3 0x20 /* sector erase (alternate) */
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#define SPIFLASH_CMD_ERASE4 0x81 /* page erase */
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#define SPIFLASH_CMD_CHIPERASE 0xc7 /* chip erase */
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/*
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* Some parts can stream bytes with the program command, whereas others require
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* a separate command sequence for each byte.
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*/
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#define SPIFLASH_CMD_PROGRAM 0x02 /* page or byte program */
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#define SPIFLASH_CMD_PROGRAM_AA 0xad /* program (autoincrement) */
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/*
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* Some additional commands. Again, mostly device specific.
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*/
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#define SPIFLASH_CMD_EBSY 0x70 /* output busy signal (SST) */
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#define SPIFLASH_CMD_DBSY 0x80 /* disable busy signal (SST) */
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/*
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* Status register bits. Not all devices implement all bits. In
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* addition, the meanings of the BP bits seem to vary from device to
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* device.
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*/
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#define SPIFLASH_SR_BUSY 0x01 /* program in progress */
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#define SPIFLASH_SR_WEL 0x02 /* write enable latch */
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#define SPIFLASH_SR_BP0 0x04 /* block protect bits */
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#define SPIFLASH_SR_BP1 0x08
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#define SPIFLASH_SR_BP2 0x10
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#define SPIFLASH_SR_BP3 0x20
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#define SPIFLASH_SR_AAI 0x40 /* auto-increment mode */
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#define SPIFLASH_SR_SRP 0x80 /* SR write protected */
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/*
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* This needs to change to accommodate boot-sectored devices.
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*/
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typedef struct spiflash_softc *spiflash_handle_t;
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struct spiflash_hw_if {
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/*
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* Driver MUST provide these.
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*/
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const char *(*sf_getname)(void *);
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struct spi_handle *(*sf_gethandle)(void *);
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int (*sf_getflags)(void *);
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int (*sf_getsize)(void *, int);
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/*
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* SPI framework will provide these if the driver does not.
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*/
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int (*sf_erase)(spiflash_handle_t, size_t, size_t);
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int (*sf_write)(spiflash_handle_t, size_t, size_t,
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const uint8_t *);
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int (*sf_read)(spiflash_handle_t, size_t, size_t, uint8_t *);
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/*
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* Not implemented yet.
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*/
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int (*sf_getstatus)(spiflash_handle_t, int, int);
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int (*sf_setstatus)(spiflash_handle_t, int, int, int);
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};
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#define SPIFLASH_SIZE_DEVICE 0
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#define SPIFLASH_SIZE_ERASE 1
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#define SPIFLASH_SIZE_WRITE 2 /* return -1 for unlimited */
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#define SPIFLASH_SIZE_READ 3 /* return -1 for unlimited */
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#define SPIFLASH_SIZE_COUNT 4
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#define SPIFLASH_FLAG_FAST_READ 0x0004 /* use fast read sequence */
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spiflash_handle_t spiflash_attach_mi(const struct spiflash_hw_if *, void *,
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device_t);
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void spiflash_set_private(spiflash_handle_t, void *);
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void *spiflash_get_private(spiflash_handle_t);
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int spiflash_read_status(spiflash_handle_t, uint8_t *);
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int spiflash_write_disable(spiflash_handle_t);
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int spiflash_write_enable(spiflash_handle_t);
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int spiflash_cmd(spiflash_handle_t, uint8_t, size_t, uint32_t, size_t,
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const uint8_t *, uint8_t *);
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int spiflash_wait(spiflash_handle_t, int);
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#endif /* _DEV_SPI_SPIFLASH_H_ */
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