291 lines
7.5 KiB
C
291 lines
7.5 KiB
C
/* $NetBSD: cpu.h,v 1.21 2002/09/26 01:13:32 matt Exp $ */
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/*
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* Copyright (C) 1999 Wolfgang Solfrank.
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* Copyright (C) 1999 TooLs GmbH.
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* Copyright (C) 1995-1997 Wolfgang Solfrank.
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* Copyright (C) 1995-1997 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _POWERPC_CPU_H_
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#define _POWERPC_CPU_H_
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#if defined(_KERNEL_OPT)
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#include "opt_lockdebug.h"
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#include "opt_multiprocessor.h"
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#include "opt_ppcarch.h"
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#endif
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#include <machine/frame.h>
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#include <machine/psl.h>
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#include <machine/intr.h>
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#include <sys/device.h>
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struct cache_info {
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int dcache_size;
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int dcache_line_size;
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int icache_size;
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int icache_line_size;
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};
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#ifdef _KERNEL
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#include <sys/sched.h>
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#include <dev/sysmon/sysmonvar.h>
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struct cpu_info {
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struct schedstate_percpu ci_schedstate; /* scheduler state */
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#if defined(DIAGNOSTIC) || defined(LOCKDEBUG)
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u_long ci_spin_locks; /* # of spin locks held */
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u_long ci_simple_locks; /* # of simple locks held */
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#endif
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struct device *ci_dev; /* device of corresponding cpu */
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struct proc *ci_curproc; /* current owner of the processor */
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struct pcb *ci_curpcb;
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struct pmap *ci_curpm;
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struct proc *ci_fpuproc;
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struct proc *ci_vecproc;
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struct pcb *ci_idle_pcb; /* PA of our idle pcb */
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int ci_cpuid;
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int ci_astpending;
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int ci_want_resched;
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u_long ci_lasttb;
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int ci_tickspending;
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int ci_cpl;
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int ci_ipending;
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int ci_intrdepth;
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char *ci_intstk;
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char *ci_spillstk;
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int ci_tempsave[8];
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int ci_ddbsave[8];
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int ci_ipkdbsave[8];
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int ci_disisave[4];
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struct cache_info ci_ci;
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struct sysmon_envsys ci_sysmon;
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struct envsys_tre_data ci_tau_info;
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struct evcnt ci_ev_traps; /* calls to trap() */
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struct evcnt ci_ev_kdsi; /* kernel DSI traps */
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struct evcnt ci_ev_udsi; /* user DSI traps */
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struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */
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struct evcnt ci_ev_isi; /* user ISI traps */
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struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */
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struct evcnt ci_ev_pgm; /* user PGM traps */
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struct evcnt ci_ev_fpu; /* FPU traps */
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struct evcnt ci_ev_fpusw; /* FPU context switch */
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struct evcnt ci_ev_ali; /* Alignment traps */
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struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */
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struct evcnt ci_ev_scalls; /* system call traps */
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struct evcnt ci_ev_vec; /* Altivec traps */
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struct evcnt ci_ev_vecsw; /* Altivec context switches */
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struct evcnt ci_ev_umchk; /* user MCHK events */
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};
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#ifdef MULTIPROCESSOR
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static __inline int
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cpu_number(void)
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{
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int pir;
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asm ("mfspr %0,1023" : "=r"(pir));
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return pir;
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}
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static __inline struct cpu_info *
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curcpu(void)
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{
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struct cpu_info *ci;
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asm volatile ("mfsprg %0,0" : "=r"(ci));
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return ci;
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}
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void cpu_boot_secondary_processors(void);
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extern struct cpu_info cpu_info[];
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#define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0)
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#define curproc curcpu()->ci_curproc
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#define curpcb curcpu()->ci_curpcb
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#define curpm curcpu()->ci_curpm
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#define want_resched curcpu()->ci_want_resched
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#define astpending curcpu()->ci_astpending
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#define intr_depth curcpu()->ci_intrdepth
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#define CPU_INFO_ITERATOR int
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#define CPU_INFO_FOREACH(cii, ci) \
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cii = 0, ci = &cpu_info[0]; cii < CPU_MAXNUM; cii++, ci++
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#else
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extern struct cpu_info cpu_info_store;
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extern volatile int want_resched;
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extern volatile int astpending;
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extern volatile int intr_depth;
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#define curcpu() (&cpu_info_store)
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#define cpu_number() 0
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#define CPU_INFO_ITERATOR int
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#define CPU_INFO_FOREACH(cii, ci) \
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cii = 0, ci = curcpu(); ci != NULL; ci = NULL
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#endif /* MULTIPROCESSOR */
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static __inline register_t
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mfmsr(void)
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{
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register_t msr;
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asm volatile ("mfmsr %0" : "=r"(msr));
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return msr;
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}
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static __inline void
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mtmsr(register_t msr)
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{
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asm volatile ("mtmsr %0" : : "r"(msr));
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}
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static __inline uint32_t
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mftbl(void)
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{
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uint32_t tbl;
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asm volatile ("mftbl %0" : "=r"(tbl));
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return tbl;
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}
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static __inline uint64_t
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mftb(void)
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{
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uint64_t tb;
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int tmp;
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asm volatile ("
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1: mftbu %0 \n\
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mftb %0+1 \n\
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mftbu %1 \n\
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cmplw %0,%1 \n\
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bne- 1b"
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: "=r"(tb), "=r"(tmp) :: "cr0");
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return tb;
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}
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static __inline uint32_t
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mfpvr(void)
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{
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uint32_t pvr;
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asm volatile ("mfpvr %0" : "=r"(pvr));
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return (pvr);
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}
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#define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0)
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#define CLKF_BASEPRI(frame) ((frame)->pri == 0)
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#define CLKF_PC(frame) ((frame)->srr0)
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#define CLKF_INTR(frame) ((frame)->depth > 0)
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#define PROC_PC(p) (trapframe(p)->srr0)
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#define cpu_swapout(p)
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#define cpu_wait(p)
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extern int powersave;
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extern int cpu_timebase;
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extern int cpu_printfataltraps;
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extern char cpu_model[];
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struct cpu_info *cpu_attach_common(struct device *, int);
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void cpu_setup(struct device *, struct cpu_info *);
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void cpu_identify(char *, size_t);
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void delay (unsigned int);
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void cpu_probe_cache(void);
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void dcache_flush_page(vaddr_t);
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void icache_flush_page(vaddr_t);
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void dcache_flush(vaddr_t, vsize_t);
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void icache_flush(vaddr_t, vsize_t);
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#define DELAY(n) delay(n)
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#define need_resched(ci) (want_resched = 1, astpending = 1)
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#define need_proftick(p) ((p)->p_flag |= P_OWEUPC, astpending = 1)
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#define signotify(p) (astpending = 1)
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#ifdef PPC_MPC6XX
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void mpc6xx_init(void (*)(void));
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void mpc6xx_startup(const char *);
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void mpc6xx_dumpsys(void);
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void mpc6xx_install_extint(void (*)(void));
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void *mapiodev(paddr_t, psize_t);
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paddr_t kvtop(caddr_t);
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void softnet(int);
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extern paddr_t msgbuf_paddr;
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extern int cpu_altivec;
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#endif
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#endif /* _KERNEL */
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#if defined(_KERNEL) || defined(_STANDALONE)
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#if !defined(CACHELINESIZE)
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#define CACHELINESIZE 32
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#endif
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#endif
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void __syncicache(void *, size_t);
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/*
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* CTL_MACHDEP definitions.
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*/
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#define CPU_CACHELINE 1
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#define CPU_TIMEBASE 2
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#define CPU_CPUTEMP 3
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#define CPU_PRINTFATALTRAPS 4
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#define CPU_CACHEINFO 5
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#define CPU_ALTIVEC 6
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#define CPU_MODEL 7
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#define CPU_POWERSAVE 8
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#define CPU_MAXID 9
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#define CTL_MACHDEP_NAMES { \
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{ 0, 0 }, \
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{ "cachelinesize", CTLTYPE_INT }, \
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{ "timebase", CTLTYPE_INT }, \
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{ "cputempature", CTLTYPE_INT }, \
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{ "printfataltraps", CTLTYPE_INT }, \
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{ "cacheinfo", CTLTYPE_STRUCT }, \
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{ "altivec", CTLTYPE_INT }, \
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{ "model", CTLTYPE_STRING }, \
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{ "powersave", CTLTYPE_INT }, \
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}
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#endif /* _POWERPC_CPU_H_ */
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