thorpej 1b20a04772 * Split pte_cache_mode into pte_l1_s_cache_mode, pte_l2_l_cache_mode, ... and pte_l2_s_cache_mode. The cache-meaningful bits are different for these descriptor types on some processor models. * Add pte_*_cache_mask, corresponding to each above, which has a mask of the cache-meangful bits, and define those for generic and XScale MMU classes. Note, the L2_S_CACHE_MASK_xscale definition requires use of the Extended Small Page L2 descriptor (the "X" bit overlaps with AP bits otherwise).		2002-04-09 22:37:00 +00:00
..
cpu_mainbus.c
mainbus_io_asm.S
mainbus_io.c	* Split pte_cache_mode into pte_l1_s_cache_mode, pte_l2_l_cache_mode,	2002-04-09 22:37:00 +00:00
mainbus.c
mainbus.h