357 lines
9.1 KiB
C
357 lines
9.1 KiB
C
/* $NetBSD: pci_machdep.c,v 1.11 2003/07/15 03:35:49 lukem Exp $ */
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/*
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* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
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* Copyright (c) 1994 Charles M. Hannum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles M. Hannum.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Machine-specific functions for PCI autoconfiguration.
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*
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* On PCs, there are two methods of generating PCI configuration cycles.
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* We try to detect the appropriate mechanism for this machine and set
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* up a few function pointers to access the correct method directly.
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*
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* The configuration method can be hard-coded in the config file by
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* using `options PCI_CONF_MODE=N', where `N' is the configuration mode
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* as defined section 3.6.4.1, `Generating Configuration Cycles'.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.11 2003/07/15 03:35:49 lukem Exp $");
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#include "opt_openpic.h"
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/errno.h>
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#include <sys/extent.h>
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#include <sys/malloc.h>
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#include <sys/queue.h>
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#include <sys/systm.h>
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#include <sys/time.h>
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#include <uvm/uvm.h>
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#define _POWERPC_BUS_DMA_PRIVATE
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#include <machine/bus.h>
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#include <machine/pio.h>
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#include <machine/intr.h>
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#include <machine/openpicreg.h>
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#include <dev/isa/isavar.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pciconf.h>
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#include <sandpoint/isa/icu.h>
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struct powerpc_bus_dma_tag pci_bus_dma_tag = {
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0, /* _bounce_thresh */
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_bus_dmamap_create,
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_bus_dmamap_destroy,
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_bus_dmamap_load,
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_bus_dmamap_load_mbuf,
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_bus_dmamap_load_uio,
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_bus_dmamap_load_raw,
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_bus_dmamap_unload,
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NULL, /* _dmamap_sync */
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_bus_dmamem_alloc,
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_bus_dmamem_free,
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_bus_dmamem_map,
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_bus_dmamem_unmap,
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_bus_dmamem_mmap,
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};
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#define PCI_CONFIG_ENABLE 0x80000000UL
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void
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pci_attach_hook(parent, self, pba)
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struct device *parent, *self;
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struct pcibus_attach_args *pba;
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{
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}
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int
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pci_bus_maxdevs(pc, busno)
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pci_chipset_tag_t pc;
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int busno;
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{
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/*
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* Bus number is irrelevant. Configuration Mechanism 1 is in
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* use, can have devices 0-32 (i.e. the `normal' range).
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*/
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return (32);
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}
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pcitag_t
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pci_make_tag(pc, bus, device, function)
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pci_chipset_tag_t pc;
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int bus, device, function;
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{
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pcitag_t tag;
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if (bus >= 256 || device >= 32 || function >= 8)
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panic("pci_make_tag: bad request");
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tag = PCI_CONFIG_ENABLE |
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(bus << 16) | (device << 11) | (function << 8);
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return tag;
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}
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void
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pci_decompose_tag(pc, tag, bp, dp, fp)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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int *bp, *dp, *fp;
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{
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if (bp != NULL)
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*bp = (tag >> 16) & 0xff;
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if (dp != NULL)
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*dp = (tag >> 11) & 0x1f;
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if (fp != NULL)
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*fp = (tag >> 8) & 0x7;
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return;
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}
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/*
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* The Kahlua documentation says that "reg" should be left-shifted by two
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* and be in bits 2-7. Apparently not. It doesn't work that way, and the
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* DINK32 ROM doesn't do it that way (I peeked at 0xfec00000 after running
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* the DINK32 "pcf" command).
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*/
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#define SP_PCI(tag, reg) ((tag) | (reg))
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pcireg_t
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pci_conf_read(pc, tag, reg)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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int reg;
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{
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pcireg_t data;
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out32rb(SANDPOINT_PCI_CONFIG_ADDR, SP_PCI(tag,reg));
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data = in32rb(SANDPOINT_PCI_CONFIG_DATA);
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out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0);
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return data;
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}
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void
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pci_conf_write(pc, tag, reg, data)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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int reg;
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pcireg_t data;
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{
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out32rb(SANDPOINT_PCI_CONFIG_ADDR, SP_PCI(tag, reg));
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out32rb(SANDPOINT_PCI_CONFIG_DATA, data);
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out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0);
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}
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int
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pci_intr_map(pa, ihp)
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struct pci_attach_args *pa;
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pci_intr_handle_t *ihp;
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{
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int pin = pa->pa_intrpin;
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int line = pa->pa_intrline;
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if (pin == 0) {
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/* No IRQ used. */
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goto bad;
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}
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if (pin > 4) {
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printf("pci_intr_map: bad interrupt pin %d\n", pin);
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goto bad;
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}
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/*
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* Section 6.2.4, `Miscellaneous Functions', says that 255 means
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* `unknown' or `no connection' on a PC. We assume that a device with
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* `no connection' either doesn't have an interrupt (in which case the
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* pin number should be 0, and would have been noticed above), or
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* wasn't configured by the BIOS (in which case we punt, since there's
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* no real way we can know how the interrupt lines are mapped in the
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* hardware).
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*
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* XXX
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* Since IRQ 0 is only used by the clock, and we can't actually be sure
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* that the BIOS did its job, we also recognize that as meaning that
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* the BIOS has not configured the device.
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*/
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if (line == 255) {
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printf("pci_intr_map: no mapping for pin %c\n", '@' + pin);
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goto bad;
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}
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#if defined(OPENPIC_SERIAL_MODE)
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if (line == 11) {
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switch (pin) {
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case PCI_INTERRUPT_PIN_A:
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*ihp = SANDPOINT_INTR_WINBOND_A;
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break;
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case PCI_INTERRUPT_PIN_B:
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*ihp = SANDPOINT_INTR_WINBOND_B;
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break;
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case PCI_INTERRUPT_PIN_C:
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*ihp = SANDPOINT_INTR_WINBOND_C;
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break;
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case PCI_INTERRUPT_PIN_D:
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*ihp = SANDPOINT_INTR_WINBOND_D;
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break;
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default:
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printf("pci_intr_map: bad interrupt line %d,%c\n",
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line, pin + '@');
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goto bad;
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break;
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}
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*ihp = SANDPOINT_INTR_WINBOND_C;
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} else {
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#else
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if (1) {
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#endif
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/*
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* Sandpoint has 4 PCI slots.
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* Sandpoint rev. X2 has them in a weird order. Counting
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* from center out toward the edge, we have:
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* Slot 1 (dev 14?) (labelled 1)
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* Slot 0 (dev 13?) (labelled 2)
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* Slot 3 (dev 16) (labelled 3)
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* Slot 2 (dev 15) (labelled 4)
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* To keep things confusing, we will consistently use a zero-
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* based numbering scheme where Motorola's is usually 1-based.
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*/
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if (line < 13 || line > 16) {
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printf("pci_intr_map: bad interrupt line %d,%c\n",
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line, pin + '@');
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goto bad;
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}
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/*
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* In the PCI configuration code, we simply assign the dev
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* number to the interrupt line. We extract it here for the
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* interrupt, but subtract off the lowest dev (13) to get
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* the IRQ.
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*/
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#if defined(OPENPIC_SERIAL_MODE)
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*ihp = line - 11;
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#else
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*ihp = line - 13;
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#endif
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}
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return 0;
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bad:
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*ihp = -1;
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return 1;
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}
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const char *
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pci_intr_string(pc, ih)
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pci_chipset_tag_t pc;
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pci_intr_handle_t ih;
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{
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static char irqstr[8]; /* 4 + 2 + NULL + sanity */
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if (ih < 0 || ih >= ICU_LEN)
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panic("pci_intr_string: bogus handle 0x%x", ih);
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sprintf(irqstr, "irq %d", ih);
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return (irqstr);
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}
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const struct evcnt *
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pci_intr_evcnt(pc, ih)
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pci_chipset_tag_t pc;
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pci_intr_handle_t ih;
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{
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/* XXX for now, no evcnt parent reported */
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return NULL;
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}
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void *
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pci_intr_establish(pc, ih, level, func, arg)
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pci_chipset_tag_t pc;
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pci_intr_handle_t ih;
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int level, (*func) __P((void *));
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void *arg;
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{
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#if 0
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if (ih < SANDPOINT_INTR_PCI0 || ih > SANDPOINT_INTR_PCI3)
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panic("pci_intr_establish: bogus handle 0x%x", ih);
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#endif
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/*
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* ih is the value assigned in pci_intr_map(), above.
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* For the Sandpoint, this is the zero-based slot #,
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* configured when the bus is set up.
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*/
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return intr_establish(ih, IST_LEVEL, level, func, arg);
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}
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void
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pci_intr_disestablish(pc, cookie)
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pci_chipset_tag_t pc;
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void *cookie;
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{
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intr_disestablish(cookie);
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}
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void
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pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin, int swiz,
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int *iline)
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{
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if (bus == 0) {
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*iline = dev;
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} else {
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/*
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* If we are not on bus zero, we're behind a bridge, so we
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* swizzle.
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*
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* The documentation lies about this. In slot 3 (numbering
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* from 0) aka device 16, INTD# becomes an interrupt for
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* slot 2. INTC# becomes an interrupt for slot 1, etc.
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* In slot 2 aka device 16, INTD# becomes an interrupt for
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* slot 1, etc.
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*
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* Verified for INTD# on device 16, INTC# on device 16,
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* INTD# on device 15, INTD# on device 13, and INTC# on
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* device 14. I presume that the rest follow the same
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* pattern.
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*
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* Slot 0 is device 13, and is the base for the rest.
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*/
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*iline = 13 + ((swiz + dev + 3) & 3);
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}
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}
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