72 lines
3.1 KiB
C
72 lines
3.1 KiB
C
/* $NetBSD: icsidereg.h,v 1.3 2002/09/15 11:00:11 bjh21 Exp $ */
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/*
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* Copyright (c) 1997 Mark Brinicombe
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* Copyright (c) 1997 Causality Limited
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Registers and address offsets for the ICS IDE card.
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*/
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/* ID register, read 4 consecutive words and extract ID from bit 0 */
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#define ID_REGISTER_OFFSET 0x2280 /* byte offset from fast base */
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#define REGISTER_SPACING_SHIFT 6
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#define IDE_REGISTER_SPACE 0x200
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#define AUX_REGISTER_SPACE 4
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#define IRQ_REGISTER_SPACE 4
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#define ID_REGISTER_SPACE 4
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#define IRQ_STATUS_REGISTER_MASK 0x01
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/* IDE drive registers */
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#define ICSIDE_MAX_CHANNELS 2
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/* ARCIN V5 registers */
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#define V5_IDE_BASE 0x2800 /* byte offset from base */
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#define V5_AUX_BASE 0x2a80 /* byte offset from base */
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#define V5_IRQ_BASE 0x0004 /* byte offset from base */
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#define V5_IRQSTAT_BASE 0x0000 /* byte offset from base */
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/* ARCIN V6 registers */
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#define V6_ADDRLATCH 0x0000
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#define V6_ADDRLATCH_DMACHAN 0x01 /* XXX doc is unclear, poss 0x02*/
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#define V6_ADDRLATCH_EASI 0x20 /* EASI space enable */
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#define V6_P_IDE_BASE 0x2000 /* byte offset from base */
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#define V6_P_AUX_BASE 0x2380 /* byte offset from base */
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#define V6_P_IRQ_BASE 0x2200 /* byte offset from base */
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#define V6_P_IRQSTAT_BASE 0x2290 /* byte offset from base */
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#define V6_S_IDE_BASE 0x3000 /* byte offset from base */
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#define V6_S_AUX_BASE 0x3380 /* byte offset from base */
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#define V6_S_IRQ_BASE 0x3200 /* byte offset from base */
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#define V6_S_IRQSTAT_BASE 0x3290 /* byte offset from base */
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