497 lines
14 KiB
C
497 lines
14 KiB
C
/* $Id: at91spi.c,v 1.3 2011/07/01 19:31:17 dyoung Exp $ */
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/* $NetBSD: at91spi.c,v 1.3 2011/07/01 19:31:17 dyoung Exp $ */
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/*-
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* Copyright (c) 2007 Embedtronics Oy. All rights reserved.
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*
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* Based on arch/mips/alchemy/dev/auspi.c,
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* Copyright (c) 2006 Urbana-Champaign Independent Media Center.
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* Copyright (c) 2006 Garrett D'Amore.
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* All rights reserved.
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*
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* Portions of this code were written by Garrett D'Amore for the
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* Champaign-Urbana Community Wireless Network Project.
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* 3. All advertising materials mentioning features or use of this
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* software must display the following acknowledgements:
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* This product includes software developed by the Urbana-Champaign
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* Independent Media Center.
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* This product includes software developed by Garrett D'Amore.
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* 4. Urbana-Champaign Independent Media Center's name and Garrett
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* D'Amore's name may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT
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* MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT
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* MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: at91spi.c,v 1.3 2011/07/01 19:31:17 dyoung Exp $");
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#include "locators.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/errno.h>
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#include <sys/proc.h>
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#include <sys/bus.h>
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#include <machine/cpu.h>
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#include <machine/vmparam.h>
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#include <sys/inttypes.h>
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#include <arm/at91/at91var.h>
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#include <arm/at91/at91reg.h>
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#include <arm/at91/at91spivar.h>
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#include <arm/at91/at91spireg.h>
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#define at91spi_select(sc, slave) \
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(sc)->sc_md->select_slave((sc), (slave))
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#define STATIC
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//#define AT91SPI_DEBUG 4
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#ifdef AT91SPI_DEBUG
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int at91spi_debug = AT91SPI_DEBUG;
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#define DPRINTFN(n,x) if (at91spi_debug>(n)) printf x;
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#else
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#define DPRINTFN(n,x)
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#endif
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STATIC int at91spi_intr(void *);
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/* SPI service routines */
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STATIC int at91spi_configure(void *, int, int, int);
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STATIC int at91spi_transfer(void *, struct spi_transfer *);
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STATIC void at91spi_xfer(struct at91spi_softc *sc, int start);
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/* internal stuff */
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STATIC void at91spi_done(struct at91spi_softc *, int);
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STATIC void at91spi_send(struct at91spi_softc *);
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STATIC void at91spi_recv(struct at91spi_softc *);
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STATIC void at91spi_sched(struct at91spi_softc *);
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#define GETREG(sc, x) \
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bus_space_read_4(sc->sc_iot, sc->sc_ioh, x)
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#define PUTREG(sc, x, v) \
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, x, v)
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void
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at91spi_attach_common(device_t parent, device_t self, void *aux,
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at91spi_machdep_tag_t md)
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{
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struct at91spi_softc *sc = device_private(self);
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struct at91bus_attach_args *sa = aux;
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struct spibus_attach_args sba;
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bus_dma_segment_t segs;
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int rsegs, err;
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aprint_normal(": AT91 SPI Controller\n");
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sc->sc_dev = self;
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sc->sc_iot = sa->sa_iot;
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sc->sc_pid = sa->sa_pid;
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sc->sc_dmat = sa->sa_dmat;
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sc->sc_md = md;
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if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, &sc->sc_ioh))
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panic("%s: Cannot map registers", device_xname(self));
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/* we want to use dma, so allocate dma memory: */
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err = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 0, PAGE_SIZE,
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&segs, 1, &rsegs, BUS_DMA_WAITOK);
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if (err == 0) {
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err = bus_dmamem_map(sc->sc_dmat, &segs, 1, PAGE_SIZE,
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&sc->sc_dmapage,
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BUS_DMA_WAITOK);
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}
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if (err == 0) {
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err = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1,
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PAGE_SIZE, 0, BUS_DMA_WAITOK,
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&sc->sc_dmamap);
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}
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if (err == 0) {
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err = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap,
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sc->sc_dmapage, PAGE_SIZE, NULL,
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BUS_DMA_WAITOK);
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}
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if (err != 0) {
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panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev));
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}
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sc->sc_dmaaddr = sc->sc_dmamap->dm_segs[0].ds_addr;
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/*
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* Initialize SPI controller
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*/
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sc->sc_spi.sct_cookie = sc;
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sc->sc_spi.sct_configure = at91spi_configure;
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sc->sc_spi.sct_transfer = at91spi_transfer;
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//sc->sc_spi.sct_nslaves must have been initialized by machdep code
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if (!sc->sc_spi.sct_nslaves) {
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aprint_error("%s: no slaves!\n", device_xname(sc->sc_dev));
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}
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sba.sba_controller = &sc->sc_spi;
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/* initialize the queue */
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SIMPLEQ_INIT(&sc->sc_q);
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/* reset the SPI */
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at91_peripheral_clock(sc->sc_pid, 1);
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PUTREG(sc, SPI_CR, SPI_CR_SWRST);
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delay(100);
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/* be paranoid and make sure the PDC is dead */
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PUTREG(sc, SPI_PDC_BASE + PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS);
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PUTREG(sc, SPI_PDC_BASE + PDC_RNCR, 0);
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PUTREG(sc, SPI_PDC_BASE + PDC_RCR, 0);
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PUTREG(sc, SPI_PDC_BASE + PDC_TNCR, 0);
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PUTREG(sc, SPI_PDC_BASE + PDC_TCR, 0);
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// configure SPI:
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PUTREG(sc, SPI_IDR, -1);
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PUTREG(sc, SPI_CSR(0), SPI_CSR_SCBR | SPI_CSR_BITS_8);
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PUTREG(sc, SPI_CSR(1), SPI_CSR_SCBR | SPI_CSR_BITS_8);
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PUTREG(sc, SPI_CSR(2), SPI_CSR_SCBR | SPI_CSR_BITS_8);
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PUTREG(sc, SPI_CSR(3), SPI_CSR_SCBR | SPI_CSR_BITS_8);
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PUTREG(sc, SPI_MR, SPI_MR_MODFDIS/* <- machdep? */ | SPI_MR_MSTR);
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/* enable device interrupts */
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sc->sc_ih = at91_intr_establish(sc->sc_pid, IPL_BIO, INTR_HIGH_LEVEL,
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at91spi_intr, sc);
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/* enable SPI */
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PUTREG(sc, SPI_CR, SPI_CR_SPIEN);
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if (GETREG(sc, SPI_SR) & SPI_SR_RDRF)
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(void)GETREG(sc, SPI_RDR);
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PUTREG(sc, SPI_PDC_BASE + PDC_PTCR, PDC_PTCR_TXTEN | PDC_PTCR_RXTEN);
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/* attach slave devices */
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(void) config_found_ia(sc->sc_dev, "spibus", &sba, spibus_print);
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}
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int
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at91spi_configure(void *arg, int slave, int mode, int speed)
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{
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struct at91spi_softc *sc = arg;
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uint scbr;
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uint32_t csr;
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/* setup interrupt registers */
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PUTREG(sc, SPI_IDR, -1); /* disable interrupts for now */
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csr = GETREG(sc, SPI_CSR(0)); /* read register */
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csr &= SPI_CSR_RESERVED; /* keep reserved bits */
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csr |= SPI_CSR_BITS_8; /* assume 8 bit transfers */
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/*
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* Calculate clock divider
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*/
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scbr = speed ? ((AT91_MSTCLK + speed - 1) / speed + 1) & ~1 : -1;
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if (scbr > 0xFF) {
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aprint_error("%s: speed %d not supported\n",
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device_xname(sc->sc_dev), speed);
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return EINVAL;
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}
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csr |= scbr << SPI_CSR_SCBR_SHIFT;
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/*
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* I'm not entirely confident that these values are correct.
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* But at least mode 0 appears to work properly with the
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* devices I have tested. The documentation seems to suggest
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* that I have the meaning of the clock delay bit inverted.
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*/
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switch (mode) {
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case SPI_MODE_0:
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csr |= SPI_CSR_NCPHA; /* CPHA = 0, CPOL = 0 */
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break;
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case SPI_MODE_1:
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csr |= 0; /* CPHA = 1, CPOL = 0 */
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break;
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case SPI_MODE_2:
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csr |= SPI_CSR_NCPHA /* CPHA = 0, CPOL = 1 */
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| SPI_CSR_CPOL;
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break;
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case SPI_MODE_3:
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csr |= SPI_CSR_CPOL; /* CPHA = 1, CPOL = 1 */
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break;
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default:
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return EINVAL;
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}
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PUTREG(sc, SPI_CSR(0), csr);
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DPRINTFN(3, ("%s: slave %d mode %d speed %d, csr=0x%08"PRIX32"\n",
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__FUNCTION__, slave, mode, speed, csr));
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#if 0
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// wait until ready!?
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for (i = 1000000; i; i -= 10) {
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if (GETREG(sc, AUPSC_SPISTAT) & SPISTAT_DR) {
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return 0;
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}
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}
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return ETIMEDOUT;
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#else
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return 0;
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#endif
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}
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#define HALF_BUF_SIZE (PAGE_SIZE / 2)
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void
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at91spi_xfer(struct at91spi_softc *sc, int start)
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{
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struct spi_chunk *chunk;
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int len;
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uint32_t sr;
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DPRINTFN(3, ("%s: sc=%p start=%d\n", __FUNCTION__, sc, start));
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/* so ready to transmit more / anything received? */
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if (((sr = GETREG(sc, SPI_SR)) & (SPI_SR_ENDTX | SPI_SR_ENDRX)) != (SPI_SR_ENDTX | SPI_SR_ENDRX)) {
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/* not ready, get out */
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DPRINTFN(3, ("%s: sc=%p start=%d sr=%"PRIX32"\n", __FUNCTION__, sc, start, sr));
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return;
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}
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DPRINTFN(3, ("%s: sr=%"PRIX32"\n", __FUNCTION__, sr));
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if (!start) {
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// ok, something has been transfered, synchronize..
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int offs = sc->sc_dmaoffs ^ HALF_BUF_SIZE;
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bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, offs, HALF_BUF_SIZE,
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BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
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if ((chunk = sc->sc_rchunk) != NULL) {
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if ((len = chunk->chunk_rresid) > HALF_BUF_SIZE)
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len = HALF_BUF_SIZE;
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if (chunk->chunk_rptr && len > 0) {
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memcpy(chunk->chunk_rptr, (const uint8_t *)sc->sc_dmapage + offs, len);
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chunk->chunk_rptr += len;
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}
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if ((chunk->chunk_rresid -= len) <= 0) {
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// done with this chunk, get next
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sc->sc_rchunk = chunk->chunk_next;
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}
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}
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}
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/* start transmitting next chunk: */
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if ((chunk = sc->sc_wchunk) != NULL) {
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/* make sure we transmit just half buffer at a time */
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len = MIN(chunk->chunk_wresid, HALF_BUF_SIZE);
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// setup outgoing data
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if (chunk->chunk_wptr && len > 0) {
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memcpy((uint8_t *)sc->sc_dmapage + sc->sc_dmaoffs, chunk->chunk_wptr, len);
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chunk->chunk_wptr += len;
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} else {
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memset((uint8_t *)sc->sc_dmapage + sc->sc_dmaoffs, 0, len);
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}
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/* advance to next transfer if it's time to */
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if ((chunk->chunk_wresid -= len) <= 0) {
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sc->sc_wchunk = sc->sc_wchunk->chunk_next;
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}
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/* determine which interrupt to get */
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if (sc->sc_wchunk) {
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/* just wait for next buffer to free */
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PUTREG(sc, SPI_IER, SPI_SR_ENDRX);
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} else {
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/* must wait until transfer has completed */
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PUTREG(sc, SPI_IDR, SPI_SR_ENDRX);
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PUTREG(sc, SPI_IER, SPI_SR_RXBUFF);
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}
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DPRINTFN(3, ("%s: dmaoffs=%d len=%d wchunk=%p (%p:%d) rchunk=%p (%p:%d) mr=%"PRIX32" sr=%"PRIX32" imr=%"PRIX32" csr0=%"PRIX32"\n",
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__FUNCTION__, sc->sc_dmaoffs, len, sc->sc_wchunk,
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sc->sc_wchunk ? sc->sc_wchunk->chunk_wptr : NULL,
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sc->sc_wchunk ? sc->sc_wchunk->chunk_wresid : -1,
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sc->sc_rchunk,
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sc->sc_rchunk ? sc->sc_rchunk->chunk_rptr : NULL,
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sc->sc_rchunk ? sc->sc_rchunk->chunk_rresid : -1,
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GETREG(sc, SPI_MR), GETREG(sc, SPI_SR),
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GETREG(sc, SPI_IMR), GETREG(sc, SPI_CSR(0))));
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// prepare DMA
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bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, sc->sc_dmaoffs, len,
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BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
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// and start transmitting / receiving
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PUTREG(sc, SPI_PDC_BASE + PDC_RNPR, sc->sc_dmaaddr + sc->sc_dmaoffs);
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PUTREG(sc, SPI_PDC_BASE + PDC_RNCR, len);
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PUTREG(sc, SPI_PDC_BASE + PDC_TNPR, sc->sc_dmaaddr + sc->sc_dmaoffs);
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PUTREG(sc, SPI_PDC_BASE + PDC_TNCR, len);
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// swap buffer
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sc->sc_dmaoffs ^= HALF_BUF_SIZE;
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// get out
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return;
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} else {
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DPRINTFN(3, ("%s: nothing to write anymore\n", __FUNCTION__));
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return;
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}
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}
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void
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at91spi_sched(struct at91spi_softc *sc)
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{
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struct spi_transfer *st;
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int err;
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while ((st = spi_transq_first(&sc->sc_q)) != NULL) {
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DPRINTFN(2, ("%s: st=%p\n", __FUNCTION__, st));
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/* remove the item */
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spi_transq_dequeue(&sc->sc_q);
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/* note that we are working on it */
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sc->sc_transfer = st;
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if ((err = at91spi_select(sc, st->st_slave)) != 0) {
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spi_done(st, err);
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continue;
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}
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/* setup chunks */
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sc->sc_rchunk = sc->sc_wchunk = st->st_chunks;
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/* now kick the master start to get the chip running */
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at91spi_xfer(sc, TRUE);
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/* enable error interrupts too: */
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PUTREG(sc, SPI_IER, SPI_SR_MODF | SPI_SR_OVRES);
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sc->sc_running = TRUE;
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return;
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}
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DPRINTFN(2, ("%s: nothing to do anymore\n", __FUNCTION__));
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PUTREG(sc, SPI_IDR, -1); /* disable interrupts */
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at91spi_select(sc, -1);
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sc->sc_running = FALSE;
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}
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void
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at91spi_done(struct at91spi_softc *sc, int err)
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{
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struct spi_transfer *st;
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/* called from interrupt handler */
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if ((st = sc->sc_transfer) != NULL) {
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sc->sc_transfer = NULL;
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DPRINTFN(2, ("%s: st %p finished with error code %d\n", __FUNCTION__, st, err));
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spi_done(st, err);
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}
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/* make sure we clear these bits out */
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sc->sc_wchunk = sc->sc_rchunk = NULL;
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at91spi_sched(sc);
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}
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int
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at91spi_intr(void *arg)
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{
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struct at91spi_softc *sc = arg;
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uint32_t imr, sr;
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int err = 0;
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if ((imr = GETREG(sc, SPI_IMR)) == 0) {
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/* interrupts are not enabled, get out */
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DPRINTFN(4, ("%s: interrupts are not enabled\n", __FUNCTION__));
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return 0;
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}
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sr = GETREG(sc, SPI_SR);
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if (!(sr & imr)) {
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/* interrupt did not happen, get out */
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DPRINTFN(3, ("%s: interrupts are not enabled, sr=%08"PRIX32" imr=%08"PRIX32"\n",
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__FUNCTION__, sr, imr));
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return 0;
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}
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DPRINTFN(3, ("%s: sr=%08"PRIX32" imr=%08"PRIX32"\n",
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__FUNCTION__, sr, imr));
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if (sr & imr & SPI_SR_MODF) {
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printf("%s: mode fault!\n", device_xname(sc->sc_dev));
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err = EIO;
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}
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if (sr & imr & SPI_SR_OVRES) {
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printf("%s: overrun error!\n", device_xname(sc->sc_dev));
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err = EIO;
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}
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if (err) {
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/* clear errors */
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/* complete transfer */
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at91spi_done(sc, err);
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} else {
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/* do all data exchanges */
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at91spi_xfer(sc, FALSE);
|
|
|
|
/*
|
|
* if the master done bit is set, make sure we do the
|
|
* right processing.
|
|
*/
|
|
if (sr & imr & SPI_SR_RXBUFF) {
|
|
if ((sc->sc_wchunk != NULL) ||
|
|
(sc->sc_rchunk != NULL)) {
|
|
printf("%s: partial transfer?\n",
|
|
device_xname(sc->sc_dev));
|
|
err = EIO;
|
|
}
|
|
at91spi_done(sc, err);
|
|
}
|
|
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
int
|
|
at91spi_transfer(void *arg, struct spi_transfer *st)
|
|
{
|
|
struct at91spi_softc *sc = arg;
|
|
int s;
|
|
|
|
/* make sure we select the right chip */
|
|
s = splbio();
|
|
spi_transq_enqueue(&sc->sc_q, st);
|
|
if (sc->sc_running == 0) {
|
|
at91spi_sched(sc);
|
|
}
|
|
splx(s);
|
|
return 0;
|
|
}
|
|
|