277 lines
7.1 KiB
C
277 lines
7.1 KiB
C
/* $NetBSD: insn.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _RISCV_INSN_H_
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#define _RISCV_INSN_H_
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union riscv_insn {
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uint32_t val;
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struct {
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unsigned int r_opcode : 7;
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unsigned int r_rd : 5;
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unsigned int r_funct3 : 3;
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unsigned int r_rs1 : 5;
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unsigned int r_rs2 : 5;
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unsigned int r_funct7 : 7;
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} type_r;
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struct {
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unsigned int rs_opcode : 7;
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unsigned int rs_rd : 5;
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unsigned int rs_funct3 : 3;
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unsigned int rs_rs1 : 5;
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unsigned int rs_shmat : 6;
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unsigned int rs_funct6 : 6;
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} type_rs;
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struct {
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unsigned int ra_opcode : 7;
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unsigned int ra_rd : 5;
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unsigned int ra_funct3 : 3;
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unsigned int ra_rs1 : 5;
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unsigned int ra_rs2 : 5;
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unsigned int ra_rl : 1;
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unsigned int ra_aq : 1;
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unsigned int ra_funct5 : 6;
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} type_ra;
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struct {
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unsigned int rf_opcode : 7;
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unsigned int rf_rd : 5;
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unsigned int rf_rm : 3;
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unsigned int rf_rs1 : 5;
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unsigned int rf_rs2 : 5;
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unsigned int rf_funct2 : 2;
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unsigned int rf_rs3 : 5;
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} type_rf;
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struct {
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unsigned int i_opcode : 7;
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unsigned int i_rd : 5;
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unsigned int i_funct3 : 3;
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unsigned int i_rs1 : 5;
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signed int i_imm11to0 : 12;
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} type_i;
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struct {
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unsigned int s_opcode : 7;
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unsigned int s_imm4_to_0 : 5;
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unsigned int s_funct3 : 3;
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unsigned int s_rs1 : 5;
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unsigned int s_rs2 : 5;
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signed int s_imm11_to_5 : 7;
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} type_s;
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struct {
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unsigned int sb_opcode : 7;
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unsigned int sb_imm11 : 1;
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unsigned int sb_imm4to1 : 4;
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unsigned int sb_funct3 : 3;
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unsigned int sb_rs1 : 5;
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unsigned int sb_rs2 : 5;
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unsigned int sb_imm10to5 : 6;
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signed int sb_imm12 : 1;
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} type_sb;
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struct {
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unsigned int u_opcode : 7;
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unsigned int u_rd : 5;
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signed int u_imm31to12 : 20;
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} type_u;
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struct {
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unsigned int uj_opcode : 7;
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unsigned int uj_rd : 5;
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unsigned int uj_imm19to12 : 9;
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unsigned int uj_imm11 : 1;
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unsigned int uj_imm10to1 : 9;
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signed int uj_imm20 : 1;
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} type_uj;
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};
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#define OPCODE_P(i, x) (((i) & 0b1111111) == ((OPCODE_##x<<2)|0b11))
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#define OPCODE_LOAD 0b00000
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#define OPCODE_LOADFP 0b00001
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#define OPCODE_CUSTOM0 0b00010
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#define OPCODE_MISCMEM 0b00011
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#define OPCODE_OPIMM 0b00100
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#define OPCODE_AUIPC 0b00101
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#define OPCODE_OPIMM32 0b00110
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#define OPCODE_X48a 0b00111
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#define OPCODE_STORE 0b01000
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#define OPCODE_STOREFP 0b01001
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#define OPCODE_CUSTOM1 0b01010
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#define OPCODE_AMO 0b01011
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#define OPCODE_OP 0b01100
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#define OPCODE_LUI 0b01101
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#define OPCODE_OP32 0b01110
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#define OPCODE_X64 0b01111
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#define OPCODE_MADD 0b10000 // FMADD.[S,D]
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#define OPCODE_MSUB 0b10001 // FMSUB.[S,D]
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#define OPCODE_NMSUB 0b10010 // FNMADD.[S,D]
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#define OPCODE_NMADD 0b10011 // FNMSUB.[S,D]
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#define OPCODE_OPFP 0b10100
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#define OPCODE_rsvd21 0b10101
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#define OPCODE_CUSTOM2 0b10110
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#define OPCODE_X48b 0b10111
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#define OPCODE_BRANCH 0b11000
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#define OPCODE_JALR 0b11001
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#define OPCODE_rsvd26 0b11010
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#define OPCODE_JAL 0b11011
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#define OPCODE_SYSTEM 0b11100
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#define OPCODE_rsvd29 0b11101
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#define OPCODE_CUSTOM3 0b11110
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#define OPCODE_X80 0b11111
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// LOAD (0x00000)
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#define LOAD_LB 0b000
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#define LOAD_LH 0b001
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#define LOAD_LW 0b010
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#define LOAD_LD 0b011 // RV64I
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#define LOAD_LBU 0b100
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#define LOAD_LHU 0b101
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#define LOAD_LWU 0b110 // RV64I
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// LOADFP (0x00001)
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#define LOADFP_FLW 0b010
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#define LOADFP_FLD 0b011
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// MISCMEM (0x00010)
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#define MISCMEM_FENCE 0b000
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#define MISCMEM_FENCEI 0b001
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// OPIMM (0b00100) and OPIMM32 (0b00110) -- see OP (0b01100)
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// AUIPC (0b00101) - no functions
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// STORE (0b01000)
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#define STORE_SB 0b000
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#define STORE_SH 0b001
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#define STORE_SW 0b010
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#define STORE_SD 0b011 // RV64I
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// STOREFP (0b01001)
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#define STOREFP_FSW 0b010
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#define STOREFP_FSD 0b011
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// AMO (0b01011)
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#define AMO_W 0b010
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#define AMO_D 0b011
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// AMO funct5
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#define AMO_ADD 0b00000
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#define AMO_SWAP 0b00001
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#define AMO_LR 0b00010
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#define AMO_SC 0b00011
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#define AMO_XOR 0b00100
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#define AMO_OR 0b01000
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#define AMO_AND 0b01100
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#define AMO_MIN 0b10000
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#define AMO_MAX 0b10100
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#define AMO_MINU 0b11000
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#define AMO_MAXU 0b11100
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// OPIMM (0b00100), OPIMM32 (0b00110), OP (0b01100), OP32 (0b01110)
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#define OP_ADDSUB 0b000
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#define OP_SLL 0b001
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#define OP_SLT 0b010
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#define OP_SLTU 0b011
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#define OP_XOR 0b100
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#define OP_SRX 0b101
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#define OP_OR 0b110
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#define OP_AND 0b111
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#define OP_FUNCT6_SRX_SRL 0b000000
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#define OP_FUNCT6_SRX_SRA 0b010000
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#define OP_FUNCT7_ADD 0b0000000
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#define OP_FUNCT7_SUB 0b0100000
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#define OP_MUL 0b000
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#define OP_MULH 0b001
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#define OP_MULHSU 0b010
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#define OP_MULHU 0b011
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#define OP_DIV 0b100
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#define OP_DIVU 0b101
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#define OP_REM 0b110
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#define OP_REMU 0b111
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#define OP_FUNCT7_MULDIV 0b0000001
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// LUI (0b01101) - no functions
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// MADD (0b10000)
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#define MXXX_S 0b00
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//#define MXXX_S 0b01
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// MSUB (0b10001)
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// NMADD (0b10010)
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// NMSUB (0b10011)
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// OPFP (0b10100)
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#define OPFP_ADD 0b00000
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#define OPFP_SUB 0b00001
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#define OPFP_MUL 0b00010
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#define OPFP_DIV 0b00011
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#define OPFP_SGNJ 0b00100
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#define OPFP_MINMAX 0b00101
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#define OPFP_SQRT 0b01011
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#define OPFP_CMP 0b10100
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#define OPFP_CVT 0b11000
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#define OPFP_MV 0b11100
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#define OPFP_MV 0b11100
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#define SJGN_SGNJ 0b000
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#define SJGN_SGNJN 0b001
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#define SJGN_SGNJX 0b010
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// BRANCH (0b11000)
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#define BRANCH_BEQ 0b000
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#define BRANCH_BNE 0b001
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#define BRANCH_BLT 0b100
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#define BRANCH_BGE 0b101
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#define BRANCH_BLTU 0b110
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#define BRANCH_BGEU 0b111
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// JALR (0b11001) - no functions
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// JAL (0b11011) - no functions
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// SYSTEM (0b11100)
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#define SYSTEM_SFUNC 0b000
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#define SYSTEM_RDREG 0b010
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#define SFUNC_RS_SCALL 0b00000
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#define SFUNC_RS_SBREAK 0b00001
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#define RDREG_LO 0b1100000
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#define RDREG_HI 0b1100100
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#define RDREG_RS_CYCLE 0b00000
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#define RDREG_RS_TIME 0b00001
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#define RDREG_RS_INSTRET 0b00010
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#endif /* _RISCV_INSN_H_ */
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