325 lines
8.6 KiB
C
325 lines
8.6 KiB
C
/* $NetBSD: esp.c,v 1.28 2008/04/28 20:23:37 martin Exp $ */
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/*-
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* Copyright (c) 1997 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jeremy Cooper and Gordon W. Ross
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* "Front end" glue for the ncr53c9x chip, formerly known as the
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* Emulex SCSI Processor (ESP) which is what we actually have.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: esp.c,v 1.28 2008/04/28 20:23:37 martin Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <sys/buf.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/scsipi/scsi_message.h>
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#include <machine/autoconf.h>
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#include <machine/bus.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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#include <sun3/dev/dmareg.h>
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#include <sun3/dev/dmavar.h>
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#define ESP_REG_SIZE (12*4)
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struct esp_softc {
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struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
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bus_space_tag_t sc_bst; /* bus space tag */
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bus_space_handle_t sc_bsh; /* bus space handle */
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struct dma_softc *sc_dma; /* pointer to my dma */
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};
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static int espmatch(device_t, cfdata_t, void *);
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static void espattach(device_t, device_t, void *);
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CFATTACH_DECL_NEW(esp, sizeof(struct esp_softc),
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espmatch, espattach, NULL, NULL);
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/*
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* Functions and the switch for the MI code.
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*/
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static uint8_t esp_read_reg(struct ncr53c9x_softc *, int);
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static void esp_write_reg(struct ncr53c9x_softc *, int, uint8_t);
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static int esp_dma_isintr(struct ncr53c9x_softc *);
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static void esp_dma_reset(struct ncr53c9x_softc *);
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static int esp_dma_intr(struct ncr53c9x_softc *);
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static int esp_dma_setup(struct ncr53c9x_softc *, uint8_t **, size_t *,
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int, size_t *);
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static void esp_dma_go(struct ncr53c9x_softc *);
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static void esp_dma_stop(struct ncr53c9x_softc *);
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static int esp_dma_isactive(struct ncr53c9x_softc *);
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static struct ncr53c9x_glue esp_glue = {
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esp_read_reg,
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esp_write_reg,
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esp_dma_isintr,
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esp_dma_reset,
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esp_dma_intr,
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esp_dma_setup,
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esp_dma_go,
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esp_dma_stop,
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esp_dma_isactive,
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NULL, /* gl_clear_latched_intr */
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};
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static int
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espmatch(device_t parent, struct cfdata *cf, void *aux)
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{
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struct confargs *ca = aux;
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/*
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* Check for the esp registers.
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*/
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if (bus_peek(ca->ca_bustype,
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ca->ca_paddr + (NCR_STAT * 4), 1) == -1)
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return 0;
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/* If default ipl, fill it in. */
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if (ca->ca_intpri == -1)
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ca->ca_intpri = 2;
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return 1;
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}
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static void
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espattach(device_t parent, device_t self, void *aux)
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{
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struct esp_softc *esc = device_private(self);
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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struct confargs *ca = aux;
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/*
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* Set up glue for MI code early; we use some of it here.
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*/
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sc->sc_dev = self;
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sc->sc_glue = &esp_glue;
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/*
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* Map the ESP registers.
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*/
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esc->sc_bst = ca->ca_bustag;
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if (bus_space_map(esc->sc_bst, ca->ca_paddr, ESP_REG_SIZE, 0,
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&esc->sc_bsh) != 0) {
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aprint_error(": can't map register\n");
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return;
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}
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/* Other settings */
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sc->sc_id = 7;
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sc->sc_freq = 20; /* The 3/80 esp runs at 20 MHz */
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/*
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* Hook up the DMA driver.
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*/
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esc->sc_dma = espdmafind(device_unit(self));
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esc->sc_dma->sc_client = sc; /* Point back to us */
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/*
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* XXX More of this should be in ncr53c9x_attach(), but
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* XXX should we really poke around the chip that much in
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* XXX the MI code? Think about this more...
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*/
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/*
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* It is necessary to try to load the 2nd config register here,
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* to find out what rev the esp chip is, else the ncr53c9x_reset
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* will not set up the defaults correctly.
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*/
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sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
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sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE;
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sc->sc_cfg3 = NCRCFG3_CDB;
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NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
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if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) !=
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(NCRCFG2_SCSI2 | NCRCFG2_RPE)) {
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sc->sc_rev = NCR_VARIANT_ESP100;
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} else {
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sc->sc_cfg2 = NCRCFG2_SCSI2;
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NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
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sc->sc_cfg3 = 0;
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NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
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sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK);
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NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
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if (NCR_READ_REG(sc, NCR_CFG3) !=
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(NCRCFG3_CDB | NCRCFG3_FCLK)) {
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sc->sc_rev = NCR_VARIANT_ESP100A;
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} else {
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/* NCRCFG2_FE enables > 64K transfers */
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sc->sc_cfg2 |= NCRCFG2_FE;
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sc->sc_cfg3 = 0;
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NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
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sc->sc_rev = NCR_VARIANT_ESP200;
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}
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}
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/*
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* XXX minsync and maxxfer _should_ be set up in MI code,
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* XXX but it appears to have some dependency on what sort
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* XXX of DMA we're hooked up to, etc.
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*/
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/*
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* This is the value used to start sync negotiations
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* Note that the NCR register "SYNCTP" is programmed
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* in "clocks per byte", and has a minimum value of 4.
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* The SCSI period used in negotiation is one-fourth
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* of the time (in nanoseconds) needed to transfer one byte.
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* Since the chip's clock is given in MHz, we have the following
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* formula: 4 * period = (1000 / freq) * 4
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*/
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sc->sc_minsync = 1000 / sc->sc_freq;
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/*
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* Alas, we must now modify the value a bit, because it's
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* only valid when can switch on FASTCLK and FASTSCSI bits
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* in config register 3...
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*/
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switch (sc->sc_rev) {
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case NCR_VARIANT_ESP100:
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sc->sc_maxxfer = 64 * 1024;
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sc->sc_minsync = 0; /* No synch on old chip? */
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break;
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case NCR_VARIANT_ESP100A:
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sc->sc_maxxfer = 64 * 1024;
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/* Min clocks/byte is 5 */
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sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5);
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break;
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case NCR_VARIANT_ESP200:
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sc->sc_maxxfer = 16 * 1024 * 1024;
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/* XXX - do actually set FAST* bits */
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break;
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}
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/* and the interuppts */
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isr_add_autovect(ncr53c9x_intr, sc, ca->ca_intpri);
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evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
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device_xname(self), "intr");
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/* Do the common parts of attachment. */
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sc->sc_adapter.adapt_minphys = minphys;
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sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
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ncr53c9x_attach(sc);
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/* Turn on target selection using the `dma' method */
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sc->sc_features |= NCR_F_DMASELECT;
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}
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/*
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* Glue functions.
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*/
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uint8_t
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esp_read_reg(struct ncr53c9x_softc *sc, int reg)
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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return bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg * 4);
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}
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void
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esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg * 4, val);
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}
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int
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esp_dma_isintr(struct ncr53c9x_softc *sc)
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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return DMA_ISINTR(esc->sc_dma);
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}
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void
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esp_dma_reset(struct ncr53c9x_softc *sc)
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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dma_reset(esc->sc_dma);
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}
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int
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esp_dma_intr(struct ncr53c9x_softc *sc)
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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return espdmaintr(esc->sc_dma);
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}
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int
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esp_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len,
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int datain, size_t *dmasize)
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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return dma_setup(esc->sc_dma, addr, len, datain, dmasize);
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}
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void
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esp_dma_go(struct ncr53c9x_softc *sc)
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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DMA_GO(esc->sc_dma);
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}
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void
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esp_dma_stop(struct ncr53c9x_softc *sc)
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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DMA_STOP(esc->sc_dma);
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}
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int
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esp_dma_isactive(struct ncr53c9x_softc *sc)
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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return DMA_ISACTIVE(esc->sc_dma);
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}
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