150 lines
4.7 KiB
C
150 lines
4.7 KiB
C
/* $NetBSD: frame.h,v 1.1 2002/06/05 01:04:22 fredette Exp $ */
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/* $OpenBSD: frame.h,v 1.11 1999/11/25 18:28:06 mickey Exp $ */
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/*
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* Copyright (c) 1999 Michael Shalayeff
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Michael Shalayeff.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _HPPA_FRAME_H_
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#define _HPPA_FRAME_H_
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#include <machine/reg.h>
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/*
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* Call frame definitions
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*/
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#define HPPA_FRAME_NARGS (12)
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#define HPPA_FRAME_MAXARGS (HPPA_FRAME_NARGS * 4)
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#define HPPA_FRAME_ARG(n) (-(32 + 4*((n) + 1)))
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#define HPPA_FRAME_CARG(n,sp) ((register_t *)((sp) + HPPA_FRAME_ARG(n)))
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#define HPPA_FRAME_SIZE (64)
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#define HPPA_FRAME_PSP (-4)
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#define HPPA_FRAME_EP (-8)
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#define HPPA_FRAME_CLUP (-12)
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#define HPPA_FRAME_SL (-16)
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#define HPPA_FRAME_CRP (-20)
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#define HPPA_FRAME_ERP (-24)
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#define HPPA_FRAME_ESR4 (-28)
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#define HPPA_FRAME_EDP (-32)
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/*
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* Macros to decode processor status word.
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*/
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#define HPPA_PC_PRIV_MASK 3
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#define HPPA_PC_PRIV_KERN 0
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#define HPPA_PC_PRIV_USER 3
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#define USERMODE(pc) ((((register_t)pc) & HPPA_PC_PRIV_MASK) != HPPA_PC_PRIV_KERN)
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#define KERNMODE(pc) (((register_t)pc) & ~HPPA_PC_PRIV_MASK)
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#ifndef _LOCORE
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/*
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* the trapframe is divided into two parts:
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* one is saved while we are in the physical mode (beginning of the trap),
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* and should be kept as small as possible, since all the interrupts will
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* be lost during this phase, also it must be 64-bytes aligned, per
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* pa-risc stack conventions, and it's dependancies in the code (;
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* the other part is filled out when we are already in the virtual mode,
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* are able to catch interrupts (they are kept pending) and perform
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* other trap activities (like tlb misses).
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*/
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struct trapframe {
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/* the `physical' part of the trapframe */
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u_int tf_t1; /* r22 */
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u_int tf_t2; /* r21 */
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u_int tf_sp; /* r30 */
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u_int tf_t3; /* r20 */
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u_int tf_iisq_head; /* cr17 */
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u_int tf_iisq_tail;
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u_int tf_iioq_head; /* cr18 */
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u_int tf_iioq_tail;
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u_int tf_eiem; /* cr15 */
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u_int tf_ipsw; /* cr22 */
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u_int tf_sr3;
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u_int tf_pidr1; /* cr8 */
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u_int tf_isr; /* cr20 */
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u_int tf_ior; /* cr21 */
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u_int tf_iir; /* cr19 */
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u_int tf_flags;
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/* here starts the `virtual' part */
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u_int tf_sar; /* cr11 */
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u_int tf_r1;
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u_int tf_rp; /* r2 */
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u_int tf_r3; /* frame pointer when -g */
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u_int tf_r4;
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u_int tf_r5;
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u_int tf_r6;
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u_int tf_r7;
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u_int tf_r8;
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u_int tf_r9;
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u_int tf_r10;
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u_int tf_r11;
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u_int tf_r12;
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u_int tf_r13;
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u_int tf_r14;
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u_int tf_r15;
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u_int tf_r16;
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u_int tf_r17;
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u_int tf_r18;
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u_int tf_t4; /* r19 */
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u_int tf_arg3; /* r23 */
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u_int tf_arg2; /* r24 */
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u_int tf_arg1; /* r25 */
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u_int tf_arg0; /* r26 */
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u_int tf_dp; /* r27 */
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u_int tf_ret0; /* r28 */
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u_int tf_ret1; /* r29 */
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u_int tf_r31;
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u_int tf_sr0;
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u_int tf_sr1;
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u_int tf_sr2;
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u_int tf_sr4;
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u_int tf_sr5;
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u_int tf_sr6;
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u_int tf_sr7;
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u_int tf_pidr2; /* cr9 */
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u_int tf_pidr3; /* cr12 */
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u_int tf_pidr4; /* cr13 */
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u_int tf_rctr; /* cr0 */
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u_int tf_ccr; /* cr10 */
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u_int tf_eirr; /* cr23 - DDB */
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u_int tf_hptm; /* cr24 - DDB */
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u_int tf_vtop; /* cr25 - DDB */
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u_int tf_cr28; /* - DDB */
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u_int tf_cr30; /* uaddr */
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u_int tf_pad[3]; /* pad to 256 bytes */
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};
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#endif /* !_LOCORE */
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#endif /* !_HPPA_FRAME_H_ */
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