NetBSD/sys/arch/evbsh5/conf/CAYMAN

176 lines
4.3 KiB
Plaintext

# $NetBSD: CAYMAN,v 1.12 2002/11/23 09:05:04 scw Exp $
#
# Config file for SuperH "CAYMAN" SH-5 Evaluation board
#
include "arch/evbsh5/conf/std.evbsh5.el"
maxusers 8
options INCLUDE_CONFIG_FILE
#ident "CAYMAN-$Revision: 1.12 $"
# Uncomment this to build a 64-bit kernel
#makeoptions SH5_ABI=64
#makeoptions DEFCOPTS="-g"
#makeoptions DEBUG="-g"
options SYMTAB_SPACE=0x40000
options DIAGNOSTIC
options DEBUG
options DDB
#options PORTMASTER
#options UVMHIST
#options UVMHIST_PRINT
options KTRACE # system call tracing via ktrace(1)
options SYSTRACE # system call vetting via systrace(1)
options SYSVMSG
options SYSVSEM
options SYSVSHM
file-system FFS
file-system NFS
file-system KERNFS
file-system MFS
options SOFTDEP
options INET
#options INET6
config netbsd root on ? type ?
options NFS_BOOT_DHCP
pseudo-device loop
pseudo-device bpfilter
pseudo-device pty
pseudo-device rnd
# The mainbus to which all devices attach
mainbus0 at root
#
# The SuperHyway bus is the main interconnect between the constituent
# "modules" which make up an SH-5 system
#
superhyway0 at mainbus0
#
# These are the "modules" present on the Cayman's SH-5
#
cpu0 at superhyway0 pport 0x0d # A single CPU
#emi0 at superhyway0 pport 0x80 # The memory controller module
pbridge0 at superhyway0 pport 0x09 # Peripheral Bridge
#dmac0 at superhyway0 pport 0x0e # DMA controller
femi0 at superhyway0 pport 0x08 # Flash/External memory
sh5pci0 at superhyway0 pport 0x40 # PCI bus
#
# The Peripheral Bridge and all its sub-devices are actually on the same
# silicon as the CPU itself.
#
cprc0 at pbridge0 # Clock, Power & Reset Control
intc0 at pbridge0 # Interrupt controller
options SH5_INTC_IRL_MODE_INDEP # Independent IRL[0-3] inputs
tmu0 at pbridge0 ipl 14 intevt 0x400 # Timer
scif0 at pbridge0 ipl 12 intevt 0x700 # On-chip serial controller
rtc0 at pbridge0 # Battery-backed Date/Time chip
#
# The Clock, Power and Reset controller has a number of sub-devices, only one
# of which is currently used.
#
clock0 at cprc0 # Primary clock generator
#watchdog0 at cprc0 # Watchdog
#power0 at cprc0 # Power Management
#reset0 at cprc0 # Reset controller
#
# The FEMI module (which hangs off the SuperHyway) is actually more than
# just an interface to Flash memory. It's pretty much a complete expansion
# bus in its own right.
#
sysfpga0 at femi0 offset 0x4000000 # The main System FPGA chip
#
# PCIbus devices
#
options PCI_NETBSD_CONFIGURE
pci* at sh5pci? bus ? # pci at SH5 PCI bridge
pci* at pcibus? bus ? # pci at PCIbus bridges
pci* at ppb? bus ? # pci at PCI-PCI bridges
ppb* at pci? dev ? function ? # PCI-PCI Bridges
# Ensoniq card on the Cayman
eap* at pci? dev ? function ? # Ensoniq AudioPCI
# Audio support
audio* at audiobus?
# PCI Network Interfaces
ex* at pci? dev ? function ? # 3Com 90x[BC]
gsip* at pci? dev ? function ? # NS83820 Gigabit Ethernet
options NMBCLUSTERS=8192
# PCI SCSI Interfaces
ahc* at pci? dev ? function ? # Adaptec 7850 SCSI Controller
#
# The Super I/O chip is straight out of the x86 PeeCee world in that
# it implements a bunch if "standard" PeeCee type devices (although
# a few of those are not connected on Cayman).
#
# We make it look like a PeeCee isa bus so that we can re-use all the
# pre-existing NetBSD drivers for the devices implemented in the Super IO.
#
superio0 at sysfpga0 # SMC Super I/O Device
isa0 at superio0 # The ISAbus attachment.
# Onboard SMC91C100 LAN controller
sm0 at sysfpga0
# The Alpha Numeric LED display on the Cayman
alphaled0 at sysfpga0
#
# These are the devices Cayman uses
#
# Note that the addresses and irqs are hard-coded and should really be
# moved into a `knowndevs' structure ...
#
#pckbc0 at isa0 # Keyboard Controller
#pms0 at pckbc0 # Mouse
com0 at isa0 port 0x3f8 irq 4 # PC-style serial ports
com1 at isa0 port 0x2f8 irq 3
lpt0 at isa0 port 0x378 irq 7 # Parallel printer port
#wdc0 at isa0 port 0x1f0 irq 14 flags 0x0 # IDE-style disk controller
# Support for IDE/ATAPI device
#wd* at wdc0 channel ? drive ? flags 0x0000
#atapibus* at wdc0 channel ?
#cd* at atapibus? drive ? flags 0x0000
# The PHY device on the onboard LAN controller
sqphy* at mii? phy ?
# The PHY on the gsip
gphyter* at mii? phy ? # NS83861 Gig-E PHY
#
# The DTF debug interface.
#
#dtfcons0 at mainbus0
#
# Generic SCSI bus
#
scsibus* at scsi?
sd* at scsibus? target ? lun ?