thorpej ba52d7a5d0 Always indirect through the "locoresw" to get the cache ops, since ... there are just far too many combinations to handle with magic #ifdefs in any sane way. Also, add a HitFlushDCache op to the "locoresw", and fill it in as appropriate (it's NULL on MIPS-I, so watch out). These changes ensure that my R4600 Indy (with 2-way cache) gets the correct cache ops when the kernel is built with only MIPS3 support, resulting in a kernel that is significantly more stable.		2001-06-11 23:52:38 +00:00
..
bonito	Memory map and register definitions for the Algorithmics BONITO	2001-06-01 20:29:33 +00:00
conf	Remove 4096-byte gap between .reginfo and .data, suggested by	2001-06-01 03:55:30 +00:00
include	Always indirect through the "locoresw" to get the cache ops, since	2001-06-11 23:52:38 +00:00
mips	Always indirect through the "locoresw" to get the cache ops, since	2001-06-11 23:52:38 +00:00
Makefile	Rework the way kernel include files are installed. In the new method,	1998-06-12 23:22:30 +00:00
Makefile.inc	…