370 lines
9.3 KiB
C
370 lines
9.3 KiB
C
/* $NetBSD: altivec.c,v 1.6 2002/07/28 07:07:45 chs Exp $ */
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/*
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* Copyright (C) 1996 Wolfgang Solfrank.
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* Copyright (C) 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/proc.h>
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#include <sys/systm.h>
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#include <sys/user.h>
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#include <sys/malloc.h>
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#include <sys/pool.h>
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#include <powerpc/altivec.h>
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#include <powerpc/spr.h>
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#include <powerpc/psl.h>
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struct pool vecpool;
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void
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enable_vec()
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{
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struct cpu_info *ci = curcpu();
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struct proc *p = curproc;
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struct pcb *pcb = &p->p_addr->u_pcb;
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struct trapframe *tf = trapframe(p);
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struct vreg *vr = pcb->pcb_vr;
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int msr, scratch;
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KASSERT(pcb->pcb_veccpu == NULL);
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/*
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* Allocate a vreg structure if we haven't done so.
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*/
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if (!(pcb->pcb_flags & PCB_ALTIVEC)) {
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vr = pcb->pcb_vr = pool_get(&vecpool, PR_WAITOK);
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pcb->pcb_flags |= PCB_ALTIVEC;
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/*
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* Initialize the vectors with NaNs
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*/
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for (scratch = 0; scratch < 32; scratch++) {
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vr->vreg[scratch][0] = 0x7FFFDEAD;
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vr->vreg[scratch][1] = 0x7FFFDEAD;
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vr->vreg[scratch][2] = 0x7FFFDEAD;
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vr->vreg[scratch][3] = 0x7FFFDEAD;
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}
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vr->vscr = 0;
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vr->vrsave = tf->vrsave;
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}
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/*
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* Enable AltiVec temporarily (and disable interrupts).
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*/
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msr = mfmsr();
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mtmsr((msr & ~PSL_EE) | PSL_VEC);
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__asm __volatile ("isync");
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if (ci->ci_vecproc) {
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save_vec_cpu();
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}
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KASSERT(curcpu()->ci_vecproc == NULL);
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/*
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* Restore VSCR by first loading it into a vector and then into VSCR.
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* (this needs to done before loading the user's vector registers
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* since we need to use a scratch vector register)
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*/
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__asm __volatile("vxor %2,%2,%2; lvewx %2,%0,%1; mtvscr %2" \
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:: "r"(vr), "r"(offsetof(struct vreg, vscr)), "n"(0));
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/*
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* VRSAVE will be restored when trap frame returns
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*/
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tf->vrsave = vr->vrsave;
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#define LVX(n,vr) __asm /*__volatile*/("lvx %2,%0,%1" \
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:: "r"(vr), "r"(offsetof(struct vreg, vreg[n])), "n"(n));
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/*
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* Load all 32 vector registers
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*/
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LVX( 0,vr); LVX( 1,vr); LVX( 2,vr); LVX( 3,vr);
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LVX( 4,vr); LVX( 5,vr); LVX( 6,vr); LVX( 7,vr);
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LVX( 8,vr); LVX( 9,vr); LVX(10,vr); LVX(11,vr);
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LVX(12,vr); LVX(13,vr); LVX(14,vr); LVX(15,vr);
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LVX(16,vr); LVX(17,vr); LVX(18,vr); LVX(19,vr);
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LVX(20,vr); LVX(21,vr); LVX(22,vr); LVX(23,vr);
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LVX(24,vr); LVX(25,vr); LVX(26,vr); LVX(27,vr);
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LVX(28,vr); LVX(29,vr); LVX(30,vr); LVX(31,vr);
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__asm __volatile ("isync");
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/*
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* Enable AltiVec when we return to user-mode.
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* Record the new ownership of the AltiVec unit.
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*/
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tf->srr1 |= PSL_VEC;
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curcpu()->ci_vecproc = p;
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pcb->pcb_veccpu = curcpu();
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__asm __volatile ("sync");
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/*
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* Restore MSR (turn off AltiVec)
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*/
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mtmsr(msr);
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}
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void
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save_vec_cpu(void)
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{
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struct cpu_info *ci = curcpu();
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struct proc *p;
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struct pcb *pcb;
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struct vreg *vr;
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struct trapframe *tf;
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int msr;
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/*
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* Turn on AltiVEC, turn off interrupts.
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*/
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msr = mfmsr();
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mtmsr((msr & ~PSL_EE) | PSL_VEC);
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__asm __volatile ("isync");
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p = ci->ci_vecproc;
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if (p == NULL) {
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goto out;
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}
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pcb = &p->p_addr->u_pcb;
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vr = pcb->pcb_vr;
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tf = trapframe(p);
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#define STVX(n,vr) __asm /*__volatile*/("stvx %2,%0,%1" \
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:: "r"(vr), "r"(offsetof(struct vreg, vreg[n])), "n"(n));
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/*
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* Save the vector registers.
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*/
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STVX( 0,vr); STVX( 1,vr); STVX( 2,vr); STVX( 3,vr);
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STVX( 4,vr); STVX( 5,vr); STVX( 6,vr); STVX( 7,vr);
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STVX( 8,vr); STVX( 9,vr); STVX(10,vr); STVX(11,vr);
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STVX(12,vr); STVX(13,vr); STVX(14,vr); STVX(15,vr);
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STVX(16,vr); STVX(17,vr); STVX(18,vr); STVX(19,vr);
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STVX(20,vr); STVX(21,vr); STVX(22,vr); STVX(23,vr);
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STVX(24,vr); STVX(25,vr); STVX(26,vr); STVX(27,vr);
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STVX(28,vr); STVX(29,vr); STVX(30,vr); STVX(31,vr);
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/*
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* Save VSCR (this needs to be done after save the vector registers
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* since we need to use one as scratch).
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*/
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__asm __volatile("mfvscr %2; stvewx %2,%0,%1" \
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:: "r"(vr), "r"(offsetof(struct vreg, vscr)), "n"(0));
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/*
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* Save VRSAVE
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*/
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vr->vrsave = tf->vrsave;
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/*
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* Note that we aren't using any CPU resources and stop any
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* data streams.
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*/
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tf->srr1 &= ~PSL_VEC;
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pcb->pcb_veccpu = NULL;
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ci->ci_vecproc = NULL;
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__asm __volatile ("dssall; sync");
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out:
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/*
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* Restore MSR (turn off AltiVec)
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*/
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mtmsr(msr);
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}
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/*
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* Save a process's AltiVEC state to its PCB. The state may be in any CPU.
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* The process must either be curproc or traced by curproc (and stopped).
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* (The point being that the process must not run on another CPU during
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* this function).
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*/
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void
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save_vec_proc(p)
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struct proc *p;
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{
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struct pcb *pcb = &p->p_addr->u_pcb;
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struct cpu_info *ci = curcpu();
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/*
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* If it's already in the PCB, there's nothing to do.
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*/
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if (pcb->pcb_veccpu == NULL) {
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return;
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}
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/*
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* If the state is in the current CPU, just flush the current CPU's
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* state.
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*/
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if (p == ci->ci_vecproc) {
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save_vec_cpu();
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return;
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}
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#ifdef MULTIPROCESSOR
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/*
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* It must be on another CPU, flush it from there.
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*/
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mp_save_vec_proc(p);
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#endif
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}
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#define ZERO_VEC 19
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void
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vzeropage(paddr_t pa)
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{
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const paddr_t ea = pa + NBPG;
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uint32_t vec[7], *vp = (void *) roundup((uintptr_t) vec, 16);
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uint32_t omsr, msr;
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__asm __volatile("mfmsr %0" : "=r"(omsr) :);
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/*
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* Turn on AltiVec, turn off interrupts.
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*/
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msr = (omsr & ~PSL_EE) | PSL_VEC;
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__asm __volatile("sync; mtmsr %0; isync" :: "r"(msr));
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/*
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* Save the VEC register we are going to use before we disable
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* relocation.
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*/
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__asm("stvx %1,0,%0" :: "r"(vp), "n"(ZERO_VEC));
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__asm("vxor %0,%0,%0" :: "n"(ZERO_VEC));
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/*
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* Turn off data relocation (DMMU off).
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*/
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msr &= ~PSL_DR;
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__asm __volatile("sync; mtmsr %0; isync" :: "r"(msr));
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/*
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* Zero the page using a single cache line.
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*/
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do {
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__asm("stvx %2,%0,%1" :: "r"(pa), "r"( 0), "n"(ZERO_VEC));
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__asm("stvxl %2,%0,%1" :: "r"(pa), "r"(16), "n"(ZERO_VEC));
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__asm("stvx %2,%0,%1" :: "r"(pa), "r"(32), "n"(ZERO_VEC));
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__asm("stvxl %2,%0,%1" :: "r"(pa), "r"(48), "n"(ZERO_VEC));
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pa += 64;
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} while (pa < ea);
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/*
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* Restore data relocation (DMMU on);
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*/
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msr |= PSL_DR;
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__asm __volatile("sync; mtmsr %0; isync" :: "r"(msr));
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/*
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* Restore VEC register (now that we can access the stack again).
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*/
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__asm("lvx %1,0,%0" :: "r"(vp), "n"(ZERO_VEC));
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/*
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* Restore old MSR (AltiVec OFF).
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*/
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__asm __volatile("sync; mtmsr %0; isync" :: "r"(omsr));
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}
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#define LO_VEC 16
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#define HI_VEC 17
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void
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vcopypage(paddr_t dst, paddr_t src)
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{
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const paddr_t edst = dst + NBPG;
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uint32_t vec[11], *vp = (void *) roundup((uintptr_t) vec, 16);
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uint32_t omsr, msr;
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__asm __volatile("mfmsr %0" : "=r"(omsr) :);
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/*
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* Turn on AltiVec, turn off interrupts.
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*/
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msr = (omsr & ~PSL_EE) | PSL_VEC;
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__asm __volatile("sync; mtmsr %0; isync" :: "r"(msr));
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/*
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* Save the VEC registers we will be using before we disable
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* relocation.
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*/
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__asm("stvx %2,%1,%0" :: "r"(vp), "r"( 0), "n"(LO_VEC));
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__asm("stvx %2,%1,%0" :: "r"(vp), "r"(16), "n"(HI_VEC));
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/*
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* Turn off data relocation (DMMU off).
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*/
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msr &= ~PSL_DR;
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__asm __volatile("sync; mtmsr %0; isync" :: "r"(msr));
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/*
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* Copy the page using a single cache line. On most PPCs, two
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* vector registers occupy one cache line.
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*/
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do {
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__asm("lvx %2,%0,%1" :: "r"(src), "r"( 0), "n"(LO_VEC));
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__asm("stvx %2,%0,%1" :: "r"(dst), "r"( 0), "n"(LO_VEC));
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__asm("lvxl %2,%0,%1" :: "r"(src), "r"(16), "n"(HI_VEC));
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__asm("stvxl %2,%0,%1" :: "r"(dst), "r"(16), "n"(HI_VEC));
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src += 32;
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dst += 32;
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} while (dst < edst);
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/*
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* Restore data relocation (DMMU on);
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*/
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msr |= PSL_DR;
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__asm __volatile("sync; mtmsr %0; isync" :: "r"(msr));
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/*
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* Restore VEC registers (now that we can access the stack again).
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*/
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__asm("lvx %2,%1,%0" :: "r"(vp), "r"( 0), "n"(LO_VEC));
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__asm("lvx %2,%1,%0" :: "r"(vp), "r"(16), "n"(HI_VEC));
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/*
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* Restore old MSR (AltiVec OFF).
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*/
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__asm __volatile("sync; mtmsr %0; isync" :: "r"(omsr));
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}
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void
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init_vec(void)
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{
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pool_init(&vecpool, sizeof(struct vreg), 16, 0, 0, "vecpl", NULL);
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}
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