494 lines
10 KiB
C
494 lines
10 KiB
C
/* $NetBSD: zs.c,v 1.9 1996/10/13 03:30:27 christos Exp $ */
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/*
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* Copyright (c) 1995 Gordon W. Ross
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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* 4. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Gordon Ross
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Zilog Z8530 Dual UART driver (machine-dependent part)
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*
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* Runs two serial lines per chip using slave drivers.
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* Plain tty/async lines use the zs_async slave.
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*
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* Modified for NetBSD/mvme68k by Jason R. Thorpe <thorpej@NetBSD.ORG>
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/proc.h>
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#include <sys/device.h>
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#include <sys/conf.h>
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#include <sys/file.h>
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#include <sys/ioctl.h>
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#include <sys/tty.h>
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#include <sys/time.h>
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#include <sys/kernel.h>
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#include <sys/syslog.h>
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#include <dev/cons.h>
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#include <dev/ic/z8530reg.h>
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#include <machine/z8530var.h>
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#include <machine/cpu.h>
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#include <mvme68k/dev/zsvar.h>
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static u_long zs_sir; /* software interrupt cookie */
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/* Flags from zscnprobe() */
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static int zs_hwflags[NZS][2];
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/* Default speed for each channel */
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static int zs_defspeed[NZS][2] = {
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{ 9600, /* port 1 */
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9600 }, /* port 2 */
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{ 9600, /* port 3 */
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9600 }, /* port 4 */
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};
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static struct zs_chanstate zs_conschan_store;
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static struct zs_chanstate *zs_conschan;
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u_char zs_init_reg[16] = {
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0, /* 0: CMD (reset, etc.) */
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ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE,
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0x18 + ZSHARD_PRI, /* IVECT */
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ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
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ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
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ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
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0, /* 6: TXSYNC/SYNCLO */
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0, /* 7: RXSYNC/SYNCHI */
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0, /* 8: alias for data port */
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ZSWR9_MASTER_IE,
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0, /*10: Misc. TX/RX control bits */
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ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
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14, /*12: BAUDLO (default=9600) */
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0, /*13: BAUDHI (default=9600) */
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ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA,
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ZSWR15_BREAK_IE | ZSWR15_DCD_IE,
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};
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/****************************************************************
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* Autoconfig
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****************************************************************/
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/* Definition of the driver for autoconfig. */
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static int zsc_print __P((void *, const char *name));
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struct cfdriver zsc_cd = {
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NULL, "zsc", DV_DULL
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};
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/*
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* Configure children of an SCC.
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*/
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void
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zs_config(zsc, chan_addr)
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struct zsc_softc *zsc;
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struct zschan *(*chan_addr) __P((int, int));
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{
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struct zsc_attach_args zsc_args;
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volatile struct zschan *zc;
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struct zs_chanstate *cs;
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int zsc_unit, channel, s;
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u_char reset;
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zsc_unit = zsc->zsc_dev.dv_unit;
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printf(": Zilog 8530 SCC\n");
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/*
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* Initialize software state for each channel.
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*/
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for (channel = 0; channel < 2; channel++) {
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cs = &zsc->zsc_cs[channel];
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/*
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* If we're the console, copy the channel state, and
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* adjust the console channel pointer.
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*/
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if (zs_hwflags[zsc_unit][channel] & ZS_HWFLAG_CONSOLE) {
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bcopy(zs_conschan, cs, sizeof(struct zs_chanstate));
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zs_conschan = cs;
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} else {
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zc = (*chan_addr)(zsc_unit, channel);
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cs->cs_reg_csr = &zc->zc_csr;
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cs->cs_reg_data = &zc->zc_data;
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/* Define BAUD rate clock for the MI code. */
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cs->cs_brg_clk = PCLK / 16;
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cs->cs_defspeed = zs_defspeed[zsc_unit][channel];
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bcopy(zs_init_reg, cs->cs_creg, 16);
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bcopy(zs_init_reg, cs->cs_preg, 16);
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}
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cs->cs_channel = channel;
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cs->cs_private = NULL;
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cs->cs_ops = &zsops_null;
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/*
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* Clear the master interrupt enable.
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* The INTENA is common to both channels,
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* so just do it on the A channel.
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*/
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if (channel == 0) {
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zs_write_reg(cs, 9, 0);
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}
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/*
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* Look for a child driver for this channel.
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* The child attach will setup the hardware.
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*/
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zsc_args.channel = channel;
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zsc_args.hwflags = zs_hwflags[zsc_unit][channel];
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if (config_found(&zsc->zsc_dev, (void *)&zsc_args,
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zsc_print) == NULL) {
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/* No sub-driver. Just reset it. */
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reset = (channel == 0) ?
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ZSWR9_A_RESET : ZSWR9_B_RESET;
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s = splzs();
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zs_write_reg(cs, 9, reset);
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splx(s);
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}
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}
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/*
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* Allocate a software interrupt cookie. Note that the argument
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* "zsc" is never actually used in the software interrupt
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* handler.
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*/
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if (zs_sir == 0)
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zs_sir = allocate_sir(zssoft, zsc);
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}
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static int
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zsc_print(aux, name)
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void *aux;
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const char *name;
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{
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struct zsc_attach_args *args = aux;
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if (name != NULL)
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printf("%s: ", name);
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if (args->channel != -1)
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printf(" channel %d", args->channel);
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return UNCONF;
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}
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int
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zshard(arg)
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void *arg;
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{
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struct zsc_softc *zsc;
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int unit, rval;
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rval = 0;
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for (unit = 0; unit < zsc_cd.cd_ndevs; ++unit) {
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zsc = zsc_cd.cd_devs[unit];
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if (zsc != NULL) {
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rval |= zsc_intr_hard(zsc);
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}
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}
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return (rval);
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}
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int zssoftpending;
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void
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zsc_req_softint(zsc)
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struct zsc_softc *zsc;
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{
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if (zssoftpending == 0) {
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/* We are at splzs here, so no need to lock. */
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zssoftpending = 1;
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setsoftint(zs_sir);
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}
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}
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int
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zssoft(arg)
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void *arg;
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{
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struct zsc_softc *zsc;
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int unit;
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/* This is not the only ISR on this IPL. */
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if (zssoftpending == 0)
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return (0);
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/*
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* The soft intr. bit will be set by zshard only if
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* the variable zssoftpending is zero.
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*/
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zssoftpending = 0;
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for (unit = 0; unit < zsc_cd.cd_ndevs; ++unit) {
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zsc = zsc_cd.cd_devs[unit];
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if (zsc != NULL) {
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(void) zsc_intr_soft(zsc);
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}
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}
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return (1);
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}
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/*
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* Read or write the chip with suitable delays.
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*/
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u_char
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zs_read_reg(cs, reg)
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struct zs_chanstate *cs;
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u_char reg;
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{
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u_char val;
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*cs->cs_reg_csr = reg;
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ZS_DELAY();
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val = *cs->cs_reg_csr;
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ZS_DELAY();
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return val;
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}
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void
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zs_write_reg(cs, reg, val)
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struct zs_chanstate *cs;
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u_char reg, val;
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{
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*cs->cs_reg_csr = reg;
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ZS_DELAY();
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*cs->cs_reg_csr = val;
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ZS_DELAY();
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}
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u_char zs_read_csr(cs)
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struct zs_chanstate *cs;
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{
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register u_char v;
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v = *cs->cs_reg_csr;
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ZS_DELAY();
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return v;
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}
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u_char zs_read_data(cs)
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struct zs_chanstate *cs;
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{
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register u_char v;
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v = *cs->cs_reg_data;
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ZS_DELAY();
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return v;
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}
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void zs_write_csr(cs, val)
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struct zs_chanstate *cs;
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u_char val;
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{
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*cs->cs_reg_csr = val;
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ZS_DELAY();
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}
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void zs_write_data(cs, val)
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struct zs_chanstate *cs;
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u_char val;
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{
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*cs->cs_reg_data = val;
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ZS_DELAY();
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}
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/****************************************************************
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* Console support functions (MVME specific!)
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****************************************************************/
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/*
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* Polled input char.
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*/
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int
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zs_getc(arg)
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void *arg;
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{
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register struct zs_chanstate *cs = arg;
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register int s, c, rr0, stat;
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s = splhigh();
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top:
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/* Wait for a character to arrive. */
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do {
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rr0 = *cs->cs_reg_csr;
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ZS_DELAY();
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} while ((rr0 & ZSRR0_RX_READY) == 0);
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/* Read error register. */
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stat = zs_read_reg(cs, 1) & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE);
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if (stat) {
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zs_write_csr(cs, ZSM_RESET_ERR);
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goto top;
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}
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/* Read character. */
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c = *cs->cs_reg_data;
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ZS_DELAY();
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splx(s);
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return (c);
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}
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/*
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* Polled output char.
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*/
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void
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zs_putc(arg, c)
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void *arg;
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int c;
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{
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register struct zs_chanstate *cs = arg;
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register int s, rr0;
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s = splhigh();
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/* Wait for transmitter to become ready. */
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do {
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rr0 = *cs->cs_reg_csr;
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ZS_DELAY();
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} while ((rr0 & ZSRR0_TX_READY) == 0);
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*cs->cs_reg_data = c;
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ZS_DELAY();
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splx(s);
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}
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/*
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* Common parts of console init.
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*/
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void
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zs_cnconfig(zsc_unit, channel, zcp)
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int zsc_unit, channel;
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struct zschan *zcp;
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{
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volatile struct zschan *zc = (volatile struct zschan *)zcp;
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struct zs_chanstate *cs;
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/*
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* Pointer to channel state. Later, the console channel
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* state is copied into the softc, and the console channel
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* pointer adjusted to point to the new copy.
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*/
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zs_conschan = cs = &zs_conschan_store;
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zs_hwflags[zsc_unit][channel] = ZS_HWFLAG_CONSOLE;
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cs->cs_reg_csr = &zc->zc_csr;
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cs->cs_reg_data = &zc->zc_data;
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cs->cs_channel = channel;
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cs->cs_private = NULL;
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cs->cs_ops = &zsops_null;
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/* Define BAUD rate clock for the MI code. */
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cs->cs_brg_clk = PCLK / 16;
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cs->cs_defspeed = zs_defspeed[zsc_unit][channel];
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bcopy(zs_init_reg, cs->cs_creg, 16);
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bcopy(zs_init_reg, cs->cs_preg, 16);
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/*
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* Clear the master interrupt enable.
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* The INTENA is common to both channels,
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* so just do it on the A channel.
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*/
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if (channel == 0) {
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zs_write_reg(cs, 9, 0);
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}
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/* Reset the SCC chip. */
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zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
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/* Initialize a few important registers. */
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zs_write_reg(cs, 10, cs->cs_creg[10]);
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zs_write_reg(cs, 11, cs->cs_creg[11]);
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zs_write_reg(cs, 14, cs->cs_creg[14]);
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/* Assert DTR and RTS. */
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cs->cs_creg[5] |= (ZSWR5_DTR | ZSWR5_RTS);
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cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS);
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zs_write_reg(cs, 5, cs->cs_creg[5]);
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}
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/*
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* Polled console input putchar.
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*/
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int
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zscngetc(dev)
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dev_t dev;
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{
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register volatile struct zs_chanstate *cs = zs_conschan;
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register int c;
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c = zs_getc(cs);
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return (c);
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}
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/*
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* Polled console output putchar.
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*/
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void
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zscnputc(dev, c)
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dev_t dev;
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int c;
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{
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register volatile struct zs_chanstate *cs = zs_conschan;
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zs_putc(cs, c);
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}
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/*
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* Handle user request to enter kernel debugger.
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*/
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void
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zs_abort()
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{
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register volatile struct zs_chanstate *cs = zs_conschan;
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int rr0;
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/* Wait for end of break to avoid PROM abort. */
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/* XXX - Limit the wait? */
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do {
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rr0 = *cs->cs_reg_csr;
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ZS_DELAY();
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} while (rr0 & ZSRR0_BREAK);
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mvme68k_abort("SERIAL LINE ABORT");
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}
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