2074c2d050
Add support for ZedBoard evaluation board and Parallella board. * cemac(4) Cadence EMAC/GEM(Gigabit) Ethernet Controller driver based on at91emac
141 lines
4.3 KiB
C
141 lines
4.3 KiB
C
/* $NetBSD: zynq7000_board.c,v 1.1 2015/01/23 12:34:09 hkenken Exp $ */
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/*-
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* Copyright (c) 2015 Genetec Corporation. All rights reserved.
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* Written by Hashimoto Kenichi for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(1, "$NetBSD: zynq7000_board.c,v 1.1 2015/01/23 12:34:09 hkenken Exp $");
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#include "opt_zynq.h"
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#include "arml2cc.h"
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/device.h>
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#include <arm/locore.h>
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#include <arm/cortex/a9tmr_var.h>
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#include <arm/cortex/pl310_var.h>
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#include <arm/mainbus/mainbus.h>
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#include <arm/zynq/zynq7000_var.h>
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#include <arm/zynq/zynq7000_reg.h>
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/*
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* PERIPHCLK_N is an arm root clock divider for MPcore interupt controller.
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* PERIPHCLK_N is equal to, or greater than two.
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* see "Cortex-A9 MPCore Technical Reference Manual" -
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* Chapter 5: Clocks, Resets, and Power Management, 5.1: Clocks.
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*/
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#ifndef PERIPHCLK_N
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#define PERIPHCLK_N 2
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#endif
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bus_space_tag_t zynq7000_ioreg_bst = &zynq_bs_tag;
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bus_space_handle_t zynq7000_ioreg_bsh;
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bus_space_tag_t zynq7000_armcore_bst = &zynq_bs_tag;
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bus_space_handle_t zynq7000_armcore_bsh;
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struct zynq7000_clock_info clk_info = { 0 };
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static void zynq7000_clock_init(struct zynq7000_clock_info *);
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psize_t
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zynq7000_memprobe(void)
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{
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return MEMSIZE * 1024 * 1024;
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}
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void
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zynq7000_bootstrap(vaddr_t iobase)
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{
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int error;
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zynq7000_ioreg_bsh = (bus_space_handle_t) iobase;
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error = bus_space_map(zynq7000_ioreg_bst, ZYNQ7000_IOREG_PBASE,
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ZYNQ7000_IOREG_SIZE, 0, &zynq7000_ioreg_bsh);
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if (error)
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panic("%s: failed to map Zynq %s registers: %d",
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__func__, "io", error);
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zynq7000_armcore_bsh = (bus_space_handle_t) iobase + ZYNQ7000_IOREG_SIZE;
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error = bus_space_map(zynq7000_armcore_bst, ZYNQ7000_ARMCORE_PBASE,
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ZYNQ7000_ARMCORE_SIZE, 0, &zynq7000_armcore_bsh);
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if (error)
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panic("%s: failed to map Zynq %s registers: %d",
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__func__, "armcore", error);
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struct zynq7000_clock_info * const clk = &clk_info;
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zynq7000_clock_init(clk);
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#if NARML2CC > 0
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arml2cc_init(zynq7000_armcore_bst, zynq7000_armcore_bsh, ARMCORE_L2C_BASE);
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#endif
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}
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static void
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zynq7000_clock_init(struct zynq7000_clock_info *clk)
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{
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clk->clk_ps = ZYNQ7000_PS_CLK;
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}
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void
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zynq7000_device_register(device_t self, void *aux)
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{
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prop_dictionary_t dict = device_properties(self);
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if (device_is_a(self, "armperiph")
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&& device_is_a(device_parent(self), "mainbus")) {
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/*
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* XXX KLUDGE ALERT XXX
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* The iot mainbus supplies is completely wrong since it scales
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* addresses by 2. The simpliest remedy is to replace with our
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* bus space used for the armcore regisers (which armperiph uses).
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*/
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struct mainbus_attach_args * const mb = aux;
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mb->mb_iot = zynq7000_armcore_bst;
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return;
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}
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/*
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* We need to tell the A9 Global/Watchdog Timer
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* what frequency it runs at.
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*/
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if (device_is_a(self, "a9tmr") || device_is_a(self, "a9wdt")) {
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prop_dictionary_set_uint32(dict, "frequency",
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666666666 / PERIPHCLK_N);
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return;
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}
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}
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#ifdef MULTIPROCESSOR
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void
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zynq7000_cpu_hatch(struct cpu_info *ci)
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{
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a9tmr_init_cpu_clock(ci);
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}
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#endif
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