d5f7715c70
I have confirmed this commit doesn't affect existing evbarm kernels by comparing binaries.
79 lines
2.9 KiB
C
79 lines
2.9 KiB
C
/*
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* Copyright (c) 2010, 2011 Genetec Corporation. All rights reserved.
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* Written by Hiroyuki Bessho for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_MPCORE_MPCOREREG_H
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#define _ARM_MPCORE_MPCOREREG_H
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/*
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* Private Memory Region
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*/
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#define MPCORE_PMR_SCU 0x0000
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#define MPCORE_PMR_CII 0x0100 /* CPU Interrupt Interface (for current core) */
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#define MPCORE_PMR_CII_CORE(n) (0x0x200 + 0x100 * (n)) /* for core N */
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#define MPCORE_PMR_CII_SIZE 0x100
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#define MPCORE_PMR_TIMER 0x600 /* for current core */
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#define MPCORE_PMR_TIMER_CORE(n) (0x700 + 0x100 * (n)) /* for core N */
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#define MPCORE_PMR_TIMER_SIZE 0x10
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#define MPCORE_PMR_WDOG 0x620
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#define MPCORE_PMR_WDOG_SIZE 0x18
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#define MPCORE_PMR_GID 0x1000 /* Global Interrupt Distributor */
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#define MPCORE_PMR_GID_SIZE 0x1000
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#define MPCORE_PMR_SIZE 0x2000
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/*
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* CPU internal timer and watchdog
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*/
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#define PMR_CLK_LOAD 0x00
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#define PMR_CLK_COUNTER 0x04
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#define PMR_CLK_CONTROL 0x08
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#define CLK_CONTROL_ENABLE __BIT(0)
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#define CLK_CONTROL_AUTOLOAD __BIT(1)
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#define CLK_CONTROL_ITENABLE __BIT(2)
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#define CLK_CONTROL_PRESCALER_SHIFT 8
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#define CLK_CONTROL_PRESCALER_MASK __BITS(CLK_CONTROL_PRESCALER_SHIFT, 15)
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#define PMR_CLK_INTR 0x0c
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#define PMR_WDOG_LOAD 0x00
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#define PMR_WDOG_COUNTER 0x04
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#define PMR_WDOG_COUNTER 0x04
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#define PMR_WDOG_CONTROL 0x08
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#define WDOG_CONTROL_ENABLE __BIT(0)
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#define WDOG_CONTROL_AUTOLOAD __BIT(1)
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#define WDOG_CONTROL_ITENABLE __BIT(2)
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#define WDOG_CONTROL_MODE __BIT(3)
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#define WDOG_CONTROL_PRESCALER_SHIFT 8
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#define WDOG_CONTROL_PRESCALER_MASK __BITS(WDOG_CONTROL_PRESCALER_SHIFT, 15)
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#define PMR_WDOG_INTR 0x0c
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#define PMR_WDOG_RESET 0x10
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#define PMR_WDOG_DISABLE 0x14
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#endif /* _ARM_MPCORE_MPCOREREG_H */
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