49 lines
2.1 KiB
C
49 lines
2.1 KiB
C
/* $NetBSD: mvsoctmrreg.h,v 1.4 2014/02/17 05:11:25 kiyohara Exp $ */
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/*
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* Copyright (c) 2007 KIYOHARA Takashi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MVSOCTMRREG_H_
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#define _MVSOCTMRREG_H_
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#define MVSOCTMR_SIZE 0x100
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#define MVSOCTMR_CTCR 0x00 /* CPU Timers Control */
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#define MVSOCTMR_TESR 0x04 /* CPU Timers Event Status */
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#define MVSOCTMR_RELOAD(n) (0x10 + (n) * 8)/* CPU Timer(n) Reload */
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#define MVSOCTMR_TIMER(n) (0x14 + (n) * 8)/* CPU Timer(n) */
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#define MVSOCTMR_TIMER0 0
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#define MVSOCTMR_TIMER1 1
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#define MVSOCTMR_WATCHDOG 2
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#define MVSOCTMR_TIMER2 4 /* Discovery Innovation only */
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#define MVSOCTMR_TIMER3 5 /* Discovery Innovation only */
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/* CPU Timers Control Register (MVSOCTMR_CTCR) */
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#define MVSOCTMR_CTCR_CPUTIMEREN(n) (1 << ((n) * 2))
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#define MVSOCTMR_CTCR_CPUTIMERAUTO(n) (1 << ((n) * 2 + 1))
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#define MVSOCTMR_CTCR_25MHZEN(n) (1 << ((n) + 11)) /* Armada XP only */
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#endif /* !_MVSOCTMRREG_H_ */
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