348 lines
15 KiB
C
348 lines
15 KiB
C
/* $NetBSD: imx6_ccmreg.h,v 1.3 2015/01/09 09:50:46 ryo Exp $ */
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/*
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* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_IMX_IMX6_CCMREG_H
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#define _ARM_IMX_IMX6_CCMREG_H
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#include <sys/cdefs.h>
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/*
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* PERIPHCLK_N is an arm root clock divider for MPcore interupt controller.
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* PERIPHCLK_N is equal to, or greater than two.
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* see "Cortex-A9 MPCore Technical Reference Manual" -
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* Chapter 5: Clocks, Resets, and Power Management, 5.1: Clocks.
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*/
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#ifndef IMX6_PERIPHCLK_N
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#define IMX6_PERIPHCLK_N 2
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#endif
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#ifndef IMX6_OSC_FREQ
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#define IMX6_OSC_FREQ (24 * 1000 * 1000) /* 24MHz */
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#endif
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#define IMX6_CCM_SIZE 0x8000
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/* 0x00000000 = 0x020c4000 */
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#define CCM_CCR 0x00000000
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#define CCM_CCDR 0x00000004
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#define CCM_CSR 0x00000008
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#define CCM_CCSR 0x0000000c
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#define CCM_CACRR 0x00000010
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#define CCM_CACRR_ARM_PODF __BITS(2, 0)
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#define CCM_CBCDR 0x00000014
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#define CCM_CBCDR_PERIPH_CLK2_PODF __BITS(29, 27)
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/* source of mmdc_ch1_axi_clk_root */
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#define CCM_CBCDR_PERIPH2_CLK_SEL __BIT(26)
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/* source of mmdc_ch0_axi_clk_root */
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#define CCM_CBCDR_PERIPH_CLK_SEL __BIT(25)
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#define CCM_CBCDR_MMDC_CH0_AXI_PODF __BITS(21, 19)
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#define CCM_CBCDR_AXI_PODF __BITS(18, 16)
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#define CCM_CBCDR_AHB_PODF __BITS(12, 10)
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#define CCM_CBCDR_IPG_PODF __BITS(9, 8)
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#define CCM_CBCDR_AXI_ALT_SEL __BIT(7)
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#define CCM_CBCDR_AXI_SEL __BIT(6)
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#define CCM_CBCDR_MMDC_CH1_AXI_PODF __BITS(5, 3)
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#define CCM_CBCDR_PERIPH2_CLK2_PODF __BITS(2, 0)
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#define CCM_CBCMR 0x00000018
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#define CCM_CBCMR_GPU3D_SHADER_PODF __BITS(31, 29)
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#define CCM_CBCMR_GPU3D_CORE_PODF __BITS(28, 26)
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#define CCM_CBCMR_GPU2D_CORE_CLK_PODF __BITS(25, 23)
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#define CCM_CBCMR_PRE_PERIPH2_CLK_SEL __BITS(22, 21)
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#define CCM_CBCMR_PERIPH2_CLK2_SEL __BIT(20)
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#define CCM_CBCMR_PRE_PERIPH_CLK_SEL __BITS(19, 18)
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#define CCM_CBCMR_GPU2D_CLK_SEL __BITS(17, 16)
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#define CCM_CBCMR_VPU_AXI_CLK_SEL __BITS(15, 14)
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#define CCM_CBCMR_PERIPH_CLK2_SEL __BITS(13, 12)
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#define CCM_CBCMR_VDOAXI_CLK_SEL __BIT(11)
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#define CCM_CBCMR_PCIE_AXI_CLK_SE __BIT(10)
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#define CCM_CBCMR_GPU3D_SHADER_CLK_SEL __BITS(9, 8)
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#define CCM_CBCMR_GPU3D_CORE_CLK_SEL __BITS(5, 4)
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#define CCM_CBCMR_GPU3D_AXI_CLK_SEL __BIT(1)
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#define CCM_CBCMR_GPU2D_AXI_CLK_SEL __BIT(0)
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#define CCM_CSCMR1 0x0000001c
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#define CCM_CSCMR1_ACLK_EIM_SLOW_SEL __BITS(30, 29)
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#define CCM_CSCMR1_ACLK_SEL __BITS(28, 27)
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#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF __BITS(25, 23)
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#define CCM_CSCMR1_ACLK_PODF __BITS(22, 20)
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#define CCM_CSCMR1_USDHC4_CLK_SEL __BIT(19)
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#define CCM_CSCMR1_USDHC3_CLK_SEL __BIT(18)
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#define CCM_CSCMR1_USDHC2_CLK_SEL __BIT(17)
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#define CCM_CSCMR1_USDHC1_CLK_SEL __BIT(16)
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#define CCM_CSCMR1_SSI3_CLK_SEL __BITS(15, 14)
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#define CCM_CSCMR1_SSI2_CLK_SEL __BITS(13, 12)
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#define CCM_CSCMR1_SSI1_CLK_SEL __BITS(11, 10)
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#define CCM_CSCMR1_PERCLK_PODF __BITS(5, 0)
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#define CCM_CSCMR2 0x00000020
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#define CCM_CSCMR2_ESAI_CLK_SEL __BITS(20, 19)
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#define CCM_CSCMR2_LDB_DI1_IPU_DIV __BIT(11)
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#define CCM_CSCMR2_LDB_DI0_IPU_DIV __BIT(10)
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#define CCM_CSCMR2_CAN_CLK_PODF __BITS(7, 2)
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#define CCM_CSCDR1 0x00000024
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#define CCM_CSCDR1_VPU_AXI_PODF __BITS(25, 27)
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#define CCM_CSCDR1_USDHC4_PODF __BITS(22, 24)
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#define CCM_CSCDR1_USDHC3_PODF __BITS(19, 21)
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#define CCM_CSCDR1_USDHC2_PODF __BITS(16, 18)
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#define CCM_CSCDR1_USDHC1_PODF __BITS(13, 11)
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#define CCM_CSCDR1_UART_CLK_PODF __BITS(5, 0)
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#define CCM_CS1CDR 0x00000028
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#define CCM_CS2CDR 0x0000002c
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#define CCM_CS2CDR_ENFC_CLK_PODF __BITS(26, 21)
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#define CCM_CS2CDR_ENFC_CLK_PRED __BITS(20, 18)
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#define CCM_CS2CDR_ENFC_CLK_SEL __BITS(17, 16)
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#define CCM_CS2CDR_LDB_DI1_CLK_SEL __BITS(14, 12)
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#define CCM_CS2CDR_LDB_DI0_CLK_SEL __BITS(11, 9)
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#define CCM_CS2CDR_SSI2_CLK_PRED __BITS(8, 6)
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#define CCM_CS2CDR_SSI2_CLK_PODF __BITS(5, 0)
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#define CCM_CDCDR 0x00000030
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#define CCM_CHSCCDR 0x00000034
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#define CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL __BITS(17, 15)
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#define CCM_CHSCCDR_IPU1_DI1_PODF __BITS(14, 12)
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#define CCM_CHSCCDR_IPU1_DI1_CLK_SEL __BITS(11, 9)
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#define CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL __BITS(8, 6)
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#define CCM_CHSCCDR_IPU1_DI0_PODF __BITS(5, 3)
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#define CCM_CHSCCDR_IPU1_DI0_CLK_SEL __BITS(2, 0)
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#define CCM_CSCDR2 0x00000038
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#define CCM_CSCDR3 0x0000003c
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#define CCM_CSCDR3_IPU2_HSP_PODF __BITS(18, 16)
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#define CCM_CSCDR3_IPU2_HSP_CLK_SEL __BITS(15, 14)
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#define CCM_CSCDR3_IPU1_HSP_PODF __BITS(13, 11)
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#define CCM_CSCDR3_IPU1_HSP_CLK_SEL __BITS(10, 9)
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#define CCM_CCGR5 0x0000007c
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#define CCM_CCGR5_UART_SERIAL_CLK_ENABLE(n) __SHIFTIN(n, __BITS(27, 26))
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#define CCM_CCGR5_UART_CLK_ENABLE(n) __SHIFTIN(n, __BITS(25, 24))
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#define CCM_CCGR5_SSI3_CLK_ENABLE(n) __SHIFTIN(n, __BITS(23, 22))
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#define CCM_CCGR5_SSI2_CLK_ENABLE(n) __SHIFTIN(n, __BITS(21, 20))
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#define CCM_CCGR5_SSI1_CLK_ENABLE(n) __SHIFTIN(n, __BITS(19, 18))
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#define CCM_CCGR5_SPDIF_CLK_ENABLE(n) __SHIFTIN(n, __BITS(15, 14))
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#define CCM_CCGR5_SPBA_CLK_ENABLE(n) __SHIFTIN(n, __BITS(13, 12))
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#define CCM_CCGR5_SDMA_CLK_ENABLE(n) __SHIFTIN(n, __BITS(7, 6))
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#define CCM_CCGR5_100M_CLK_ENABLE(n) __SHIFTIN(n, __BITS(5, 4))
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#define CCM_CCGR5_ROM_CLK_ENABLE(n) __SHIFTIN(n, __BITS(1, 0))
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#define CCM_CCGR6 0x00000080
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#define CCM_CCGR6_VPU_CLK_ENABLE(n) __SHIFTIN(n, __BITS(15, 14))
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#define CCM_CCGR6_VDOAXICLK_CLK_ENABLE(n) __SHIFTIN(n, __BITS(13, 12))
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#define CCM_CCGR6_EIM_SLOW_CLK_ENABLE(n) __SHIFTIN(n, __BITS(11, 10))
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#define CCM_CCGR6_USDHC4_CLK_ENABLE(n) __SHIFTIN(n, __BITS(9, 8))
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#define CCM_CCGR6_USDHC3_CLK_ENABLE(n) __SHIFTIN(n, __BITS(7, 6))
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#define CCM_CCGR6_USDHC2_CLK_ENABLE(n) __SHIFTIN(n, __BITS(5, 4))
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#define CCM_CCGR6_USDHC1_CLK_ENABLE(n) __SHIFTIN(n, __BITS(3, 2))
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#define CCM_CCGR6_USBOH3_CLK_ENABLE(n) __SHIFTIN(n, __BITS(1, 0))
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/* 0x00004000 = 0x020c8000 */
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#define CCM_ANALOG_PLL_ARM 0x00004000 /* = 020c8000 */
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#define CCM_ANALOG_PLL_ARM_SET 0x00004004
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#define CCM_ANALOG_PLL_ARM_CLR 0x00004008
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#define CCM_ANALOG_PLL_ARM_TOG 0x0000400c
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#define CCM_ANALOG_PLL_ARM_DIV_SELECT __BITS(6, 0)
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#define CCM_ANALOG_PLL_USB1 0x00004010
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#define CCM_ANALOG_PLL_USB1_SET 0x00004014
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#define CCM_ANALOG_PLL_USB1_CLR 0x00004018
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#define CCM_ANALOG_PLL_USB1_TOG 0x0000401c
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#define CCM_ANALOG_PLL_USB1_DIV_SELECT __BITS(1, 0)
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#define CCM_ANALOG_PLL_USB2 0x00004020
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#define CCM_ANALOG_PLL_USB2_SET 0x00004024
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#define CCM_ANALOG_PLL_USB2_CLR 0x00004028
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#define CCM_ANALOG_PLL_USB2_TOG 0x0000402c
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#define CCM_ANALOG_PLL_USBn_LOCK __BIT(31)
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#define CCM_ANALOG_PLL_USBn_BYPASS __BIT(16)
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#define CCM_ANALOG_PLL_USBn_ENABLE __BIT(13)
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#define CCM_ANALOG_PLL_USBn_POWER __BIT(12)
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#define CCM_ANALOG_PLL_USBn_EN_USB_CLK __BIT(6)
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#define CCM_ANALOG_PLL_USBn_DIV_SELECT(n) __BITS(1, 0)
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#define CCM_ANALOG_PLL_SYS 0x00004030
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#define CCM_ANALOG_PLL_SYS_SET 0x00004034
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#define CCM_ANALOG_PLL_SYS_CLR 0x00004038
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#define CCM_ANALOG_PLL_SYS_TOG 0x0000403c
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#define CCM_ANALOG_PLL_SYS_DIV_SELECT __BIT(0)
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#define CCM_ANALOG_PLL_SYS_SS 0x00004040
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#define CCM_ANALOG_PLL_SYS_NUM 0x00004050
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#define CCM_ANALOG_PLL_SYS_DENOM 0x00004060
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#define CCM_ANALOG_PLL_AUDIO 0x00004070
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#define CCM_ANALOG_PLL_AUDIO_SET 0x00004074
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#define CCM_ANALOG_PLL_AUDIO_CLR 0x00004078
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#define CCM_ANALOG_PLL_AUDIO_TOG 0x0000407c
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#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT __BITS(20, 19)
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#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT __BITS(6, 0)
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#define CCM_ANALOG_PLL_AUDIO_NUM 0x00004080
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#define CCM_ANALOG_PLL_AUDIO_DENOM 0x00004090
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#define CCM_ANALOG_PLL_VIDEO 0x000040a0
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#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT __BITS(20, 19)
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#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT __BITS(6, 0)
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#define CCM_ANALOG_PLL_VIDEO_SET 0x000040a4
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#define CCM_ANALOG_PLL_VIDEO_CLR 0x000040a8
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#define CCM_ANALOG_PLL_VIDEO_TOG 0x000040ac
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#define CCM_ANALOG_PLL_VIDEO_NUM 0x000040b0
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#define CCM_ANALOG_PLL_VIDEO_DENOM 0x000040c0
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#define CCM_ANALOG_PLL_MLB 0x000040d0
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#define CCM_ANALOG_PLL_MLB_SET 0x000040d4
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#define CCM_ANALOG_PLL_MLB_CLR 0x000040d8
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#define CCM_ANALOG_PLL_MLB_TOG 0x000040dc
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#define CCM_ANALOG_PLL_ENET 0x000040e0
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#define CCM_ANALOG_PLL_ENET_SET 0x000040e4
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#define CCM_ANALOG_PLL_ENET_CLR 0x000040e8
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#define CCM_ANALOG_PLL_ENET_TOG 0x000040ec
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#define CCM_ANALOG_PLL_ENET_LOCK __BIT(31)
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#define CCM_ANALOG_PLL_ENET_ENABLE_100M __BIT(20) /* SATA */
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#define CCM_ANALOG_PLL_ENET_ENABLE_125M __BIT(19) /* PCIe */
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#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN __BIT(18)
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#define CCM_ANALOG_PLL_ENET_BYPASS __BIT(16)
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#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(s) __SHIFTIN(s, __BITS(15, 14))
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#define CCM_ANALOG_PLL_ENET_ENABLE __BIT(13) /* Ether */
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#define CCM_ANALOG_PLL_ENET_POWERDOWN __BIT(12)
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#define CCM_ANALOG_PLL_ENET_DIV_SELECT(d) __SHIFTIN(d, __BITS(1, 0))
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#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK __SHIFTIN(3, __BITS(1, 0))
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#define CCM_ANALOG_PFD_480 0x000040f0
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#define CCM_ANALOG_PFD_480_SET 0x000040f4
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#define CCM_ANALOG_PFD_480_CLR 0x000040f8
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#define CCM_ANALOG_PFD_480_TOG 0x000040fc
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#define CCM_ANALOG_PFD_480_PFD3_CLKGATE __BIT(31)
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#define CCM_ANALOG_PFD_480_PFD3_STABLE __BIT(30)
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#define CCM_ANALOG_PFD_480_PFD3_FRAC __BITS(29, 24)
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#define CCM_ANALOG_PFD_480_PFD2_CLKGATE __BIT(23)
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#define CCM_ANALOG_PFD_480_PFD2_STABLE __BIT(22)
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#define CCM_ANALOG_PFD_480_PFD2_FRAC __BITS(21, 16)
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#define CCM_ANALOG_PFD_480_PFD1_CLKGATE __BIT(15)
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#define CCM_ANALOG_PFD_480_PFD1_STABLE __BIT(14)
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#define CCM_ANALOG_PFD_480_PFD1_FRAC __BITS(13, 8)
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#define CCM_ANALOG_PFD_480_PFD0_CLKGATE __BIT(7)
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#define CCM_ANALOG_PFD_480_PFD0_STABLE __BIT(6)
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#define CCM_ANALOG_PFD_480_PFD0_FRAC __BITS(5, 0)
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#define CCM_ANALOG_PFD_528 0x00004100
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#define CCM_ANALOG_PFD_528_SET 0x00004104
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#define CCM_ANALOG_PFD_528_CLR 0x00004108
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#define CCM_ANALOG_PFD_528_TOG 0x0000410c
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#define CCM_ANALOG_PFD_528_PFD2_CLKGATE __BIT(23)
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#define CCM_ANALOG_PFD_528_PFD2_STABLE __BIT(22)
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#define CCM_ANALOG_PFD_528_PFD2_FRAC __BITS(21, 16)
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#define CCM_ANALOG_PFD_528_PFD1_CLKGATE __BIT(15)
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#define CCM_ANALOG_PFD_528_PFD1_STABLE __BIT(14)
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#define CCM_ANALOG_PFD_528_PFD1_FRAC __BITS(13, 8)
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#define CCM_ANALOG_PFD_528_PFD0_CLKGATE __BIT(7)
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#define CCM_ANALOG_PFD_528_PFD0_STABLE __BIT(6)
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#define CCM_ANALOG_PFD_528_PFD0_FRAC __BITS(5, 0)
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#define CCM_ANALOG_MISC0 0x00004150
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#define CCM_ANALOG_MISC0_SET 0x00004154
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#define CCM_ANALOG_MISC0_CLR 0x00004158
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#define CCM_ANALOG_MISC0_TOG 0x0000415C
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#define CCM_ANALOG_MISC2 0x00004170
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#define CCM_ANALOG_MISC2_SET 0x00004174
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#define CCM_ANALOG_MISC2_CLR 0x00004178
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#define CCM_ANALOG_MISC2_TOG 0x0000417C
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#define CCM_TEMPMON_TEMPSENSE0 0x00004180
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#define CCM_TEMPMON_TEMPSENSE0_ALARM_VALUE __BIT(31, 30)
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#define CCM_TEMPMON_TEMPSENSE0_TEMP_CNT __BITS(19, 8)
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#define CCM_TEMPMON_TEMPSENSE0_FINISHED __BIT(2)
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#define CCM_TEMPMON_TEMPSENSE0_MEASURE_TEMP __BIT(1)
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#define CCM_TEMPMON_TEMPSENSE0_POWER_DOWN __BIT(0)
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#define CCM_TEMPMON_TEMPSENSE1 0x00004180
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#define CCM_TEMPMON_TEMPSENSE1_MEASURE_FREQ __BITS(15, 0)
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#define USB_ANALOG_USB1_VBUS_DETECT 0x000041a0
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#define USB_ANALOG_USB1_CHRG_DETECT 0x000041b0
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#define USB_ANALOG_USB_CHRG_DETECT_EN_B __BIT(20)
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#define USB_ANALOG_USB_CHRG_DETECT_CHK_CHRG_B __BIT(19)
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#define USB_ANALOG_USB_CHRG_DETECT_CHK_CHK_CONTACT __BIT(18)
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#define USB_ANALOG_USB1_VBUS_DETECT_STAT 0x000041c0
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#define USB_ANALOG_USB1_CHRG_DETECT_STAT 0x000041d0
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#define USB_ANALOG_USB1_MISC 0x000041f0
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#define USB_ANALOG_USB2_VBUS_DETECT 0x00004200
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#define USB_ANALOG_USB2_CHRG_DETECT 0x00004210
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#define USB_ANALOG_USB2_VBUS_DETECT_STAT 0x00004220
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#define USB_ANALOG_USB2_CHRG_DETECT_STAT 0x00004230
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#define USB_ANALOG_USB2_MISC 0x00004250
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#define USB_ANALOG_DIGPROG 0x00004260
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#define USB_ANALOG_DIGPROG_SOLOLITE 0x00004280
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#define USB_ANALOG_DIGPROG_MAJOR __BITS(23, 8)
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#define USB_ANALOG_DIGPROG_MINOR __BITS(7, 0)
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/* 0x00005000 = 0x020c9000 */
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#define USBPHY1_PWD 0x00005000 /* = 020c9000 */
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#define USBPHY1_PWD_SET 0x00005004
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#define USBPHY1_PWD_CLR 0x00005008
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#define USBPHY1_PWD_TOG 0x0000500c
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#define USBPHY1_TX 0x00005010
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#define USBPHY1_TX_SET 0x00005014
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#define USBPHY1_TX_CLR 0x00005018
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#define USBPHY1_TX_TOG 0x0000501c
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#define USBPHY_TX_USBPHY_TX_EDGECTRL __BITS(28, 26)
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#define USBPHY_TX_TXCAL45DP __BITS(19, 16)
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#define USBPHY_TX_TXCAL45DN __BITS(11, 8)
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#define USBPHY_TX_D_CAL __BITS(3, 0)
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#define USBPHY1_RX 0x00005020
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#define USBPHY1_RX_SET 0x00005024
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#define USBPHY1_RX_CLR 0x00005028
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#define USBPHY1_RX_TOG 0x0000502c
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#define USBPHY1_CTRL 0x00005030
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#define USBPHY1_CTRL_SET 0x00005034
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#define USBPHY1_CTRL_CLR 0x00005038
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#define USBPHY1_CTRL_TOG 0x0000503c
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#define USBPHY_CTRL_SFTRST __BIT(31)
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#define USBPHY_CTRL_CLKGATE __BIT(30)
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#define USBPHY_CTRL_ENUTMILEVEL3 __BIT(15)
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#define USBPHY_CTRL_ENUTMILEVEL2 __BIT(14)
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#define USBPHY1_STATUS 0x00005040
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#define USBPHY1_DEBUG 0x00005050
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#define USBPHY1_DEBUG0_STATUS 0x00005060
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#define USBPHY1_DEBUG1 0x00005070
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#define USBPHY1_VERSION 0x00005080
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#define USBPHY2_PWD 0x00006000 /* = 020ca000 */
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#define USBPHY2_PWD_SET 0x00006004
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#define USBPHY2_PWD_CLR 0x00006008
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#define USBPHY2_PWD_TOG 0x0000600c
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#define USBPHY2_TX 0x00006010
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#define USBPHY2_TX_SET 0x00006014
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#define USBPHY2_TX_CLR 0x00006018
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#define USBPHY2_TX_TOG 0x0000601c
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#define USBPHY2_RX 0x00006020
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#define USBPHY2_RX_SET 0x00006024
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#define USBPHY2_RX_CLR 0x00006028
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#define USBPHY2_RX_TOG 0x0000602c
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#define USBPHY2_CTRL 0x00006030
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#define USBPHY2_CTRL_SET 0x00006034
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#define USBPHY2_CTRL_CLR 0x00006038
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#define USBPHY2_CTRL_TOG 0x0000603c
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#define USBPHY2_STATUS 0x00006040
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#define USBPHY2_DEBUG 0x00006050
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#define USBPHY2_DEBUG0_STATUS 0x00006060
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#define USBPHY2_DEBUG1 0x00006070
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#define USBPHY2_VERSION 0x00006080
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#endif /* _ARM_IMX_IMX6_CCMREG_H */
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