433506fb11
- Fix typo: AHBH should be APBH - Add support for APBX DMA - New function apbdma_wait(); wait for DMA completion
139 lines
5.2 KiB
C
139 lines
5.2 KiB
C
/* $Id: imx23_apbdmavar.h,v 1.2 2015/01/10 12:13:00 jmcneill Exp $ */
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/*
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* Copyright (c) 2013 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Petri Laakso.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_IMX_IMX23_APBDMAVAR_H_
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#define _ARM_IMX_IMX23_APBDMAVAR_H_
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#include <sys/cdefs.h>
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#include <sys/types.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/mutex.h>
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/* DMA command control register bits. */
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#define APBDMA_CMD_XFER_COUNT __BITS(31, 16)
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#define APBDMA_CMD_CMDPIOWORDS __BITS(15, 12)
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#define APBDMA_CMD_RESERVED __BITS(11, 9)
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#define APBDMA_CMD_HALTONTERMINATE __BIT(8)
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#define APBDMA_CMD_WAIT4ENDCMD __BIT(7)
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#define APBDMA_CMD_SEMAPHORE __BIT(6)
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#define APBDMA_CMD_NANDWAIT4READY __BIT(5)
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#define APBDMA_CMD_NANDLOCK __BIT(4)
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#define APBDMA_CMD_IRQONCMPLT __BIT(3)
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#define APBDMA_CMD_CHAIN __BIT(2)
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#define APBDMA_CMD_COMMAND __BITS(1, 0)
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/* DMA command types. */
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#define APBDMA_CMD_NO_DMA_XFER 0
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#define APBDMA_CMD_DMA_WRITE 1
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#define APBDMA_CMD_DMA_READ 2
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#define APBDMA_CMD_DMA_SENSE 3
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/* Flags. */
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#define F_APBH_DMA __BIT(0)
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#define F_APBX_DMA __BIT(1)
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/* Number of channels. */
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#define AHBH_DMA_CHANNELS 8
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#define AHBX_DMA_CHANNELS 16
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/* APBH DMA channel assignments. */
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#define APBH_DMA_CHANNEL_RES0 0 /* Reserved. */
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#define APBH_DMA_CHANNEL_SSP1 1 /* SSP1. */
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#define APBH_DMA_CHANNEL_SSP2 2 /* SSP2. */
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#define APBH_DMA_CHANNEL_RES1 3 /* Reserved. */
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#define APBH_DMA_CHANNEL_NAND_DEVICE0 4 /* NAND_DEVICE0. */
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#define APBH_DMA_CHANNEL_NAND_DEVICE1 5 /* NAND_DEVICE1. */
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#define APBH_DMA_CHANNEL_NAND_DEVICE2 6 /* NAND_DEVICE2. */
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#define APBH_DMA_CHANNEL_NAND_DEVICE3 7 /* NAND_DEVICE3. */
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/* APBX DMA channel assignments. */
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#define APBX_DMA_CHANNEL_AUDIO_ADC 0 /* Audio ADCs. */
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#define APBX_DMA_CHANNEL_AUDIO_DAC 1 /* Audio DACs. */
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#define APBX_DMA_CHANNEL_SPDIF_TX 2 /* SPDIF TX. */
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#define APBX_DMA_CHANNEL_I2C 3 /* I2C. */
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#define APBX_DMA_CHANNEL_SAIF1 4 /* SAIF1. */
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#define APBX_DMA_CHANNEL_RES0 5 /* Reserved. */
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#define APBX_DMA_CHANNEL_UART1_RX 6 /* UART1 RX, IrDA RX. */
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#define APBX_DMA_CHANNEL_UART1_TX 7 /* UART1 TX, IrDA TX. */
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#define APBX_DMA_CHANNEL_UART2_RX 8 /* UART2 RX. */
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#define APBX_DMA_CHANNEL_UART2_TX 9 /* UART2 TX. */
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#define APBX_DMA_CHANNEL_SAIF2 10 /* SAIF2. */
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#define APBX_DMA_CHANNEL_RES1 11 /* Reserved. */
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#define APBX_DMA_CHANNEL_RES2 12 /* Reserved. */
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#define APBX_DMA_CHANNEL_RES3 13 /* Reserved. */
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#define APBX_DMA_CHANNEL_RES4 14 /* Reserved. */
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#define APBX_DMA_CHANNEL_RES5 15 /* Reserved. */
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/* Return codes for apbdma_intr_status() */
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#define DMA_IRQ_CMDCMPLT 0
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#define DMA_IRQ_TERM 1
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#define DMA_IRQ_BUS_ERROR 2
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#define PIO_WORDS_MAX 15
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/*
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* How many PIO words apbdma_command structure has.
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*
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* XXX: If you change this value, make sure drivers are prepared for that.
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* That means you have to allocate enough DMA memory for command chains.
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*/
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#define PIO_WORDS 3
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typedef struct apbdma_softc {
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device_t sc_dev;
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bus_dma_tag_t sc_dmat;
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bus_space_handle_t sc_ioh;
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bus_space_tag_t sc_iot;
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kmutex_t sc_lock;
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u_int flags;
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} *apbdma_softc_t;
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typedef struct apbdma_command {
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void *next; /* Physical address. */
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uint32_t control;
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void *buffer; /* Physical address. */
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uint32_t pio_words[PIO_WORDS];
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} *apbdma_command_t;
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void apbdma_cmd_chain(apbdma_command_t, apbdma_command_t, void *, bus_dmamap_t);
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void apbdma_cmd_buf(apbdma_command_t, bus_addr_t, bus_dmamap_t);
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void apbdma_chan_init(struct apbdma_softc *, unsigned int);
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void apbdma_chan_set_chain(struct apbdma_softc *, unsigned int, bus_dmamap_t);
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void apbdma_run(struct apbdma_softc *, unsigned int);
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void apbdma_ack_intr(struct apbdma_softc *, unsigned int);
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void apbdma_ack_error_intr(struct apbdma_softc *, unsigned int);
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unsigned int apbdma_intr_status(struct apbdma_softc *, unsigned int);
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void apbdma_chan_reset(struct apbdma_softc *, unsigned int);
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void apbdma_wait(struct apbdma_softc *, unsigned int);
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#endif /* !_ARM_IMX_IMX23_APBDMAVAR_H_ */
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