273 lines
8.4 KiB
C
273 lines
8.4 KiB
C
/* $Id: at91sam9261reg.h,v 1.3 2009/10/23 06:53:13 snj Exp $ */
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/* $NetBSD: at91sam9261reg.h,v 1.3 2009/10/23 06:53:13 snj Exp $ */
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/*
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* Copyright (c) 2007 Embedtronics Oy
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _AT91SAM9261REG_H_
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#define _AT91SAM9261REG_H_
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#include <arm/at91/at91reg.h>
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/*
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* Physical memory map for the AT91SAM9261
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*/
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/*
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* ffff ffff ---------------------------
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* System Controller
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* ffff c000 ---------------------------
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* Peripherals
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* fffa 0000 ---------------------------
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* (not used)
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* 9000 0000 ---------------------------
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* EBI Chip Select 7
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* 8000 0000 ---------------------------
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* EBI Chip Select 6 / CF logic
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* 7000 0000 ---------------------------
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* EBI Chip Select 5 / CF logic
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* 6000 0000 ---------------------------
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* EBI Chip Select 4 / CF logic
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* 5000 0000 ---------------------------
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* EBI Chip Select 3 / NANDFlash
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* 4000 0000 ---------------------------
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* EBI Chip Select 2
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* 3000 0000 ---------------------------
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* EBI Chip Select 1 / SDRAM
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* 2000 0000 ---------------------------
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* EBI Chip Select 0 / BFC
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* 1000 0000 ---------------------------
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* Reserved
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* 0070 0000 ---------------------------
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* LCD User Interface
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* 0060 0000 ---------------------------
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* UHP User Interface
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* 0050 0000 ---------------------------
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* Reserved
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* 0040 0000 ---------------------------
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* SRAM
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* 0030 0000 ---------------------------
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* DTCM
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* 0020 0000 ---------------------------
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* ITCM
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* 0010 0000 ---------------------------
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* Boot memory
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* 0000 0000 ---------------------------
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*/
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/*
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* Virtual memory map for the AT91SAM9261 integrated devices
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*
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* Some device registers are statically mapped on upper address region.
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* because we have to access them before bus_space is initialized.
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* Most devices are dynamicaly mapped by bus_space_map(). In this case,
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* the actual mapped (virtual) address are not cared by device drivers.
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*/
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/*
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* FFFF FFFF ---------------------------
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* APB bus (1 MB)
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* FFF0 0000 ---------------------------
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* (not used)
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* E000 0000 ---------------------------
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* Kernel text and data
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* C000 0000 ---------------------------
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* (not used)
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* 0000 0000 ---------------------------
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*
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*/
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#define AT91SAM9261_BOOTMEM_BASE 0x00000000U
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#define AT91SAM9261_BOOTMEM_SIZE 0x00100000U
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#define AT91SAM9261_ROM_BASE 0x00100000U
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#define AT91SAM9261_ROM_SIZE 0x00100000U
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#define AT91SAM9261_SRAM_BASE 0x00300000U
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#define AT91SAM9261_SRAM_SIZE 0x00028000U
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#define AT91SAM9261_UHP_BASE 0x00500000U
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#define AT91SAM9261_UHP_SIZE 0x00100000U
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#define AT91SAM9261_LCD_BASE 0x00600000U
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#define AT91SAM9261_LCD_SIZE 0x00100000U
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#define AT91SAM9261_CS0_BASE 0x10000000U
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#define AT91SAM9261_CS0_SIZE 0x10000000U
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#define AT91SAM9261_CS1_BASE 0x20000000U
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#define AT91SAM9261_CS1_SIZE 0x10000000U
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#define AT91SAM9261_SDRAM_BASE AT91SAM9261_CS1_BASE
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#define AT91SAM9261_CS2_BASE 0x30000000U
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#define AT91SAM9261_CS2_SIZE 0x10000000U
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#define AT91SAM9261_CS3_BASE 0x40000000U
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#define AT91SAM9261_CS3_SIZE 0x10000000U
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#define AT91SAM9261_CS4_BASE 0x50000000U
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#define AT91SAM9261_CS4_SIZE 0x10000000U
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#define AT91SAM9261_CS5_BASE 0x60000000U
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#define AT91SAM9261_CS5_SIZE 0x10000000U
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#define AT91SAM9261_CS6_BASE 0x70000000U
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#define AT91SAM9261_CS6_SIZE 0x10000000U
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#define AT91SAM9261_CS7_BASE 0x80000000U
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#define AT91SAM9261_CS7_SIZE 0x10000000U
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/* Virtual address for I/O space */
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#define AT91SAM9261_APB_VBASE 0xfff00000U
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#define AT91SAM9261_APB_HWBASE 0xfff00000U
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#define AT91SAM9261_APB_SIZE 0x00100000U
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/* Peripherals: */
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#include <arm/at91/at91pdcreg.h>
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#define AT91SAM9261_TC0_BASE 0xFFFA0000U
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#define AT91SAM9261_TC1_BASE 0xFFFA0040U
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#define AT91SAM9261_TC2_BASE 0xFFFA0080U
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#define AT91SAM9261_TCB012_BASE 0xFFFA00C0U
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#define AT91SAM9261_TC_SIZE 0x4000U
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//#include <arm/at91/at91tcreg.h>
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#define AT91SAM9261_UDP_BASE 0xFFFA4000U
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#define AT91SAM9261_UDP_SIZE 0x4000U
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//#include <arm/at91/at91udpreg.h>
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#define AT91SAM9261_MCI_BASE 0xFFFA8000U
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#define AT91SAM9261_TWI_BASE 0xFFFAC000U
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#include <arm/at91/at91twireg.h>
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#define AT91SAM9261_USART0_BASE 0xFFFB0000U
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#define AT91SAM9261_USART1_BASE 0xFFFB4000U
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#define AT91SAM9261_USART2_BASE 0xFFFB8000U
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#define AT91SAM9261_USART_SIZE 0x4000U
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#include <arm/at91/at91usartreg.h>
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#define AT91SAM9261_SSC0_BASE 0xFFFBC000U
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#define AT91SAM9261_SSC1_BASE 0xFFFC0000U
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#define AT91SAM9261_SSC2_BASE 0xFFFC4000U
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#define AT91SAM9261_SSC_SIZE 0x4000U
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//#include <arm/at91/at91sscreg.h>
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#define AT91SAM9261_SPI0_BASE 0xFFFC8000U
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#define AT91SAM9261_SPI1_BASE 0xFFFCC000U
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#define AT91SAM9261_SPI_SIZE 0x4000U
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#include <arm/at91/at91spireg.h>
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/* system controller: */
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#define AT91SAM9261_SDRAMC_BASE 0xFFFFEA00U
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#define AT91SAM9261_SDRAMC_SIZE 0x200U
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#define AT91SAM9261_SMC_BASE 0xFFFFEC00U
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#define AT91SAM9261_SMC_SIZE 0x200U
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#define AT91SAM9261_MATRIX_BASE 0xFFFFEE00U
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#define AT91SAM9216_MATRIX_SIZE 0x200U
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#define AT91SAM9261_AIC_BASE 0xFFFFF000U
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#define AT91SAM9261_AIC_SIZE 0x200U
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#include <arm/at91/at91aicreg.h>
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#define AT91SAM9261_DBGU_BASE 0xFFFFF200U
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#define AT91SAM9261_DBGU_SIZE 0x200U
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#include <arm/at91/at91dbgureg.h>
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#define AT91SAM9261_PIOA_BASE 0xFFFFF400U
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#define AT91SAM9261_PIOB_BASE 0xFFFFF600U
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#define AT91SAM9261_PIOC_BASE 0xFFFFF800U
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#define AT91SAM9261_PIO_SIZE 0x200U
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#define AT91_PIO_SIZE AT91SAM9261_PIO_SIZE // for generic AT91 code
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#include <arm/at91/at91pioreg.h>
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#define PIOA_READ(_reg) *((volatile uint32_t *)(AT91SAM9261_PIOA_BASE + (_reg)))
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#define PIOA_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9261_PIOA_BASE + (_reg))) = (_val);} while (0)
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#define PIOB_READ(_reg) *((volatile uint32_t *)(AT91SAM9261_PIOB_BASE + (_reg)))
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#define PIOB_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9261_PIOB_BASE + (_reg))) = (_val);} while (0)
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#define PIOC_READ(_reg) *((volatile uint32_t *)(AT91SAM9261_PIOC_BASE + (_reg)))
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#define PIOC_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9261_PIOC_BASE + (_reg))) = (_val);} while (0)
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#define AT91SAM9261_PMC_BASE 0xFFFFFC00U
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#define AT91SAM9261_PMC_SIZE 0x100U
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#include <arm/at91/at91pmcreg.h>
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#define AT91SAM9261_RSTC_BASE 0xFFFFFD00U
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#define AT91SAM9261_RSTC_SIZE 0x10U
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#define AT91SAM9261_SHDWC_BASE 0xFFFFFD10U
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#define AT91SAM9261_SHDWC_SIZE 0x10U
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#define AT91SAM9261_RTT_BASE 0xFFFFFD20U
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#define AT91SAM9261_RTT_SIZE 0x10U
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#define AT91SAM9261_PIT_BASE 0xFFFFFD30U
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#define AT91SAM9261_PIT_SIZE 0x10U
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#define AT91SAM9261_WDT_BASE 0xFFFFFD40U
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#define AT91SAM9261_WDTC_SIZE 0x10U
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#define AT91SAM9261_GPBR_BASE 0xFFFFFD50U
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#define AT91SAM9261_GPBR_SIZE 0x10U
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// peripheral identifiers:
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/* peripheral identifiers: */
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enum {
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PID_FIQ = 0, /* 0 */
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PID_SYSIRQ, /* 1 */
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PID_PIOA, /* 2 */
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PID_PIOB, /* 3 */
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PID_PIOC, /* 4 */
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PID_US0 = 6, /* 6 */
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PID_US1, /* 7 */
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PID_US2, /* 8 */
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PID_MCI, /* 9 */
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PID_UDP, /* 10 */
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PID_TWI, /* 11 */
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PID_SPI0, /* 12 */
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PID_SPI1, /* 13 */
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PID_SSC0, /* 14 */
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PID_SSC1, /* 15 */
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PID_SSC2, /* 16 */
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PID_TC0, /* 17 */
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PID_TC1, /* 18 */
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PID_TC2, /* 19 */
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PID_UHP, /* 20 */
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PID_LCDC, /* 21 */
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PID_IRQ0 = 29, /* 29 */
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PID_IRQ1, /* 30 */
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PID_IRQ2, /* 31 */
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};
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#endif /* _AT91SAM9261REG_H_ */
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