90 lines
4.0 KiB
C
90 lines
4.0 KiB
C
/* $Id: at91twireg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */
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/* $NetBSD: at91twireg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */
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/*-
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* Copyright (c) 2007 Embedtronics Oy.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* 3. All advertising materials mentioning features or use of this
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* software must display the following acknowledgements:
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* This product includes software developed by the Urbana-Champaign
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* Independent Media Center.
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* This product includes software developed by Garrett D'Amore.
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* 4. Urbana-Champaign Independent Media Center's name and Garrett
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* D'Amore's name may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT
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* MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT
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* MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _AT91TWIREG_H_
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#define _AT91TWIREG_H_
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#define AT91_TWI_SIZE 0x4000U
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#define TWI_CR 0x00U /* 0x00: Control Register */
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#define TWI_MMR 0x04U /* 0x04: Master Mode Register */
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#define TWI_IADR 0x0CU /* 0x0C: Internal Address Register */
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#define TWI_CWGR 0x10U /* 0x10: Clock Waveform Generator Reg */
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#define TWI_SR 0x20U /* 0x20: Status Register */
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#define TWI_IER 0x24U /* 0x24: Interrupt Enable Register */
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#define TWI_IDR 0x28U /* 0x28: Interrupt Disable Register */
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#define TWI_IMR 0x2CU /* 0x2C: Interrupt Mask Register */
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#define TWI_RHR 0x30U /* 0x30: Receive Holding Register */
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#define TWI_THR 0x34U /* 0x34: Transmit Holding Register */
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/* Control Registre bits: */
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#define TWI_CR_SWRST 0x80U /* 1 = do software reset */
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#define TWI_CR_MSDIS 0x08U /* 1 = disable master mode */
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#define TWI_CR_MSEN 0x04U /* 1 = enable master mode */
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#define TWI_CR_STOP 0x02U /* 1 = send a stop condition */
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#define TWI_CR_START 0x01U /* 1 = send a start condition */
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/* Master Mode Register bits: */
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#define TWI_MMR_DADR 0x7F0000U /* device address */
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#define TWI_MMR_DADR_SHIFT 16U
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#define TWI_MMR_MREAD 0x1000U /* 1 = Master read direction (0= write) */
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#define TWI_MMR_IADRSZ 0x300U /* device address size */
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#define TWI_MMR_IADRSZ_SHIFT 8U
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/* Clock Waveform Generator Register bits: */
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#define TWI_CWGR_CKDIV 0x70000U /* Clock Divider */
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#define TWI_CWGR_CKDIV_SHIFT 16U
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#define TWI_CWGR_CHDIV 0xFF00U /* Clock High Divider */
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#define TWI_CWGR_CHDIV_SHIFT 8U
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#define TWI_CWGR_CLDIV 0xFFU /* Clock Low Divider */
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#define TWI_CWGR_CLDIV_SHIFT 0U
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/* Status Register bits: */
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#define TWI_SR_NACK 0x100U /* 1 = not acknowledged */
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#define TWI_SR_UNRE 0x080U /* 1 = underrun error */
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#define TWI_SR_OVRE 0x040U /* 1 = overrun error */
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#define TWI_SR_TXRDY 0x004U /* 1 = transmit holding reg rdy */
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#define TWI_SR_RXRDY 0x002U /* 1 = receive hodling reg rdy */
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#define TWI_SR_TXCOMP 0x001U /* 1 = transmission completed */
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#endif /* _AT91TWIREG_H_ */
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