73 lines
3.1 KiB
C
73 lines
3.1 KiB
C
/* $NetBSD: at91aicreg.h,v 1.3 2009/10/23 06:53:13 snj Exp $ */
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/*
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* Copyright (c) 2007 Embedtronics Oy
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _AT91AICREG_H_
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#define _AT91AICREG_H_
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#define AT91AIC_BASE 0xFFFFF000UL /* AIC BUS address */
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#define AIC_NIRQ 32UL /* number of vectors */
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#define AIC_VEC_VALID(n) ((n) >= 0 && (n) < AIC_NIRQ)
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#define AIC_SMR(vec) (0x000UL+(vec)*4UL)/* Source Mode Registers */
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#define AIC_SVR(vec) (0x080UL+(vec)*4UL)/* Source Vectors Regs */
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#define AIC_IVR 0x100UL /* 100: Interrupt Vector Reg */
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#define AIC_FVR 0x104UL /* 104: Fast Interrupt Vect Reg */
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#define AIC_ISR 0x108UL /* 108: Interrupt Status Reg */
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#define AIC_IPR 0x10CUL /* 10c: Interrupt Pending Reg */
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#define AIC_IMR 0x110UL /* 110: Interrupt Mask Reg */
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#define AIC_CISR 0x114UL /* 114: Core interrupt Stat Reg */
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#define AIC_IECR 0x120UL /* 120: Interrupt Enable Cmd reg*/
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#define AIC_IDCR 0x124UL /* 124: Interrupt Dis. Cmd Reg */
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#define AIC_ICCR 0x128UL /* 128: Interrupt Clear Cmd Reg */
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#define AIC_ISCR 0x12CUL /* 12c: Interrupt Set Cmd Reg */
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#define AIC_EOICR 0x130UL /* 130: End of Interrupt Vec Reg*/
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#define AIC_SPU 0x134UL /* 134: Spurious Int. Vec Reg */
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#define AIC_DCR 0x138UL /* 138: Debug Control Reg */
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#define AIC_FFER 0x140UL /* 140: Fast Forcing Enable */
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#define AIC_FFDR 0x144UL /* 144: Fast Forcing Disable */
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#define AIC_FFSR 0x148UL /* 148: Fast Forcing Status */
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/* Source Mode Register bits: */
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#define AIC_SMR_SRCTYPE 0x60
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#define AIC_SMR_SRCTYPE_LVL_LO 0x00
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#define AIC_SMR_SRCTYPE_FALLING 0x20
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#define AIC_SMR_SRCTYPE_LEVEL 0x00
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#define AIC_SMR_SRCTYPE_EDGE 0x20
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#define AIC_SMR_SRCTYPE_LVL_HI 0x40
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#define AIC_SMR_SRCTYPE_RISING 0x60
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#define AIC_SMR_PRIOR 0x7
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#define AIC_SMR_PRIOR_SHIFT 0
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/* Debug Control Register: */
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#define AIC_DEBUG_GMSK 0x2 /* 1= mask all interrupts (?) */
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#define AIC_DEBUG_PROT 0x1 /* 1 = protection mode enabled */
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#endif // _AT91AICREG_H_
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