363 lines
9.2 KiB
C
363 lines
9.2 KiB
C
/* $NetBSD: apecs_pci.c,v 1.3 1995/08/03 01:16:57 cgd Exp $ */
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/*
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* Copyright (c) 1995 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <vm/vm.h>
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#include <machine/autoconf.h>
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#include <machine/pio.h>
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#include <dev/isa/isavar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <alpha/pci/pci_chipset.h>
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#include <alpha/pci/apecsreg.h>
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void apecs_setup __P((void));
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pcitag_t apecs_make_tag __P((int, int, int));
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pcireg_t apecs_conf_read __P((pcitag_t, int));
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void apecs_conf_write __P((pcitag_t, int, pcireg_t));
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int apecs_map_io __P((pcitag_t, int, int *));
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int apecs_map_mem __P((pcitag_t, int, vm_offset_t *, vm_offset_t *));
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int apecs_pcidma_map __P((caddr_t, vm_size_t, vm_offset_t *));
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void apecs_pcidma_unmap __P((caddr_t, vm_size_t, int, vm_offset_t *));
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struct pci_cs_fcns apecs_p1e_cs_fcns = { /* XXX WHAT'S DIFFERENT? */
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apecs_setup,
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apecs_make_tag,
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apecs_conf_read,
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apecs_conf_write,
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apecs_map_io,
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apecs_map_mem,
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apecs_pcidma_map,
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apecs_pcidma_unmap,
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};
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struct pci_cs_fcns apecs_p2e_cs_fcns = { /* XXX WHAT'S DIFFERENT? */
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apecs_setup,
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apecs_make_tag,
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apecs_conf_read,
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apecs_conf_write,
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apecs_map_io,
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apecs_map_mem,
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apecs_pcidma_map,
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apecs_pcidma_unmap,
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};
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#define REGVAL(r) (*(u_int32_t *)phystok0seg(r))
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void
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apecs_setup()
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{
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/*
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* Set up PCI bus mastering DMA windows on the APECS chip.
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*
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* What the PROM wants:
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* a 1G direct-mapped window that maps the PCI address
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* space from 4G -> 5G to memory addresses 0 -> 1G,
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* set up in window two.
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*
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* What we want:
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* a 1G direct-mapped window that maps the PCI address
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* space from 0 -> 1G to memory addresses 0 -> 1G.
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*
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* Unless we satisfy the PROM, we can't live through a reboot.
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* If we don't do what we want, I have to write more code.
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* So:
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* Leave window two alone, map window 1 the way I want it.
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*
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* XXX verify that windows don't overlap
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* XXX be trickier
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* XXX magic numbers
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*/
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#if 0 /* should be routine to dump regs */
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printf("old base1 was 0x%x\n", REGVAL(EPIC_PCI_BASE_1));
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printf("old mask1 was 0x%x\n", REGVAL(EPIC_PCI_MASK_1));
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printf("old tbase1 was 0x%x\n", REGVAL(EPIC_TBASE_1));
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printf("old base2 was 0x%x\n", REGVAL(EPIC_PCI_BASE_2));
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printf("old mask2 was 0x%x\n", REGVAL(EPIC_PCI_MASK_2));
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printf("old tbase2 was 0x%x\n", REGVAL(EPIC_TBASE_2));
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#endif
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#if 0 /* XXX STUPID PROM; MUST LEAVE WINDOW 2 ALONE. See above */
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/* Turn off DMA window enables in PCI Base Reg 2. */
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REGVAL(EPIC_PCI_BASE_2) = 0;
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/* Set up Translated Base Register 2; translate to sybBus addr 0. */
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REGVAL(EPIC_TBASE_2) = 0;
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/* Set up PCI mask register 2; map 1G space. */
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REGVAL(EPIC_PCI_MASK_2) = 0x3ff00000;
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/* Enable window 2; from PCI address 4G, direct mapped. */
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REGVAL(EPIC_PCI_BASE_2) = 0x40080000;
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#endif /* STUPID PROM */
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/* Turn off DMA window enables in PCI Base Reg 1. */
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REGVAL(EPIC_PCI_BASE_1) = 0;
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/* Set up Translated Base Register 1; translate to sybBus addr 0. */
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{ /* XXX */
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extern struct sgmapent *sgmap;
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REGVAL(EPIC_TBASE_1) = vtophys(sgmap) >> 1;
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} /* XXX */
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/* Set up PCI mask register 1; map 8MB space. */
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REGVAL(EPIC_PCI_MASK_1) = 0x00700000;
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/* Enable window 1; from PCI address 8MB, direct mapped. */
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REGVAL(EPIC_PCI_BASE_1) = 0x008c0000;
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/*
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* Should set up HAXR1 and HAXR2... However, the PROM again
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* wants them where they're set to be...
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*/
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#if 0
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printf("old haxr0 was 0x%x\n", REGVAL(EPIC_HAXR0));
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printf("old haxr1 was 0x%x\n", REGVAL(EPIC_HAXR1));
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printf("old haxr2 was 0x%x\n", REGVAL(EPIC_HAXR2));
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#endif
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#if 0 /* XXX STUPID PROM */
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/* HAXR0 is wired zero; no op. */
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REGVAL(EPIC_HAXR0) = 0;
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/* HAXR1: maps PCI memory space above 16M. 16M -> 2G+16M. */
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REGVAL(EPIC_HAXR1) = 0x80000000;
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/* HAXR2: maps PCI I/O space above 256K. 256K -> 256k. */
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REGVAL(EPIC_HAXR2) = 0;
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#endif
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}
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pcitag_t
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apecs_make_tag(bus, device, function)
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int bus, device, function;
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{
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pcitag_t tag;
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if (bus >= 256 || device >= 32 || function >= 8)
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panic("apecs_make_tag: bad request");
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tag = (bus << 21) | (device << 16) | (function << 13);
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#if 0
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printf("apecs_make_tag: bus %d, device %d, function %d -> 0x%lx\n", bus,
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device, function, tag);
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#endif
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return tag;
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}
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pcireg_t
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apecs_conf_read(tag, offset)
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pcitag_t tag;
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int offset; /* XXX */
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{
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pcireg_t *datap, data;
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int reg = offset >> 2; /* XXX */
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if ((tag & 0x1fe00000) != 0) {
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panic("apecs_conf_read: bus != 0?");
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}
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/* XXX FILL IN HAXR2 bits. */
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datap = (pcireg_t *)
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phystok0seg(APECS_PCI_CONF | tag | reg << 7 | 0 << 5 | 0x3 << 3);
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if (badaddr(datap, sizeof *datap))
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return ((pcireg_t)-1);
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data = *datap;
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#if 0
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printf("apecs_conf_read: tag 0x%lx, reg 0x%lx -> %x @ %p\n", tag, reg,
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data, datap);
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#endif
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return data;
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}
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void
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apecs_conf_write(tag, offset, data)
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pcitag_t tag;
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int offset; /* XXX */
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pcireg_t data;
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{
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pcireg_t *datap;
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int reg = offset >> 2; /* XXX */
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if ((tag & 0x1fe00000) != 0) {
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panic("apecs_conf_read: bus != 0?");
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}
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/* XXX FILL IN HAXR2 bits. */
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datap = (pcireg_t *)
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phystok0seg(APECS_PCI_CONF | tag | reg << 7 | 0 << 5 | 0x3 << 3);
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#if 0
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printf("apecs_conf_write: tag 0x%lx, reg 0x%lx -> 0x%x @ %p\n", tag,
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reg, data, datap);
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#endif
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*datap = data;
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}
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int
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apecs_map_io(tag, reg, iobasep)
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pcitag_t tag;
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int reg;
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int *iobasep;
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{
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pcireg_t data;
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int pci_iobase;
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if (reg < PCI_MAP_REG_START || reg >= PCI_MAP_REG_END || (reg & 3))
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panic("apecs_map_io: bad request");
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data = pci_conf_read(tag, reg);
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if ((data & PCI_MAP_IO) == 0)
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panic("apecs_map_io: attempt to I/O map an memory region");
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/* figure out where it was mapped... */
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pci_iobase = data & PCI_MAP_MEMORY_ADDRESS_MASK; /* PCI I/O addr */
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return (pci_iobase);
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}
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int
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apecs_map_mem(tag, reg, vap, pap)
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pcitag_t tag;
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int reg;
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vm_offset_t *vap, *pap;
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{
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pcireg_t data;
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vm_offset_t pci_pa, sb_pa;
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if (reg < PCI_MAP_REG_START || reg >= PCI_MAP_REG_END || (reg & 3))
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panic("apecs_map_mem: bad request");
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/*
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* "HERE WE GO AGAIN!!!"
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*
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* The PROM has already mapped the device for us. The PROM is
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* our friend. We wouldn't want to make the PROM unhappy.
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*
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* So, we take the address that's been assigned (already) to
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* the register, and figure out what physical and virtual addresses
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* go with it...
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*/
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/*
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* Section 6.2.5.1, `Address Maps', says that a device which wants 2^n
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* bytes of memory will hardwire the bottom n bits of the address to 0.
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* As recommended, we write all 1s and see what we get back.
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*/
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data = pci_conf_read(tag, reg);
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if (data & PCI_MAP_IO)
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panic("apecs_map_mem: attempt to memory map an I/O region");
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switch (data & PCI_MAP_MEMORY_TYPE_MASK) {
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case PCI_MAP_MEMORY_TYPE_32BIT:
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break;
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case PCI_MAP_MEMORY_TYPE_32BIT_1M:
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printf("apecs_map_mem: attempt to map restricted 32-bit region\n");
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return EOPNOTSUPP;
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case PCI_MAP_MEMORY_TYPE_64BIT:
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printf("apecs_map_mem: attempt to map 64-bit region\n");
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return EOPNOTSUPP;
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default:
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printf("apecs_map_mem: reserved mapping type\n");
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return EINVAL;
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}
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/* figure out where it was mapped... */
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pci_pa = data & PCI_MAP_MEMORY_ADDRESS_MASK; /* PCI bus address */
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/* calcluate sysBus address -- should be a better way to get space */
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if (data & PCI_MAP_MEMORY_CACHABLE) {
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/* Dense space */
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sb_pa = (pci_pa & 0xffffffff) | (3L << 32); /* XXX */
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} else {
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/* Sparse space */
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sb_pa = ((pci_pa & 0x7ffffff) << 5) | (2L << 32); /* XXX */
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}
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/* and tell the driver. */
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*vap = phystok0seg(sb_pa);
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*pap = pci_pa;
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#if 0
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printf("pci_map_mem: memory mapped at 0x%lx\n", *pap);
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printf("pci_map_mem: virtual 0x%lx\n", *vap);
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#endif
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return 0;
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}
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int
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apecs_pcidma_map(addr, size, mappings)
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caddr_t addr;
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vm_size_t size;
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vm_offset_t *mappings;
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{
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vm_offset_t va;
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long todo;
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int i;
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i = 0;
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va = (vm_offset_t)addr;
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todo = size;
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while (todo > 0) {
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mappings[i] = vtophys(va) | 0x40000000;
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#if 0
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printf("a_pd_m mapping %d: %lx -> %lx -> %lx\n", i, va,
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vtophys(va), mappings[i]);
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#endif
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i++;
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todo -= PAGE_SIZE - (va - trunc_page(va));
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va += PAGE_SIZE - (va - trunc_page(va));
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}
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return (i);
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}
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void
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apecs_pcidma_unmap(addr, size, nmappings, mappings)
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caddr_t addr;
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vm_size_t size;
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int nmappings;
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vm_offset_t *mappings;
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{
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/* maybe XXX if diagnostic, check that mapping happened. */
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printf("apecs_pcidma_unmap: nada\n");
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}
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