243 lines
7.3 KiB
C
243 lines
7.3 KiB
C
/* $NetBSD: cac_pci.c,v 1.6 2000/09/26 11:38:47 ad Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Andrew Doran.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* PCI front-end for cac(4) driver.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/queue.h>
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#include <sys/proc.h>
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#include <sys/buf.h>
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#include <machine/endian.h>
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#include <machine/bus.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pcivar.h>
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#include <dev/ic/cacreg.h>
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#include <dev/ic/cacvar.h>
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#define PCI_CBIO 0x10 /* Configuration base I/O address */
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#define PCI_CBMA 0x14 /* Configuration base memory address */
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static void cac_pci_attach(struct device *, struct device *, void *);
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static int cac_pci_match(struct device *, struct cfdata *, void *);
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static struct cac_ccb *cac_pci_l0_completed(struct cac_softc *);
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static int cac_pci_l0_fifo_full(struct cac_softc *);
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static void cac_pci_l0_intr_enable(struct cac_softc *, int);
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static int cac_pci_l0_intr_pending(struct cac_softc *);
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static void cac_pci_l0_submit(struct cac_softc *, struct cac_ccb *);
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struct cfattach cac_pci_ca = {
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sizeof(struct cac_softc), cac_pci_match, cac_pci_attach
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};
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static struct cac_linkage cac_pci_l0 = {
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cac_pci_l0_completed,
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cac_pci_l0_fifo_full,
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cac_pci_l0_intr_enable,
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cac_pci_l0_intr_pending,
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cac_pci_l0_submit
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};
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#define CT_IOMAP 0x01 /* Use I/O port access */
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#define CT_STARTFW 0x02 /* Need to start controller firmware */
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struct cac_pci_type {
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int ct_subsysid;
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int ct_flags;
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struct cac_linkage *ct_linkage;
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char *ct_typestr;
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} static cac_pci_type[] = {
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{ 0x3040110e, CT_IOMAP, &cac_l0, "SMART-2/E" },
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{ 0x40300e11, 0, &cac_l0, "SMART-2/P" },
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{ 0x40310e11, 0, &cac_l0, "SMART-2SL" },
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{ 0x40320e11, 0, &cac_l0, "Smart Array 3200" },
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{ 0x40330e11, 0, &cac_l0, "Smart Array 3100ES" },
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{ 0x40340e11, 0, &cac_l0, "Smart Array 221" },
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{ 0x40400e11, CT_STARTFW, &cac_pci_l0, "Integrated Array" },
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{ 0x40480e11, CT_STARTFW, &cac_pci_l0, "RAID LC2" },
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{ 0x40500e11, 0, &cac_pci_l0, "Smart Array 4200" },
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{ 0x40510e11, 0, &cac_pci_l0, "Smart Array 4200ES" },
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{ 0x40580e11, 0, &cac_pci_l0, "Smart Array 431" },
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{ 0, 0, &cac_l0, NULL },
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};
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static int
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cac_pci_match(struct device *parent, struct cfdata *match, void *aux)
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{
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struct pci_attach_args *pa;
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pa = (struct pci_attach_args *)aux;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_COMPAQ &&
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_COMPAQ_SMART2P)
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return (1);
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_DEC &&
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_DEC_CPQ42XX)
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return (1);
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return (0);
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}
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static void
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cac_pci_attach(struct device *parent, struct device *self, void *aux)
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{
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struct pci_attach_args *pa;
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struct cac_pci_type *ct;
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struct cac_softc *sc;
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pci_chipset_tag_t pc;
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pci_intr_handle_t ih;
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const char *intrstr;
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pcireg_t csr, subsysid;
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int flags;
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sc = (struct cac_softc *)self;
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pa = (struct pci_attach_args *)aux;
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pc = pa->pa_pc;
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subsysid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
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for (ct = cac_pci_type; ct->ct_subsysid != 0; ct++)
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if (subsysid == ct->ct_subsysid)
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break;
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if (((flags = ct->ct_flags) & CT_IOMAP) == 0)
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if (pci_mapreg_map(pa, PCI_CBMA, PCI_MAPREG_TYPE_MEM, 0,
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&sc->sc_iot, &sc->sc_ioh, NULL, NULL))
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flags |= CT_IOMAP;
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if ((flags & CT_IOMAP) != 0)
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if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0,
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&sc->sc_iot, &sc->sc_ioh, NULL, NULL)) {
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printf("can't map i/o space\n");
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return;
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}
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sc->sc_dmat = pa->pa_dmat;
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/* Enable the device. */
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csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
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pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
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csr | PCI_COMMAND_MASTER_ENABLE);
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/* Map and establish the interrupt. */
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if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin,
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pa->pa_intrline, &ih)) {
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printf("can't map interrupt\n");
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return;
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}
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intrstr = pci_intr_string(pc, ih);
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sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, cac_intr, sc);
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if (sc->sc_ih == NULL) {
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printf("can't establish interrupt");
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if (intrstr != NULL)
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printf(" at %s", intrstr);
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printf("\n");
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return;
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}
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printf(": Compaq ");
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if (ct->ct_typestr == NULL) {
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printf("array controller\n%s: unknown subsystem ID: 0x%08x\n",
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sc->sc_dv.dv_xname, (u_int)subsysid);
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} else
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printf("%s\n", ct->ct_typestr);
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/* Now attach to the bus-independent code. */
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sc->sc_cl = ct->ct_linkage;
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cac_init(sc, intrstr, (flags & CT_STARTFW) != 0);
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}
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static void
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cac_pci_l0_submit(struct cac_softc *sc, struct cac_ccb *ccb)
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{
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bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, (caddr_t)ccb - sc->sc_ccbs,
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sizeof(struct cac_ccb), BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
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cac_outl(sc, CAC_42REG_CMD_FIFO, ccb->ccb_paddr);
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}
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static struct cac_ccb *
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cac_pci_l0_completed(struct cac_softc *sc)
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{
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struct cac_ccb *ccb;
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u_int32_t off;
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if ((off = cac_inl(sc, CAC_42REG_DONE_FIFO)) == 0xffffffffU)
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return (0);
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cac_outl(sc, CAC_42REG_DONE_FIFO, 0);
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off = (off & ~3) - sc->sc_ccbs_paddr;
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ccb = (struct cac_ccb *)(sc->sc_ccbs + off);
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bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, off, sizeof(struct cac_ccb),
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BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
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return (ccb);
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}
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static int
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cac_pci_l0_intr_pending(struct cac_softc *sc)
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{
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return (cac_inl(sc, CAC_42REG_INTR_PENDING) &
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cac_inl(sc, CAC_42REG_STATUS));
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}
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static void
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cac_pci_l0_intr_enable(struct cac_softc *sc, int state)
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{
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cac_outl(sc, CAC_42REG_INTR_MASK, (state ? 0 : 8)); /* XXX */
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}
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static int
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cac_pci_l0_fifo_full(struct cac_softc *sc)
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{
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return (~cac_inl(sc, CAC_42REG_CMD_FIFO));
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}
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